Conferences in DBLP
Andrew B. Kahng , Stefanus Mantik , Dirk Stroobandt Requirements for models of achievable routing. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Jie Fang , Kei-Yong Khoo DUNE: a multi-layer gridless routing system with wire planning. [Citation Graph (0, 0)][DBLP ] Conf ] Christoph Albrecht Provably good global routing by a new approximation algorithm for multicommodity flow. [Citation Graph (0, 0)][DBLP ] Conf ] Frank Schmiedle , Daniel Unruh , Bernd Becker Exact switchbox routing with search space reduction. [Citation Graph (0, 0)][DBLP ] Conf ] I-Min Liu , Tan-Li Chou , Adnan Aziz , D. F. Wong Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion. [Citation Graph (0, 0)][DBLP ] Conf ] Naveed A. Sherwani The bottom-10 problems in EDA (panel session (title only)). [Citation Graph (0, 0)][DBLP ] Conf ] Chin-Chih Chang , Jason Cong Pseudo pin assignment with crosstalk noise control. [Citation Graph (0, 0)][DBLP ] Conf ] Lauren Hui Chen , Malgorzata Marek-Sadowska Aggressor alignment for worst-case coupling noise. [Citation Graph (0, 0)][DBLP ] Conf ] Lei He , Kevin M. Lepak Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization. [Citation Graph (0, 0)][DBLP ] Conf ] Rony Kay , Rob A. Rutenbar Wire packing: a strong formulation of crosstalk-aware chip-level track/layer assignment with an efficient integer programming solution. [Citation Graph (0, 0)][DBLP ] Conf ] Charles J. Alpert , Anirudh Devgan , Chandramouli V. Kashyap A two moment RC delay metric for performance optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Rob A. Rutenbar , John M. Cohn Layout tools for analog ICs and mixed-signal SoCs: a survey. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Majid Sarrafzadeh Incremental physical design. [Citation Graph (0, 0)][DBLP ] Conf ] Utpal Desai , Simon Tam , Robert Kim , Ji Zhang , Stefan Rusu Itanium processor clock design. [Citation Graph (0, 0)][DBLP ] Conf ] Rory McInerney , Kurt Leeper , Troy Hill , Heming Chan , Bulent Basaran , Lance McQuiddy Methodology for repeater insertion management in the RTL, layout, floorplan and fullchip timing databases of the Itanium microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Hai Zhou , Adnan Aziz Buffer minimization in pass transistor logic. [Citation Graph (0, 0)][DBLP ] Conf ] Masanori Hashimoto , Hidetoshi Onodera A performance optimization method by gate sizing using statistical static timing analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Li-Fu Chang , Keh-Jeng Chang , Robert Mathews Simulating frequency-dependent current distribution for inductance modeling of on-chip copper interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Suresh Raman , Sachin S. Sapatnekar , Charles J. Alpert Datapath routing based on a decongestion metric. [Citation Graph (0, 0)][DBLP ] Conf ] Iris Hui-Ru Jiang , Song-Ra Pan , Yao-Wen Chang , Jing-Yang Jou Optimal reliable crosstalk-driven interconnect optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Yu-Yen Mo , Chris C. N. Chu A hybrid dynamic/quadratic programming algorithm for interconnect tree optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Evanthia Papadopoulou Critical area computation for missing material defects in VLSI circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Maogang Wang , Xiaojian Yang , Kenneth Eguro , Majid Sarrafzadeh Multi-center congestion estimation and minimization during placement. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaojian Yang , Maogang Wang , Kenneth Eguro , Majid Sarrafzadeh A snap-on placement tool. [Citation Graph (0, 0)][DBLP ] Conf ] Masahiko Toyonaga , Keiichi Kurokawa , Takuya Yasui , Atsushi Takahashi A practical clock tree synthesis for semi-synchronous circuits. [Citation Graph (0, 0)][DBLP ] Conf ] D. Hill , Mark Gilbreath , Wayne Heideman , J. George Janac , Adriaan Ligtenberg EDA and the Internet (panel session - title only). [Citation Graph (0, 0)][DBLP ] Conf ] Yingxin Pang , Chung-Kuan Cheng , Takeshi Yoshimura An enhanced perturbing algorithm for floorplan design using the O-tree representation. [Citation Graph (0, 0)][DBLP ] Conf ] Fung Yu Young , Chris C. N. Chu , W. S. Luk , Y. C. Wong Floorplan area minimization using Lagrangian relaxation. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaoping Tang , D. F. Wong Planning buffer locations by network flows. [Citation Graph (0, 0)][DBLP ] Conf ] Probir Sarkar , Vivek Sundararaman , Cheng-Kok Koh Routability-driven repeater block planning for interconnect-centric floorplanning. [Citation Graph (0, 0)][DBLP ] Conf ] Min Ouyang , Michel Toulouse , Krishnaiyan Thulasiraman , Fred Glover , Jitender S. Deogun Multilevel cooperative search: application to the circuit/hypergraph partitioning problem. [Citation Graph (0, 0)][DBLP ] Conf ] Ralph H. J. M. Otten What is a floorplan?. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew B. Kahng Classical floorplanning harmful? [Citation Graph (0, 0)][DBLP ] Conf ] Patrick Groeneveld , Jacob Greidinger , J. George Janac , Wilm E. Donath The right floorplanning formulations for future chip implementation methodologies (panel discussion - title only). [Citation Graph (0, 0)][DBLP ] Conf ] 