
Conferences in DBLP
 Nancy Nettleton, Wolfgang Roethig, D. Hill, Majid Sarrafzadeh
Differences in ASIC, COT and processor design (panel). [Citation Graph (0, 0)][DBLP] ISPD, 2001, pp:2 [Conf]
 Charles J. Alpert, Milos Hrkic, Jiang Hu, Andrew B. Kahng, John Lillis, Bao Liu, Stephen T. Quay, Sachin S. Sapatnekar, A. J. Sullivan, Paul Villarrubia
Buffered Steiner trees for difficult instances. [Citation Graph (0, 0)][DBLP] ISPD, 2001, pp:49 [Conf]
 Ryan Kastner, Elaheh Bozorgzadeh, Majid Sarrafzadeh
An exact algorithm for couplingfree routing. [Citation Graph (0, 0)][DBLP] ISPD, 2001, pp:1015 [Conf]
 Tao Lin, Lawrence T. Pileggi
RC(L) interconnect sizing with second order considerations via posynomial programming. [Citation Graph (0, 0)][DBLP] ISPD, 2001, pp:1621 [Conf]
 YihChih Chou, YounLong Lin
A performancedriven standardcell placer based on a modified forcedirected algorithm. [Citation Graph (0, 0)][DBLP] ISPD, 2001, pp:2429 [Conf]
 Patrick H. Madden
Reporting of standard cell placement results. [Citation Graph (0, 0)][DBLP] ISPD, 2001, pp:3035 [Conf]
 FookLuen Heng, Lars Liebmann, Jennifer Lund
Application of automated design migration to alternating phase shift mask design. [Citation Graph (0, 0)][DBLP] ISPD, 2001, pp:3843 [Conf]
 Warren Grobman, Robert Boone, Cece Philbin, Bob Jarvis
Reticle enhancement technology trends: resource and manufacturability implications for the implementation of physical designs. [Citation Graph (0, 0)][DBLP] ISPD, 2001, pp:4551 [Conf]
 Franklin M. Schellenberg, Luigi Capodieci
Impact of RET on physical layouts. [Citation Graph (0, 0)][DBLP] ISPD, 2001, pp:5255 [Conf]
 Stephen P. Boyd, Lieven Vandenberghe, Abbas El Gamal, Sunghee Yun
Design of robust global power and ground networks. [Citation Graph (0, 0)][DBLP] ISPD, 2001, pp:6065 [Conf]
 Shiyou Zhao, Kaushik Roy, ChengKok Koh
Decoupling capacitance allocation for power supply noise suppression. [Citation Graph (0, 0)][DBLP] ISPD, 2001, pp:6671 [Conf]
 Andrew R. Conn, Chandramouli Visweswariah
Overview of continuous optimization advances and applications to circuit tuning. [Citation Graph (0, 0)][DBLP] ISPD, 2001, pp:7481 [Conf]
 Majid Sarrafzadeh, Elaheh Bozorgzadeh, Ryan Kastner, Ankur Srivastava
Design and analysis of physical design algorithms. [Citation Graph (0, 0)][DBLP] ISPD, 2001, pp:8289 [Conf]
 Phillip Restle, Albert E. Ruehli, Steven G. Walker
MultiGHz interconnect effects in microprocessors. [Citation Graph (0, 0)][DBLP] ISPD, 2001, pp:9397 [Conf]
 WaiKei Mak
Mincut partitioning with functional replication for technology mapped circuits using minimum area overhead. [Citation Graph (0, 0)][DBLP] ISPD, 2001, pp:100105 [Conf]
 Fei Li, Lei He
Maximum current estimation considering power gating. [Citation Graph (0, 0)][DBLP] ISPD, 2001, pp:106111 [Conf]
 Jinan Lou, Shankar Krishnamoorthy, Henry S. Sheng
Estimating routing congestion using probabilistic analysis. [Citation Graph (0, 0)][DBLP] ISPD, 2001, pp:112117 [Conf]
 Ruiqi Tian, Xiaoping Tang, D. F. Wong
Dummy feature placement for chemicalmechanical polishing uniformity in a shallow trench isolation process. [Citation Graph (0, 0)][DBLP] ISPD, 2001, pp:118123 [Conf]
 EnCheng Liu, MingShiun Lin, Jianbang Lai, TingChi Wang
Slicing floorplan design with boundaryconstrained modules. [Citation Graph (0, 0)][DBLP] ISPD, 2001, pp:124129 [Conf]
 Sabyasachi Das, Sunil P. Khatri
A regularitydriven fast gridless detailed router for high frequency datapath designs. [Citation Graph (0, 0)][DBLP] ISPD, 2001, pp:130135 [Conf]
 Bo Yao, Hongyu Chen, ChungKuan Cheng, Ronald L. Graham
Revisiting floorplan representations. [Citation Graph (0, 0)][DBLP] ISPD, 2001, pp:138143 [Conf]
 Shigetoshi Nakatake, Yukiko Kubo, Yoji Kajitani
Consistent floorplanning with super hierarchical constraints. [Citation Graph (0, 0)][DBLP] ISPD, 2001, pp:144149 [Conf]
 Shuo Zhou, Sheqin Dong, ChungKuan Cheng, Jun Gu
ECBL: an extended corner block list with solution space including optimum placement. [Citation Graph (0, 0)][DBLP] ISPD, 2001, pp:150155 [Conf]
 Yingxin Pang, ChungKuan Cheng, Koen Lampaert, Weize Xie
Rectilinear block packing using Otree representation. [Citation Graph (0, 0)][DBLP] ISPD, 2001, pp:156161 [Conf]
 Xiaojian Yang, Ryan Kastner, Majid Sarrafzadeh
Congestion estimation during topdown placement. [Citation Graph (0, 0)][DBLP] ISPD, 2001, pp:164169 [Conf]
 Yangdong Deng, Wojciech Maly
Interconnect characteristics of 2.5D system integration scheme. [Citation Graph (0, 0)][DBLP] ISPD, 2001, pp:171175 [Conf]
 WeiJin Dai
Hierarchical physical design methodology for multimillion gate chips. [Citation Graph (0, 0)][DBLP] ISPD, 2001, pp:179181 [Conf]
 Padmini Gopalakrishnan, Altan Odabasioglu, Lawrence T. Pileggi, Salil Raje
Overcoming wireload model uncertainty during physical design. [Citation Graph (0, 0)][DBLP] ISPD, 2001, pp:182189 [Conf]
 Zhaoyun Xing, Russell Kao
A minimum cost path search algorithm through tile obstacles. [Citation Graph (0, 0)][DBLP] ISPD, 2001, pp:192197 [Conf]
 Kolja Sulimma, Wolfgang Kunz
An exact algorithm for solving difficult detailed routing problems. [Citation Graph (0, 0)][DBLP] ISPD, 2001, pp:198203 [Conf]
 Ankireddy Nalamalpu, Wayne Burleson
Boosters for driving long onchip interconnects: design issues, interconnect synthesis and comparison with repeaters. [Citation Graph (0, 0)][DBLP] ISPD, 2001, pp:204211 [Conf]
 Rajeev Jayaraman
Physical design for FPGAs. [Citation Graph (0, 0)][DBLP] ISPD, 2001, pp:214221 [Conf]
 GiJoon Nam, Fadi A. Aloul, Karem A. Sakallah, Rob A. Rutenbar
A comparative study of two Boolean formulations of FPGA detailed routing constraints. [Citation Graph (0, 0)][DBLP] ISPD, 2001, pp:222227 [Conf]
 Kaustav Banerjee, Massoud Pedram, Amir H. Ajami
Analysis and optimization of thermal issues in highperformance VLSI. [Citation Graph (0, 0)][DBLP] ISPD, 2001, pp:230237 [Conf]
 TingYuan Wang, Charlie ChungPing Chen
ThermalADI: a lineartime chiplevel dynamic thermal simulation algorithm based on alternatingdirectionimplicit (ADI) method. [Citation Graph (0, 0)][DBLP] ISPD, 2001, pp:238243 [Conf]
