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Conferences in DBLP

International Symposium on Physical Design (ISPD) (ispd)
2001 (conf/ispd/2001)

  1. Nancy Nettleton, Wolfgang Roethig, D. Hill, Majid Sarrafzadeh
    Differences in ASIC, COT and processor design (panel). [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:2- [Conf]
  2. Charles J. Alpert, Milos Hrkic, Jiang Hu, Andrew B. Kahng, John Lillis, Bao Liu, Stephen T. Quay, Sachin S. Sapatnekar, A. J. Sullivan, Paul Villarrubia
    Buffered Steiner trees for difficult instances. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:4-9 [Conf]
  3. Ryan Kastner, Elaheh Bozorgzadeh, Majid Sarrafzadeh
    An exact algorithm for coupling-free routing. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:10-15 [Conf]
  4. Tao Lin, Lawrence T. Pileggi
    RC(L) interconnect sizing with second order considerations via posynomial programming. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:16-21 [Conf]
  5. Yih-Chih Chou, Youn-Long Lin
    A performance-driven standard-cell placer based on a modified force-directed algorithm. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:24-29 [Conf]
  6. Patrick H. Madden
    Reporting of standard cell placement results. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:30-35 [Conf]
  7. Fook-Luen Heng, Lars Liebmann, Jennifer Lund
    Application of automated design migration to alternating phase shift mask design. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:38-43 [Conf]
  8. Warren Grobman, Robert Boone, Cece Philbin, Bob Jarvis
    Reticle enhancement technology trends: resource and manufacturability implications for the implementation of physical designs. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:45-51 [Conf]
  9. Franklin M. Schellenberg, Luigi Capodieci
    Impact of RET on physical layouts. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:52-55 [Conf]
  10. Stephen P. Boyd, Lieven Vandenberghe, Abbas El Gamal, Sunghee Yun
    Design of robust global power and ground networks. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:60-65 [Conf]
  11. Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh
    Decoupling capacitance allocation for power supply noise suppression. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:66-71 [Conf]
  12. Andrew R. Conn, Chandramouli Visweswariah
    Overview of continuous optimization advances and applications to circuit tuning. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:74-81 [Conf]
  13. Majid Sarrafzadeh, Elaheh Bozorgzadeh, Ryan Kastner, Ankur Srivastava
    Design and analysis of physical design algorithms. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:82-89 [Conf]
  14. Phillip Restle, Albert E. Ruehli, Steven G. Walker
    Multi-GHz interconnect effects in microprocessors. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:93-97 [Conf]
  15. Wai-Kei Mak
    Min-cut partitioning with functional replication for technology mapped circuits using minimum area overhead. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:100-105 [Conf]
  16. Fei Li, Lei He
    Maximum current estimation considering power gating. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:106-111 [Conf]
  17. Jinan Lou, Shankar Krishnamoorthy, Henry S. Sheng
    Estimating routing congestion using probabilistic analysis. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:112-117 [Conf]
  18. Ruiqi Tian, Xiaoping Tang, D. F. Wong
    Dummy feature placement for chemical-mechanical polishing uniformity in a shallow trench isolation process. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:118-123 [Conf]
  19. En-Cheng Liu, Ming-Shiun Lin, Jianbang Lai, Ting-Chi Wang
    Slicing floorplan design with boundary-constrained modules. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:124-129 [Conf]
  20. Sabyasachi Das, Sunil P. Khatri
    A regularity-driven fast gridless detailed router for high frequency datapath designs. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:130-135 [Conf]
  21. Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Ronald L. Graham
    Revisiting floorplan representations. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:138-143 [Conf]
  22. Shigetoshi Nakatake, Yukiko Kubo, Yoji Kajitani
    Consistent floorplanning with super hierarchical constraints. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:144-149 [Conf]
  23. Shuo Zhou, Sheqin Dong, Chung-Kuan Cheng, Jun Gu
    ECBL: an extended corner block list with solution space including optimum placement. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:150-155 [Conf]
  24. Yingxin Pang, Chung-Kuan Cheng, Koen Lampaert, Weize Xie
    Rectilinear block packing using O-tree representation. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:156-161 [Conf]
  25. Xiaojian Yang, Ryan Kastner, Majid Sarrafzadeh
    Congestion estimation during top-down placement. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:164-169 [Conf]
  26. Yangdong Deng, Wojciech Maly
    Interconnect characteristics of 2.5-D system integration scheme. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:171-175 [Conf]
  27. Wei-Jin Dai
    Hierarchical physical design methodology for multi-million gate chips. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:179-181 [Conf]
  28. Padmini Gopalakrishnan, Altan Odabasioglu, Lawrence T. Pileggi, Salil Raje
    Overcoming wireload model uncertainty during physical design. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:182-189 [Conf]
  29. Zhaoyun Xing, Russell Kao
    A minimum cost path search algorithm through tile obstacles. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:192-197 [Conf]
  30. Kolja Sulimma, Wolfgang Kunz
    An exact algorithm for solving difficult detailed routing problems. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:198-203 [Conf]
  31. Ankireddy Nalamalpu, Wayne Burleson
    Boosters for driving long on-chip interconnects: design issues, interconnect synthesis and comparison with repeaters. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:204-211 [Conf]
  32. Rajeev Jayaraman
    Physical design for FPGAs. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:214-221 [Conf]
  33. Gi-Joon Nam, Fadi A. Aloul, Karem A. Sakallah, Rob A. Rutenbar
    A comparative study of two Boolean formulations of FPGA detailed routing constraints. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:222-227 [Conf]
  34. Kaustav Banerjee, Massoud Pedram, Amir H. Ajami
    Analysis and optimization of thermal issues in high-performance VLSI. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:230-237 [Conf]
  35. Ting-Yuan Wang, Charlie Chung-Ping Chen
    Thermal-ADI: a linear-time chip-level dynamic thermal simulation algorithm based on alternating-direction-implicit (ADI) method. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:238-243 [Conf]
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