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Conferences in DBLP

International Symposium on Physical Design (ISPD) (ispd)
1999 (conf/ispd/1999)

  1. Desmond Kirkpatrick
    The deep sub-micron signal integrity challenge. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:4-7 [Conf]
  2. Masato Iwabuchi, Noboru Sakamoto, Yasushi Sekine, Takashi Omachi
    A methodology to analyze power, voltage drop and their effects on clock skew/delay in early stages of design. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:9-15 [Conf]
  3. Sachio Hayashi, Masaaki Yamada
    EMI-noise analysis under ASIC design environment. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:16-21 [Conf]
  4. Paul B. Morton, Wayne Wei-Ming Dai
    An efficient sequential quadratic programming formulation of optimal wire spacing for cross-talk noise avoidance routing. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:22-28 [Conf]
  5. Chieh Changfan, Yu-Chin Hsu, Fur-Shing Tsai
    Post-routing timing optimization with routing characterization. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:30-35 [Conf]
  6. X. Zeng, D. Zhou, Wei Li
    Buffer insertion for clock delay and skew minimization. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:36-41 [Conf]
  7. Yanhong Yuan, Prithviraj Banerjee
    Incremental capacitance extraction and its application to iterative timing-driven detailed routing. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:42-47 [Conf]
  8. Kevin T. Tang, Eby G. Friedman
    Interconnect coupling noise in CMOS VLSI circuits. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:48-53 [Conf]
  9. Jeff Parkhurst, Naveed A. Sherwani, Sury Maturi, Dana Ahrams, Eli Chiprout
    SRC physical design top ten problem. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:55-58 [Conf]
  10. Dirk Stroobandt, Peter Verplaetse, Jan Van Campenhout
    Towards synthetic benchmark circuits for evaluating timing-driven CAD tools. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:60-66 [Conf]
  11. Joachim Pistorius, Edmée Legai, Michel Minoux
    Generation of very large circuits to benchmark the partitioning of FPGA. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:67-73 [Conf]
  12. Michael A. Riepe, Karem A. Sakallah
    Transistor level micro-placement and routing for two-dimensional digital VLSI cell synthesis. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:74-81 [Conf]
  13. Patrick H. Madden
    Partitioning by iterative deletion. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:83-89 [Conf]
  14. Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov
    Optimal partitioners and end-case placers for standard-cell layout. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:90-96 [Conf]
  15. Fung Yu Young, D. F. Wong
    Slicing floorplans with range constraint. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:97-102 [Conf]
  16. Kunihiro Fujiyoshi, Hiroshi Murata
    Arbitrary convex and concave rectilinear block packing using sequence-pair. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:103-110 [Conf]
  17. Andrew B. Kahng, Y. C. Pati
    Subwavelength optical lithography: challenges and impact on physical design. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:112-119 [Conf]
  18. Piotr Berman, Andrew B. Kahng, Devendra Vidhani, Huijuan Wang, Alexander Zelikovsky
    Optimal phase conflict removal for layout of dark field alternating phase shifting masks. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:121-126 [Conf]
  19. Wei Chen, Cheng-Ta Hsieh, Massoud Pedram
    Gate sizing with controlled displacement. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:127-132 [Conf]
  20. Jiang Hu, Sachin S. Sapatnekar
    Simultaneous buffer insertion and non-Hanan optimization for VLSI interconnect under a higher order AWE model. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:133-138 [Conf]
  21. Joseph L. Ganley
    Efficient solution of systems of orientation constraints. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:140-144 [Conf]
  22. Maogang Wang, Majid Sarrafzadeh
    On the behavior of congestion minimization during placement. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:145-150 [Conf]
  23. Charles J. Alpert, Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov
    Partitioning with terminals: a "new" problem and new benchmarks. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:151-157 [Conf]
  24. Durgam Vahia, Maciej J. Ciesielski
    Transistor level placement for full custom datapath cell design. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:158-163 [Conf]
  25. Amit Singh, Malgorzata Marek-Sadowska
    Circuit clustering using graph coloring. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:164-169 [Conf]
  26. Danqing Chen, Erhong Li, Elyse Rosenbaum, Sung-Mo Kang
    Interconnect thermal modeling for determining design limits on current density. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:172-178 [Conf]
  27. Ching-Han Tsai, Sung-Mo Kang
    Standard cell placement for even on-chip thermal distribution. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:179-184 [Conf]
  28. Kusnadi, Jo Dale Carothers
    A method of measuring nets routability for MCM's general area routing problems. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:186-192 [Conf]
  29. Dennis Sylvester, Kurt Keutzer
    Getting to the bottom of deep submicron II: a global wiring paradigm. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:193-200 [Conf]
  30. Phiroze N. Parakh, Richard B. Brown
    Crosstalk constrained global route embedding. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:201-206 [Conf]
  31. Sung-Woo Hur, Ashok Jagannathan, John Lillis
    Timing driven maze routing. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:208-213 [Conf]
  32. Jason Cong, Jie Fang, Kei-Yong Khoo
    VIA design rule consideration in multi-layer maze routing algorithms. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:214-220 [Conf]
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