Conferences in DBLP
Organizing Committee. [Citation Graph (0, 0)][DBLP ] Conf ] Welcome Notes. [Citation Graph (0, 0)][DBLP ] Conf ] Technical Subcommittees. [Citation Graph (0, 0)][DBLP ] Conf ] Conference at a Glance. [Citation Graph (0, 0)][DBLP ] Conf ] Steering/Advisory Committee. [Citation Graph (0, 0)][DBLP ] Conf ] Rajiv V. Joshi , Kaustav Banerjee , André DeHon Tutorial 1: Emerging Technologies for VLSI Design. [Citation Graph (0, 0)][DBLP ] Conf ] Keith A. Bowman , Michael Orshansky , Sachin S. Sapatnekar Tutorial II: Variability and Its Impact on Design. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Santarini , Pallab K. Chatterjee Session EP1: Power Management and Optimization Challenges for Sub 90nm CMOS Designs- What is the Real Cost of Long Battery Life?. [Citation Graph (0, 0)][DBLP ] Conf ] Risto Suoranta Modular service-oriented platform architecture - a key enabler to SoC design quality. [Citation Graph (0, 0)][DBLP ] Conf ] T. Furuyama Deep sub-100 nm Design Challenges. [Citation Graph (0, 0)][DBLP ] Conf ] Di Ma Successful IP Business Models. [Citation Graph (0, 0)][DBLP ] Conf ] Praveen Ghanta , Sarma B. K. Vrudhula Variational Interconnect Delay Metrics for Statistical Timing Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Evelyn Grossar , Michele Stucchi , Karen Maex , Wim Dehaene Statistically Aware SRAM Memory Array Design. [Citation Graph (0, 0)][DBLP ] Conf ] Zhiyu Liu , Volkan Kursun Robust Dynamic Node Low Voltage Swing Domino Logic with Multiple Threshold Voltages. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew B. Kahng , Bao Liu , Xu Xu Constructing Current-Based Gate Models Based on Existing Timing Library. [Citation Graph (0, 0)][DBLP ] Conf ] Zhuo Feng , Peng Li , Jiang Hu Efficient Model Update for General Link-Insertion Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Miroslav N. Velev Using Abstraction for Efficient Formal Verification of Pipelined Processors with Value Prediction. [Citation Graph (0, 0)][DBLP ] Conf ] Giuseppe Di Guglielmo , Franco Fummi , Cristina Marconcini , Graziano Pravadelli EFSM Manipulation to Increase High-Level ATPG Effectiveness. [Citation Graph (0, 0)][DBLP ] Conf ] Indradeep Ghosh , Mukul R. Prasad A Technique for Estimating the Difficulty of a Formal Verification Problem. [Citation Graph (0, 0)][DBLP ] Conf ] Chandan Karfa , Chittaranjan A. Mandal , Dipankar Sarkar , S. R. Pentakota , Chris Reade A Formal Verification Method of Scheduling in High-level Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Anand Rajaram , David Z. Pan Fast Incremental Link Insertion in Clock Networks for Skew Variability Reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Chao-Yang Yeh , Gustavo R. Wilke , Hongyu Chen , Subodh M. Reddy , Hoa-van Nguyen , Takashi Miyoshi , William W. Walker , Rajeev Murgai Clock Distribution Architectures: A Comparative Study. [Citation Graph (0, 0)][DBLP ] Conf ] Narender Hanchate , Nagarajan Ranganathan Post-Layout Gate Sizing for Interconnect Delay and Crosstalk Noise Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Wei-Lun Hung , Greg M. Link , Yuan Xie , Narayanan Vijaykrishnan , Mary Jane Irwin Interconnect and Thermal-aware Floorplanning for 3D Microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Keating Simplicity and Executability: Cornerstones of Quality. [Citation Graph (0, 0)][DBLP ] Conf ] Yogesh Singh Chauhan , C. Anghel , Francois Krummenacher , Renaud Gillon , A. Baguenier A Compact DC and AC Model for Circuit Simulation of High Voltage VDMOS Transistor. [Citation Graph (0, 0)][DBLP ] Conf ] Jin He , Xing Zhang , Ganggang Zhang , Mansun Chan , Yangyuan Wang A Complete Carrier-Based Non-Charge-Sheet Analytic Theory for Nano-Scale Undoped Surrounding-Gate MOSFETs. [Citation Graph (0, 0)][DBLP ] Conf ] Brian Swahn , Soha Hassoun METS: A Metric for Electro-Thermal Sensitivity, and Its Application To FinFETs. [Citation Graph (0, 0)][DBLP ] Conf ] Jin He , Xing Zhang , Ganggang Zhang , Yangyuan Wang A Carrier-Based Analytic Model for Undoped (Lightly Doped) Ultra-Thin-Body Silicon-on-Insulator (UTB-SOI) MOSFETs. [Citation Graph (0, 0)][DBLP ] Conf ] Chong Zhao , Sujit Dey Improving Transient Error Tolerance of Digital VLSI Circuits Using RObustness COmpiler (ROCO). [Citation Graph (0, 0)][DBLP ] Conf ] Soheil Ghiasi , Po-Kuan Huang Probabilistic Delay Budgeting for Soft Realtime Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Jindrich Zejda , Li Ding TBNM - Transistor-Level Boundary Model for Fast Gate-Level Noise Analysis of Macro Blocks. [Citation Graph (0, 0)][DBLP ] Conf ] Nahmsuk Oh , Li Ding , Alireza Kasnavi Fast Sequential Cell Noise Immunity Characterization Using Meta-stable Point of Feedback Loop. [Citation Graph (0, 0)][DBLP ] Conf ] Emre Salman , Eby G. Friedman , Ali Dasdan , Feroze Taraporevala , Kayhan Küçükçakar Pessimism Reduction In Static Timing Analysis Using Interdependent Setup and Hold Times. [Citation Graph (0, 0)][DBLP ] Conf ] Deniz Dal , Adrian Nunez , Nazanin Mansouri Power Islands: A High-Level Technique for Counteracting Leakage in Deep Sub-Micron. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew Havlir , David Z. Pan Simultaneous Statistical Delay and Slew Optimization for Interconnect Pipelines. [Citation Graph (0, 0)][DBLP ] Conf ] Fadi J. Kurdahi , Ahmed M. Eltawil , Young-Hwan Park , Rouwaida N. Kanj , Sani R. Nassif System-Level SRAM Yield Enhancement. [Citation Graph (0, 0)][DBLP ] Conf ] Young-Gu Kim , Sang-Hoon Lee , Dae-Han Kim , Jae-Woo Im , Sung-Eun Yu , Dae-Wook Kim , Young-Kwan Park , Jeong-Taek Kong Sensing Margin Analysis of MLC Flash Memories Using a Novel Unified Statistical Model. [Citation Graph (0, 0)][DBLP ] Conf ] R. Venkatraman , R. Castagnetti , S. Ramesh The Statistics of Device Variations and its Impact on SRAM Bitcell Performance, Leakage and Stability. [Citation Graph (0, 0)][DBLP ] Conf ] Makoto Sugihara , Tohru Ishihara , Masanori Muroyama , Koji Hashimoto A Simulation-Based Soft Error Estimation Methodology for Computer Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Praveen Elakkumanan , Jente B. Kuang , Kevin J. Nowka , Ramalingam Sridhar , Rouwaida Kanj , Sani R. Nassif SRAM Local Bit Line Access Failure Analyses. [Citation Graph (0, 0)][DBLP ] Conf ] Sanjay V. Kumar , Chris H. Kim , Sachin S. Sapatnekar Impact of NBTI on SRAM Read Stability and Design for Reliability. [Citation Graph (0, 0)][DBLP ] Conf ] Krishna Prasad Raghuraman , Haibo Wang , Spyros Tragoudas Minimizing FPGA Reconfiguration Data at Logic Level. [Citation Graph (0, 0)][DBLP ] Conf ] Kaiping Zeng , Sorin A. Huss Structure Synthesis of Analog and Mixed-Signal Circuits using Partition Techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Yi-Le Huang , Chun-Yao Wang , Richard Yeh , Shih-Chieh Chang , Yung-Chih Chen Language-Based High Level Transaction Extraction on On-chip Buses. [Citation Graph (0, 0)][DBLP ] Conf ] Xinjie Wei , Yici Cai , Xianlong Hong Clock Skew Scheduling Under Process Variations. [Citation Graph (0, 0)][DBLP ] Conf ] Qikai Chen , Mesut Meterelliyoz , Kaushik Roy A CMOS Thermal Sensor and Its Applications in Temperature Adaptive Design. [Citation Graph (0, 0)][DBLP ] Conf ] Rasit Onur Topaloglu Monte Carlo-Alternative Probabilistic Simulations for Analog Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Peng Li Critical Path Analysis Considering Temperature, Power Supply Variations and Temperature Induced Leakage. [Citation Graph (0, 0)][DBLP ] Conf ] C. Tabery , M. Craig , G. Burbach , B. Wagner , S. McGowan , P. Etter , S. Roling , C. Haidinyak , E. Ehrichs Process Window and Device Variations Evaluation using Array-Based Characterization Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Xiongfei Meng , Resve A. Saleh , Karim Arabi Novel Decoupling Capacitor Designs for sub- 90nm CMOS Technology. [Citation Graph (0, 0)][DBLP ] Conf ] Jeffrey Fan , I-Fan Liao , Sheldon X.-D. Tan , Yici Cai , Xianlong Hong Localized On-Chip Power Delivery Network Optimization via Sequence of Linear Programming. [Citation Graph (0, 0)][DBLP ] Conf ] Seongkyun Shin , Yungseon Eo Non-Physical Pseudo-Wave-Based Modal Decoupling Technique of Multi- Coupled Co-Planar Transmission Lines with Homogeneous Dielectric Media. [Citation Graph (0, 0)][DBLP ] Conf ] Krishna Srinivasan , P. Muthana , Rohan Mandrekar , Ege Engin , J. Choi , Madhavan Swaminathan Enhancement of Signal Integrity and Power Integrity with Embedded Capacitors in High-Speed Packages. [Citation Graph (0, 0)][DBLP ] Conf ] Cheng Zhuo , Jiang Hu , Kangsheng Chen An Improved AMG-based Method for Fast Power Grid Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Miroslav N. Velev Formal Verification of Pipelined Microprocessors with Delayed Branches. [Citation Graph (0, 0)][DBLP ] Conf ] Arkan Abdulrahman , Spyros Tragoudas Power-Aware Test Pattern Generation for Improved Concurrency at the Core Level. [Citation Graph (0, 0)][DBLP ] Conf ] Debjit Sinha , Hai Zhou , Narendra V. Shenoy Advances in Computation of the Maximum of a Set of Random Variables. [Citation Graph (0, 0)][DBLP ] Conf ] Ali Bastani , Charles A. Zukowski A Low-Leakage High-Speed Monotonic Static CMOS 64b Adder in a Dual Gate Oxide 65-nm CMOS Technology. [Citation Graph (0, 0)][DBLP ] Conf ] Zhiyu Liu , Volkan Kursun Leakage Biased Sleep Switch Domino Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Randy Bach , Bob Davis , Rich Laubhan Improvements to CBCM (Charge-Based Capacitance Measurement) for Deep Submicron CMOS Technology. [Citation Graph (0, 0)][DBLP ] Conf ] Sajid Baloch , Tughrul Arslan , Adrian Stoica Design of a Single Event Upset (SEU) Mitigation Technique for Programmable Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Jean-Marc Philippe , Sébastien Pillement , Olivier Sentieys Area Efficient Temporal Coding Schemes for Reducing Crosstalk Effects. [Citation Graph (0, 0)][DBLP ] Conf ] Jia Wang , Hai Zhou , Ping-Chih Wu Processing Rate Optimization by Sequential System Floorplanning. [Citation Graph (0, 0)][DBLP ] Conf ] Zile Wei , Donald Chai , A. Richard Newton , Andreas Kuehlmann Fast Boolean Matching with Don't Cares. [Citation Graph (0, 0)][DBLP ] Conf ] Krishnan Srinivasan , Karam S. Chatha A Methodology for Layout Aware Design and Optimization of Custom Network-on-Chip Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Praveen Bhojwani , Rabi N. Mahapatra Core Network Interface Architecture and Latency Constrained On-Chip Communication. [Citation Graph (0, 0)][DBLP ] Conf ] Vyas Krishnan , Srinivas Katkoori Design Space Exploration of RTL Datapaths Using Rent Parameter based Stochastic Wirelength Estimation. [Citation Graph (0, 0)][DBLP ] Conf ] Takeshi Matsumoto , Hiroshi Saito , Masahiro Fujita Equivalence Checking of C Programs by Locally Performing Symbolic Simulation on Dependence Graphs. [Citation Graph (0, 0)][DBLP ] Conf ] C. Sanz , Manuel Prieto , Antonis Papanikolaou , Miguel Miranda , Francky Catthoor System-level process variability compensation on memory organizations of dynamic applications: a case study. [Citation Graph (0, 0)][DBLP ] Conf ] Biye Wang , Lili He , Morris Jones A low input, low-power dissipation CMOS ADC. [Citation Graph (0, 0)][DBLP ] Conf ] J. Balachandran , Steven Brebels , G. Carchon , Walter De Raedt , Eric Beyne , M. Kuijk , Bart Nauwelaers Constant Impedance Scaling Paradigm for Scaling LC transmission lines. [Citation Graph (0, 0)][DBLP ] Conf ] Yuichi Tanji , Takayuki Watanabe , Hidemasa Kubota , Hideki Asai Quasi-One-Step Gauss-Jacobi Method for Large-Scale Interconnect Analysis via RLCG-MNA Formulation. [Citation Graph (0, 0)][DBLP ] Conf ] Min Chen , Yu Cao Analysis of Pulse Signaling for Low-Power On-Chip Global Bus Design. [Citation Graph (0, 0)][DBLP ] Conf ] Rohit Singhal , Gwan S. Choi , Rabi N. Mahapatra Information Theoretic Capacity of Long On-chip Interconnects in the Presence of Crosstalk. [Citation Graph (0, 0)][DBLP ] Conf ] Pu Liu , Sheldon X.-D. Tan , Bruce McGaughy , Lifeng Wu Compact Reduced Order Modeling for Multiple-Port Interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Taeyong Je , Yungseon Eo Efficient Signal Integrity Verification Method of Multi-Coupled RLC Interconnect Lines with Asynchronous Circuit Switching. [Citation Graph (0, 0)][DBLP ] Conf ] Maged Ghoneima , Yehea I. Ismail , Muhammad M. Khellah , Vivek De Reducing the Data Switching Activity on Serial Link Buses. [Citation Graph (0, 0)][DBLP ] Conf ] Emmanouil Kalligeros , Xrysovalantis Kavousianos , Dimitris Nikolos Efficient Multiphase Test Set Embedding for Scan-based Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Rajsekhar Adapa , Spyros Tragoudas , Maria K. Michael Evaluation of Collapsing Methods for Fault Diagnosis. [Citation Graph (0, 0)][DBLP ] Conf ] Yu Huang On N-Detect Pattern Set Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Li-Chung Hsu , Hung-Ming Chen On Optimizing Scan Testing Power and Routing Cost in Scan Chain Design. [Citation Graph (0, 0)][DBLP ] Conf ] Edward Flanigan , Themistoklis Haniotakis , Spyros Tragoudas An Improved Method for Identifying Linear Dependencies in Path Delay Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Vishal J. Mehta , Malgorzata Marek-Sadowska , Zhiyuan Wang , Kun-Han Tsai , Janusz Rajski Delay Fault Diagnosis for Non-Robust Test. [Citation Graph (0, 0)][DBLP ] Conf ] Jeanne Bickford , Jason Hibbeler , Markus Bühler , Jürgen Koehl , Dirk Muller , Sven Peyer , Christian Schulte Yield Improvement by Local Wiring Redundancy. [Citation Graph (0, 0)][DBLP ] Conf ] Takumi Uezono , Kenichi Okada , Kazuya Masu Via Distribution Model for Yield Estimation. [Citation Graph (0, 0)][DBLP ] Conf ] Lawrence S. Melvin III , Daniel N. Zhang , Kirk J. Strozewski , Skye Wolfer The Use of the Manufacturing Sensitivity Model Forms to Comprehend Layout Manufacturing Robustness For Use During Device Design. [Citation Graph (0, 0)][DBLP ] Conf ] Robert C. Aitken DFM Metrics for Standard Cells. [Citation Graph (0, 0)][DBLP ] Conf ] Arnaud Epinat , N. Vijayaraghavan , Matthieu Sautier , Olivier Callen , Sebastien Fabre , Ryan Ross , Paul Simon , Robin Wilson Yield Enhancement Methodology for CMOS Standard Cells. [Citation Graph (0, 0)][DBLP ] Conf ] Hsin-Chyh Hsu , Ming-Dou Ker Dummy-Gate Structure to Improve ESD Robustness in a Fully-Salicided 130-nm CMOS Technology without Using Extra Salicide-Blocking Mask. [Citation Graph (0, 0)][DBLP ] Conf ] Ron Wilson , David Overhauser Who is really responsible for quality throughout the design process?. [Citation Graph (0, 0)][DBLP ] Conf ] Raul Camposano Adding Manufacturability to the Quality of Results. [Citation Graph (0, 0)][DBLP ] Conf ] Changhyun Kim Future Memory Technology Trends and Challenges. [Citation Graph (0, 0)][DBLP ] Conf ] H.-S. Philip Wong Device and Technology Challenges for Nanoscale CMOS. [Citation Graph (0, 0)][DBLP ] Conf ] Adam Matthews A Totally Self-Checking S-box Architecture for the Advanced Encryption Standard. [Citation Graph (0, 0)][DBLP ] Conf ] Qingqi Dou , Jacob A. Abraham Jitter Decomposition by Time Lag Correlation. [Citation Graph (0, 0)][DBLP ] Conf ] Amit Laknaur , Haibo Wang Design ofWindow Comparators for Integrator-Based Capacitor Array Testing Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Daniela De Venuto , Leonardo Reyneri Analysis and experimental results of an FPGA-based strategy for fast production test of high resolution ADCs. [Citation Graph (0, 0)][DBLP ] Conf ] José Luis Catalano , Gabriela Peretti , Eduardo Romero , Carlos A. Marqués Exploring the Ability of Oscillation Based Test for Testing Continuous -Time Ladder Filters. [Citation Graph (0, 0)][DBLP ] Conf ] Ozcan Ozturk , Mahmut T. Kandemir Data Replication in Banked DRAMs for Reducing Energy Consumption. [Citation Graph (0, 0)][DBLP ] Conf ] Minh Quang Do , Mindaugas Drazdziulis , Per Larsson-Edefors , Lars Bengtsson Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration. [Citation Graph (0, 0)][DBLP ] Conf ] Saraju P. Mohanty , Ramakrishna Velagapudi , Elias Kougianos Dual-K Versus Dual-T Technique for Gate Leakage Reduction : A Comparative Perspective. [Citation Graph (0, 0)][DBLP ] Conf ] Sri Hari Krishna Narayanan , Mahmut T. Kandemir , Ozcan Ozturk Compiler-Directed Power Density Reduction in NoC-Based Multi-Core Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Ozcan Ozturk , Mahmut T. Kandemir , Ibrahim Kolcu Shared Scratch-Pad Memory Space Management. [Citation Graph (0, 0)][DBLP ] Conf ] Wei Zhao , Yu Cao New Generation of Predictive Technology Model for Sub-45nm Design Exploration. [Citation Graph (0, 0)][DBLP ] Conf ] M. Thomas , J. Pathak , J. Payne , F. Leisenberger , E. Wachmann , G. Schatzberger , A. Wiesner , M. Schrems A Non-Volatile Embedded Memory for High Temperature Automotive and High-Retention Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Tai-Xiang Lai , Ming-Dou Ker Method to Evaluate Cable Discharge Event (CDE) Reliability of Integrated Circuits in CMOS Technology. [Citation Graph (0, 0)][DBLP ] Conf ] Chung-Kuan Tsai , Malgorzata Marek-Sadowska Analysis of Process Variation's Effect on SRAM's Read Stability. [Citation Graph (0, 0)][DBLP ] Conf ] Vivek Joshi , Rajeev R. Rao , David Blaauw , Dennis Sylvester Logic SER Reduction through Flipflop Redesign. [Citation Graph (0, 0)][DBLP ] Conf ] Praveen Elakkumanan , Kishan Prasad , Ramalingam Sridhar Time Redundancy Based Scan Flip-Flop Reuse To Reduce SER Of Combinational Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Greg M. Link , Narayanan Vijaykrishnan Thermal Trends in Emerging Technologies. [Citation Graph (0, 0)][DBLP ] Conf ] Kanak Agarwal , Kevin J. Nowka , Harmander Deogun , Dennis Sylvester Power Gating with Multiple Sleep Modes. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew B. Kahng , Bao Liu , Sheldon X.-D. Tan SMM: Scalable Analysis of Power Delivery Networks by Stochastic Moment Matching. [Citation Graph (0, 0)][DBLP ] Conf ] Anand Ramalingam , David Z. Pan , Frank Liu , Sani R. Nassif Accurate Thermal Analysis Considering Nonlinear Thermal Conductivity. [Citation Graph (0, 0)][DBLP ] Conf ] Mark M. Budnik , Kaushik Roy Minimizing Ohmic Loss in Future Processor IR Events. [Citation Graph (0, 0)][DBLP ] Conf ] Anand P. Kulkarni , Thomas J. Grebinski mTest: An Industry-Wide Database of VLSI Layouts for Quality Control. [Citation Graph (0, 0)][DBLP ] Conf ] Sanghamitra Roy , Charlie Chung-Ping Chen ConvexSmooth: A simultaneous convex fitting and smoothing algorithm for convex optimization problems. [Citation Graph (0, 0)][DBLP ] Conf ] Guangyu Sun , Zhiqiang Gao , Yi Xu A Watermarking System for IP Protection by Buffer Insertion Technique. [Citation Graph (0, 0)][DBLP ] Conf ] Anand P. Kulkarni , Thomas J. Grebinski Partial Selective Encryption: An Improved System for Protecting VLSI Design Data in the OASIS format. [Citation Graph (0, 0)][DBLP ] Conf ] Dimitri Kagaris , Themistoklis Haniotakis Transistor-Level Optimization of Supergates. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew B. Kahng , Kambiz Samadi , Puneet Sharma Study of Floating Fill Impact on Interconnect Capacitance. [Citation Graph (0, 0)][DBLP ] Conf ] Karen Chow The Challenges and Impact of Parasitic Extraction at 65 nm. [Citation Graph (0, 0)][DBLP ] Conf ] Laureline David , Stephane Martin , Corinne Cregut , Eric Balossier , Frederic Nyer , Fabrice Huret Pre-Layout Inductive Corners for Advanced Digital Design Interconnect: Modeling and Silicon Validation. [Citation Graph (0, 0)][DBLP ] Conf ] Changhao Yan , Wenjian Yu , Zeyi Wang A Mixed Boundary Element Method for Extracting Frequency- Inductances of 3D Interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Sarvesh Bhardwaj , Yu Cao , Sarma B. K. Vrudhula LOTUS: Leakage Optimization under Timing Uncertainty for Standard-cell designs. [Citation Graph (0, 0)][DBLP ] Conf ] Yu Wang , Hai Lin , Huazhong Yang , Rong Luo , Hui Wang Simultaneous Fine-grain Sleep Transistor Placement and Sizing for Leakage Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Behnam Amelifard , Massoud Pedram , Farzan Fallah Low-leakage SRAM Design with Dual V_t Transistors. [Citation Graph (0, 0)][DBLP ] Conf ] Akhilesh Kumar , Mohab Anis Dual-Vt Design of FPGAs for Subthreshold Leakage Tolerance. [Citation Graph (0, 0)][DBLP ] Conf ] Chanseok Hwang , Chang Woo Kang , Massoud Pedram Gate Sizing and Replication to Minimize the Effects of Virtual Ground Parasitic Resistances in MTCMOS Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew B. Kahng , Swamy Muddu , Puneet Sharma Impact of Gate-Length Biasing on Threshold-Voltage Selection. [Citation Graph (0, 0)][DBLP ] Conf ] Bin Zhang , Wei-Shen Wang , Michael Orshansky FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Lee Barford Diagnosis and Design for Diagnosability for Internet Routers. [Citation Graph (0, 0)][DBLP ] Conf ] Bhaskar J. Karmakar , V. Kalyana Chakravarty , R. Venkatraman , Jagdish C. Rao Enabling Quality and Schedule Predictability in SoC Design using HandoffQC. [Citation Graph (0, 0)][DBLP ] Conf ] I.-C. Lin , S. Srinivasan , Narayanan Vijaykrishnan , N. Dhanwada Transaction Level Error Susceptibility Model for Bus Based SoC Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Riad Ben Mouhoub , Omar Hammami System-Level Design Methodology with Direct Execution For Multiprocessors on SoPC. [Citation Graph (0, 0)][DBLP ] Conf ] Artur Balasinski Question: DRC or DfM ? Answer: FMEA and ROI. [Citation Graph (0, 0)][DBLP ] Conf ] Usha Narasimha , Binu Abraham , N. S. Nagaraj Statistical Analysis of Capacitance Coupling Effects on Delay and Noise. [Citation Graph (0, 0)][DBLP ] Conf ] S. Tirumala , Y. Mahotin , X. Lin , V. Moroz , L. Smith , S. Krishnamurthy , L. Bomholt , D. Pramanik Bringing Manufacturing into Design via Process-Dependent SPICE Models. [Citation Graph (0, 0)][DBLP ] Conf ] Victor Moroz , Lee Smith , Xi-Wei Lin , Dipu Pramanik , Greg Rollins Stress-Aware Design Methodology. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Wright , Minghui Fan A DFM Methodology to Evaluate the Impact of Lithography Conditions on the Speed of Critical Paths in a VLSI Circuit. [Citation Graph (0, 0)][DBLP ] Conf ] 