Conferences in DBLP
Robert N. Blair , Jacques Benkoski How Do You Select A High Quality EDA Tool Flow?. [Citation Graph (0, 0)][DBLP ] Conf ] Aart J. de Geus Slap it Together and Ship it! [Citation Graph (0, 0)][DBLP ] Conf ] John East The Practical Side of Quality. [Citation Graph (0, 0)][DBLP ] Conf ] Prakash Agrawal Design for Quality and Manufacturing. [Citation Graph (0, 0)][DBLP ] Conf ] John Kibarian Ramping New IC Products in the Deep Submicron Age. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Reinhardt , Michael Santarini What is Design Quality? How can Quality in Electronic Design be Quantified? [Citation Graph (0, 0)][DBLP ] Conf ] Michael S. Shur , Tor A. Fjeldly , Trond Ytterdal Transistor Modeling for the VDSM Era. [Citation Graph (0, 0)][DBLP ] Conf ] Gilbert Yoh , Farid N. Najm A Statistical Model for Electromigration Failures. [Citation Graph (0, 0)][DBLP ] Conf ] Murat R. Becer , Ibrahim N. Hajj An Analytical Model for Delay and Crosstalk Estimation with Application to Decoupling. [Citation Graph (0, 0)][DBLP ] Conf ] Roberto Zafalon , Massimo Rossello , Enrico Macii , Massimo Poncino Power Macromodeling for a High Quality RT-Level Power Estimation. [Citation Graph (0, 0)][DBLP ] Conf ] Jiann S. Yuan Overview of SiGe Technology Modeling and Application. [Citation Graph (0, 0)][DBLP ] Conf ] Lifeng Wu , Jingkun Fang , Heting Yan , Ping Chen , Alvin I-Hsien Chen , Yoshifumi Okamoto , Chune-Sin Yeh , Zhihong Liu , Nobufusa Iwanishi , Norio Koike , Hirokazu Yonezawa , Yoshiyuki Kawakami GLACIER: A Hot Carrier Gate Level Circuit Characterization and Simulation System for VLSI Design. [Citation Graph (0, 0)][DBLP ] Conf ] Ji-Soong Park , Chul-Hong Park , Sang-Uhk Rhie , Yoo-Hyon Kim , Moon-Hyun Yoo , Jeong-Taek Kong , Hyung-Woo Kim , Sun-Il Yoo An Efficient Rule-Based OPC Approach Using a DRC Tool for 0.18mum ASIC. [Citation Graph (0, 0)][DBLP ] Conf ] Kwan-Do Kim , Young-Kwan Park , Jun-Ha Lee , Jeong-Taek Kong , Hee-Sung Kang , Young-Wug Kim , Seok-Jin Kim Three Dimensional Analysis of Thermal Degradation Effects in FDSOI MOSFET's. [Citation Graph (0, 0)][DBLP ] Conf ] Lech Józwiak Quality-Driven System-on-a-Chip Design. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Keating Measuring Design Quality by Measuring Design Complexity. [Citation Graph (0, 0)][DBLP ] Conf ] Betty Prince Quality Memory Blocks -- Balancing the Trade-Offs. [Citation Graph (0, 0)][DBLP ] Conf ] Israel Koren Should Yield be a Design Objective? [Citation Graph (0, 0)][DBLP ] Conf ] Anna Fontanelli , Luigi Arnone , Roberto Branca , Giorgio Mastrorocco Early Addressing IC and Package Relationship Allows an Overall Better Quality of Complex SOC. [Citation Graph (0, 0)][DBLP ] Conf ] Kenji Shimazaki , Hiroyuki Tsujikawa , Seijiro Kojima , Shouzou Hirano LEMINGS: LSI's EMI-Noise Analysis with Gate Level Simulator. [Citation Graph (0, 0)][DBLP ] Conf ] Yi-Min Jiang , Angela Krstic , Kwang-Ting Cheng Dynamic Timing Analysis Considering Power Supply Noise Effects. [Citation Graph (0, 0)][DBLP ] Conf ] Zhiping Yu , Dan Yergeau , Robert W. Dutton , Sam Nakagawa , Norman Chang , Shen Lin , Weize Xie Full Chip Thermal Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Wonjae L. Kang , Brad Potts , Ray Hokinson , John Riley , David Doman , Frank Cano , N. S. Nagaraj , Noel Durrant Enabling DIR(Designing-In-Reliability) through CAD Capabilities. [Citation Graph (0, 0)][DBLP ] Conf ] Mariagrazia Graziano , Marco Delaurenti , Guido Masera , Gianluca Piccinini , Maurizio Zamboni Noise Safety Design Methodologies. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas W. Williams , Rohit Kapur Design for Testability in Nanometer Technologies; Searching for Quality. [Citation Graph (0, 0)][DBLP ] Conf ] Patrick Girard Low Power Testing of VLSI Circuits: Problems and Solutions. [Citation Graph (0, 0)][DBLP ] Conf ] Zhanping Chen , Liqiong Wei , Kaushik Roy On Effective IDDQ Testing of Low Voltage CMOS Circuits Using Leakage Control Techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Raimund Ubar , Jaan Raik Efficient Hierarchical Approach to Test Generation for Digital Systems. [Citation Graph (0, 0)][DBLP ] Conf ] O. P. Dias , Jorge Semião , Marcelino B. Santos , Isabel C. Teixeira , João Paulo Teixeira Quality of Electronic Design: From Architectural Level to Test Coverage. [Citation Graph (0, 0)][DBLP ] Conf ] Richard Goering , Richard Wallace The Hidden Costs of Design Qualit. [Citation Graph (0, 0)][DBLP ] Conf ] Alberto L. Sangiovanni-Vincentelli Platform-Based Design: A Path to Efficient Design Re-Use. [Citation Graph (0, 0)][DBLP ] Conf ] Yervant Zorian Embedded-Quality for Test. [Citation Graph (0, 0)][DBLP ] Conf ] Kamran Eshraghian Deep Submicron USLI Design Paradigm: Who is Writing the Future? [Citation Graph (0, 0)][DBLP ] Conf ] Tomás Bautista , Antonio Núñez Synthesis Experiments and Performance Metrics for Evaluating the Quality of IP Blocks and Megacells. [Citation Graph (0, 0)][DBLP ] Conf ] Dave Protheroe , Francesco Pessolano An Objective Measure of Digital System Design Quality. [Citation Graph (0, 0)][DBLP ] Conf ] Tom Chen , Anneliese von Mayrhauser , Amjad Hajjar , Charles Anderson , Mehmet Sahinoglu Achieving the Quality of Verification for Behavioral Models with Minimum Effort. [Citation Graph (0, 0)][DBLP ] Conf ] Ashok K. Sinha Extending Moore's Law through Advances in Semiconductor Manufacturing Equipment. [Citation Graph (0, 0)][DBLP ] Conf ] Ana Hunter , C. K. Lau , John Martin Combining Advanced Process Technology and Design for Systems Level Integration. [Citation Graph (0, 0)][DBLP ] Conf ] Charvaka Duvvury ESD: Design For IC Chip Quality and Reliability. [Citation Graph (0, 0)][DBLP ] Conf ] Geng Bai , Sudhakar Bobba , Ibrahim N. Hajj Power Bus Maximum Voltage Drop in Digital VLSI Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Mely Chen Chi , Shih-Hsu Huang A Reliable Clock Tree Design Methodology for ASIC Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Peter H. Chen , Sunil Malkani , Chun-Mou Peng , James Lin Fixing Antenna Problem by Dynamic Diode Dropping and Jumper Insertion. [Citation Graph (0, 0)][DBLP ] Conf ] Donald J. Dent Project Management for System-on-Chip Using Multi-Chip Modules. [Citation Graph (0, 0)][DBLP ] Conf ] Mohamed Dessouky , Marie-Minerve Louërat A Layout Approach for Electrical and Physical Design Integration of High-Performance Analog Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Th. Haniotakis , Y. Tsiatouhas , Dimitris Nikolos , Costas Efstathiou On Testability of Multiple Precharged Domino Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Makoto Ikeda , Hideyuki Aoki , Kunihiro Asada DVDT: Design for Voltage Drop Test Using Onchip-Voltage Scan Path. [Citation Graph (0, 0)][DBLP ] Conf ] J. L. Knighten , N. W. Smith , L. O. Hoeft , J. T. DiBene II EMI Common-Mode Current Dependence on Delay Skew Imbalance in High Speed Differential Transmission Lines Operating at 1 Gigabit/second Data Rates. [Citation Graph (0, 0)][DBLP ] Conf ] Wieslaw Kuzmicz Internet-Based Virtual Manufacturing: A Verification Tool for IC Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Rong Lin A Reconfigurable Low-Power High-Performance Matrix Multiplier Design. [Citation Graph (0, 0)][DBLP ] Conf ] Mehdi M. Mechaik Electrical Characterization of Signal Routability and Performance. [Citation Graph (0, 0)][DBLP ] Conf ] Steffen Rochel , N. S. Nagaraj Full-Chip Signal Interconnect Analysis for Electromigration Reliability. [Citation Graph (0, 0)][DBLP ] Conf ] Erik A. McShane , Krishna Shenai Correct-by-Design CAD Enhancement for EMI Signal Integrity. [Citation Graph (0, 0)][DBLP ] Conf ] Alvernon Walker , Parag K. Lala A Transition Based BIST Approach for Passive Analog Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Jin Ding , David Moloney , Xiaojun Wang Aliasing-Free Space and Time Compactions with Limited Overhead. [Citation Graph (0, 0)][DBLP ] Conf ] Matthew Worsman , Mike W. T. Wong , Y. S. Lee A Pre-Simulation Measure of D.C. Design-for-Testability Fault Diagnosis Quality. [Citation Graph (0, 0)][DBLP ] Conf ] Gin Yee , Tyler Thorp , Ron Christopherson , Ban P. Wang , Carl Sechen An Automated Shielding Algorithm and Tool For Dynamic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Li-Fu Chang , Keh-Jeng Chang , Christophe J. Bianchi A Proposal for Accurately Modeling Frequency-Dependent On-Chip Interconnect Impedance. [Citation Graph (0, 0)][DBLP ] Conf ] Jean-Pierre Gukguen , Pierre Bricaud Applying the OpenMORE Assessment Program for IP Cores. [Citation Graph (0, 0)][DBLP ] Conf ] Nader Vasseghi , Rita Glover Focus on Quality of Design: Does it Help or Hinder Time to Market? [Citation Graph (0, 0)][DBLP ] Conf ] Einar J. Aas Design Quality and Design Efficiency; Definitions, Metrics and Relevant Design Experiences. [Citation Graph (0, 0)][DBLP ] Conf ] Amir H. Farrahi , David J. Hathaway , Maogang Wang , Majid Sarrafzadeh Quality of EDA CAD Tools: Definitions, Metrics and Directions. [Citation Graph (0, 0)][DBLP ] Conf ] Richard Goldman , Karen Bartleson Tool Interoperability is Key to Improved Design Quality. [Citation Graph (0, 0)][DBLP ] Conf ] Giora Ben-Yaacov , Larry Bjork , Edward P. Stone Advancing Customer-Perceived Quality in the EDA Industry. [Citation Graph (0, 0)][DBLP ] Conf ] Takayasu Sakurai Reducing Power Consumption of CMOS VLSI's through VDD and VTH Control. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaodong Zhang , Kaushik Roy Peak Power Reduction in Low Power BIST. [Citation Graph (0, 0)][DBLP ] Conf ] Dimitris Bakalis , Dimitris Nikolos , George Alexiou , Emmanouil Kalligeros , Haridimos T. Vergos Low Power BIST for Wallace Tree-Based Fast Multipliers. [Citation Graph (0, 0)][DBLP ] Conf ] Ricardo Ferreira , A.-M. Trullemans , José C. Costa , José Monteiro Probabilistic Bottom-Up RTL Power Estimation. [Citation Graph (0, 0)][DBLP ] Conf ] Carlo Guardiani , Andrzej J. Strojwas Design-Manufacturing Interface in the Deep Submicron: Is Technology Independent Design Dead? [Citation Graph (0, 0)][DBLP ] Conf ] Sani R. Nassif Design for Variability in DSM Technologies. [Citation Graph (0, 0)][DBLP ] Conf ] Alessandra Nardi , Andrea Neviani , Carlo Guardiani Realistic Worst-Case Modeling by Performance Level Principal Component Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Valery Axelrad , Nicolas B. Cobb , M. O'Brien , Thuy Do , Tom Donnelly , Yuri Granik , Emile Y. Sahouria , Victor Boksha , Artur Balasinski Efficient Full-Chip Yield Analysis Methodology for OPC-Corrected VLSI Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Gary W. Maier , Shawn Smith Electronic Process Limited Yield. [Citation Graph (0, 0)][DBLP ] Conf ] Mehdi M. Mechaik Effects of Package Stackups on Microprocessor Performance. [Citation Graph (0, 0)][DBLP ] Conf ] Kathirgamar Aingaran , Fabian Klass , Chin-Man Kim , Chaim Amir , Joydeep Mitra , Eileen You , Jamil Mohd , Sai-keung Dong Coupling Noise Analysis for VLIS and ULSI Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Tong Xiao , Malgorzata Marek-Sadowska Efficient Delay Calculation in Presence of Crosstalk. [Citation Graph (0, 0)][DBLP ] Conf ] Bruno Franzini , Cristiano Forzan , Davide Pandini , Primo Scandolara , Alessandro Dal Fabbro Crosstalk Aware Static Timing Analysis: A Two Step Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Peivand F. Tehrani , Shang Woo Chyou , Uma Ekambaram Deep Sub-Micron Static Timing Analysis in Presence of Crosstalk. [Citation Graph (0, 0)][DBLP ] Conf ] Shen Lin , Norman Chang , O. Sam Nakagawa Quick On-Chip Self- and Mutual-Inductance Screen. [Citation Graph (0, 0)][DBLP ] Conf ] 