Conferences in DBLP
Yervant Zorian System-on-Chip: Embedded Test Strategies. [Citation Graph (0, 0)][DBLP ] Conf ] Kaushik Roy , Ali Keshavarzi Design and Test of Low Voltage CMOS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Mo Tamjidi , Bejoy G. Oomman Redundancy Requirements for Embedded Memories. [Citation Graph (0, 0)][DBLP ] Conf ] Phil Dworsky , Warren Savage Fundamental Methods to Enable SoC Design and Reuse. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew B. Kahng , Ronald Collett , Ton. H. van de Kraats Design Metrics to Achieve Design Quality. [Citation Graph (0, 0)][DBLP ] Conf ] Charvaka Duvvury Issues in Deep Submicron State-of-the-Art ESD Design. [Citation Graph (0, 0)][DBLP ] Conf ] Magdy S. Abadir , Li-C. Wang Verification and Validation of Complex Digital Systems: An Industrial Perspective. [Citation Graph (0, 0)][DBLP ] Conf ] Noel R. Strader , Gérard Memmi , Carl Pixley Application of Formal Verification to Design Creation and Implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Foty , David Binkley Re-Connecting MOS Modeling and Circuit Design: New Methods for Design Quality. [Citation Graph (0, 0)][DBLP ] Conf ] Narain Arora , N. S. Nagaraj Interconnect Modeling for Timing, Signal Integrity and Reliability. [Citation Graph (0, 0)][DBLP ] Conf ] David Blaauw , Rajendran Panda On-Chip Inductance Extraction and Modelin. [Citation Graph (0, 0)][DBLP ] Conf ] Rick Merritt , Richard Goering The 50-Million Transistor Chip: The Quality Challenge for 2001. [Citation Graph (0, 0)][DBLP ] Conf ] Tak Young Monterey Design. [Citation Graph (0, 0)][DBLP ] Conf ] Hajimi Sasaki Future Platform for Mobile Communication. [Citation Graph (0, 0)][DBLP ] Conf ] Joe Costello Delivering Quality Delivers Profits. [Citation Graph (0, 0)][DBLP ] Conf ] Raul Camposano The Expanding Use of Formal Techniques in Electronic Design. [Citation Graph (0, 0)][DBLP ] Conf ] Edward C. Ross IC Design Methodology in the Foundry Era: Introducing , Heads-Up(tm) Design. [Citation Graph (0, 0)][DBLP ] Conf ] Amjad Hajjar , Tom Chen , Isabelle Munn , Anneliese Amschler Andrews , Maria Bjorkman Stopping Criteria Comparison: Towards High Quality Behavioral Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Umberto Rossi , Andrea Fedeli , Marco Boschini , Franco Toto Concrete Impact of Formal Verification on Quality in IP Design and Implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Zan Yang , Byeong Min , Gwan Choi Simulation Using Code-Perturbation: Black- and White-Box Approach. [Citation Graph (0, 0)][DBLP ] Conf ] F. Sforza , L. Battú , M. Brunelli , A. Castelnuovo , M. Magnaghi A "Design for Verification" Methodology. [Citation Graph (0, 0)][DBLP ] Conf ] Mohammed El Shobaki , Lennart Lindh A Hardware and Software Monitor for High-Level System-on-Chip Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Paul Kartschoke , Shervin Hojat Techniques that Improved the Timing Convergence of the Gekko PowerPC Microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Gulsun Yasar , Charles Chiu , Robert A. Proctor , James P. Libous I/O Cell Placement and Electrical Checking Methodology for ASICs with Peripheral I/Os. [Citation Graph (0, 0)][DBLP ] Conf ] Giora Ben-Yaacov , Edward P. Stone , Richard Goldman Applying Moore's Technology Adoption Life Cycle Model to Quality of EDA Software. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew B. Kahng , Stefanus Mantik A System for Automatic Recording and Prediction of Design Quality Metrics. [Citation Graph (0, 0)][DBLP ] Conf ] Pinhong Chen , Kurt Keutzer , Desmond Kirkpatrick Scripting for EDA Tools: A Case Study. [Citation Graph (0, 0)][DBLP ] Conf ] Akira Matsuzawa High Quality Analog CMOS and Mixed Signal LSI Design. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth L. Shepard CAD Issues for CMOS VLSI Design in SOI. [Citation Graph (0, 0)][DBLP ] Conf ] Sheldon Wu , Fred Wang , Lie-Szu Juang Foundry's Perspective of System Integration: Quality Design and Time-to-Volume. [Citation Graph (0, 0)][DBLP ] Conf ] Choshu Ito , Kaustav Banerjee , Robert W. Dutton Analysis and Design of ESD Protection Circuits for High-Frequency/RF Applications. [Citation Graph (0, 0)][DBLP ] Conf ] J. W. McPherson Scaling-Induced Reductions in CMOS Reliability Margins and the Escalating Need for Increased Design-In Reliability Efforts. [Citation Graph (0, 0)][DBLP ] Conf ] Ninglong Lu , Ibrahim N. Hajj A Fast Coupling Aware Delay Estimation Scheme Based on Simplified Circuit Model. [Citation Graph (0, 0)][DBLP ] Conf ] Pirouz Bazargan-Sabet , Fabrice Ilponse A Model for Crosstalk Noise Evaluation in Deep Submicron Processes. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew B. Kahng , Sudhakar Muddu , Niranjan Pol , Devendra Vidhani Noise Model for Multiple Segmented Coupled RC Interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Qingjian Yu , Ernest S. Kuh New Efficient and Accurate Moment Matching Based Model for Crosstalk Estimation in Coupled RC Trees. [Citation Graph (0, 0)][DBLP ] Conf ] Murat R. Becer , David Blaauw , Supamas Sirichotiyakul , Chanhee Oh , Vladimir Zolotov , Jingyan Zuo , Rafi Levy , Ibrahim N. Hajj A Global Driver Sizing Tool for Functional Crosstalk Noise Avoidance. [Citation Graph (0, 0)][DBLP ] Conf ] Asim Husain Models For Interconnect Capacitance Extraction. [Citation Graph (0, 0)][DBLP ] Conf ] Tom Chen Impact of On-Chip Inductance When Transitioning from Al to Cu Based Technology. [Citation Graph (0, 0)][DBLP ] Conf ] Yusuke Nakashima , Makoto Ikeda , Kunihiro Asada Computational Cost Reduction in Extracting Inductance. [Citation Graph (0, 0)][DBLP ] Conf ] Yu Cao , Xuejue Huang , Chenming Hu , Norman Chang , Shen Lin , O. Sam Nakagawa , Weize Xie Effective On-chip Inductance Modeling for Multiple Signal Lines and Application on Repeater Insertion. [Citation Graph (0, 0)][DBLP ] Conf ] Mehdi M. Mechaik Signal Attenuation in Transmission Lines. [Citation Graph (0, 0)][DBLP ] Conf ] Wei-Chung Cheng , Massoud Pedram Memory Bus Encoding for Low Power: A Tutorial. [Citation Graph (0, 0)][DBLP ] Conf ] Geng Bai , Sudhakar Bobba , Ibrahim N. Hajj RC Power Bus Maximum Voltage Drop in Digital VLSI Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Zhenyu Tang , Lei He , Norman Chang , Shen Lin , Weize Xie , Sam Nakagawa Instruction Prediction for Step Power Reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Rongtian Zhang , Kaushik Roy , Cheng-Kok Koh , David B. Janes Power Trends and Performance Characterization of 3-Dimensional Integration for Future Technology Generations. [Citation Graph (0, 0)][DBLP ] Conf ] Juan A. Montiel-Nelson , V. de Armas , Roberto Sarmiento , Antonio Núñez A Compact Layout Technique for Reducing Switching Current Effects in High Speed Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Bill Alexander , Jacques Benkoski 0.13 micron: Will the Speed Bumps Slow the Race to Market? [Citation Graph (0, 0)][DBLP ] Conf ] Wojciech Maly Quality of Design from an IC Manufacturing Perspective. [Citation Graph (0, 0)][DBLP ] Conf ] Vinod Agrawal Embedded Test Leads to Embedded Quality. [Citation Graph (0, 0)][DBLP ] Conf ] Aki Fujimura Quality on Time. [Citation Graph (0, 0)][DBLP ] Conf ] Philippe Magarshack Quality of SoC Designs through Quality of the Design Flow: Status and Needs. [Citation Graph (0, 0)][DBLP ] Conf ] Nguyen Quang Trung , Krystyna Siekierska Soft Core Based Model of a Microcomputer Family. [Citation Graph (0, 0)][DBLP ] Conf ] Tung-Yang Chen , Ming-Dou Ker Design on ESD Protection Circuit with Very Low and Constant Input Capacitance. [Citation Graph (0, 0)][DBLP ] Conf ] Subhasish Mitra , Edward J. McCluskey Diversity Techniques for Concurrent Error Detection. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Verplaetse Refinements of Rent's Rule Allowing Accurate Interconnect Complexity Modeling. [Citation Graph (0, 0)][DBLP ] Conf ] Vlado Vorisek Test Pattern Generators for Distributed and Embedded Built-in Self-Test at Register Transfer Level. [Citation Graph (0, 0)][DBLP ] Conf ] S. Klupsch Design, Integration and Validation of Heterogeneous Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Geng Bai , Sudhakar Bobba , Ibrahim N. Hajj RC Power Bus Maximum Voltage Drop in Digital VLSI Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Ming-Dou Ker , Wen-Yu Lo , Tung-Yang Chen , Howard Tang , S.-S. Chen , M.-C. Wang Compact Layout Rule Extraction for Latchup Prevention in a 0.25-?m Shallow-Trench-Isolation Silicided Bulk CMOS Process. [Citation Graph (0, 0)][DBLP ] Conf ] Alexander Zemliak One Approach to Analog System Design Problem Formulation. [Citation Graph (0, 0)][DBLP ] Conf ] Mark Birnbaum , Charlene C. Johnson VSIA Quality Metrics for IP and SoC. [Citation Graph (0, 0)][DBLP ] Conf ] Wei Li , Qiang Li , J. S. Yuan , Joshua McConkey , Yuan Chen , Sundar Chetlur , Jonathan Zhou , A. S. Oates Hot-carrier-Induced Circuit Degradation for 0.18 µm CMOS Technology. [Citation Graph (0, 0)][DBLP ] Conf ] Tom Egan , Samiha Mourad Verification of Embedded Phase-Locked Loops. [Citation Graph (0, 0)][DBLP ] Conf ] Alexander Korshak , Jyh-Chwen Lee An Effective Current Source Cell Model for VDSM Delay Calculation. [Citation Graph (0, 0)][DBLP ] Conf ] Mehdi M. Mechaik An Evaluation of Single-Ended and Differential Impedance in PCBs. [Citation Graph (0, 0)][DBLP ] Conf ] Yi-Min Jiang , Han Young Koh , Kwang-Ting Cheng HRM - A Hierarchical Simulator for Full-Chip Power Network Reliability Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Ning Zhu , Han Young Koh Power Grid Modeling Technique for Hierarchical Power Network Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Imed Ben Dhaou , Hannu Tenhunen , Vijay Sundararajan , Keshab K. Parhi Energy Efficient Signaling in Deep Submicron CMOS Technology. [Citation Graph (0, 0)][DBLP ] Conf ] Rong Lin Trading Bitwidth For Array Size: A Unified Reconfigurable Arithmetic Processor Design. [Citation Graph (0, 0)][DBLP ] Conf ] Mihaela Radu , Dan Pitica , Radu Munteanu , Cristian Posteuca Complex Reliability Evaluation of Voters for Fault Tolerant Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Josef Schmid , Timo Schüring , Christoph Smalla Using the Boundary Scan Delay Chain for Cross-Chip Delay Measurement and Characterization of Delay Modeling Flow. [Citation Graph (0, 0)][DBLP ] Conf ] Nektarios Kranitis , Mihalis Psarakis , Dimitris Gizopoulos , Antonis M. Paschalis , Yervant Zorian An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths. [Citation Graph (0, 0)][DBLP ] Conf ] Dimitris Bakalis , Dimitris Nikolos , Haridimos T. Vergos , Xrysovalantis Kavousianos On Accumulator-Based Bit-Serial Test Response Compaction Schemes. [Citation Graph (0, 0)][DBLP ] Conf ] Michel Renovell Revisiting the Classical Fault Models through a Detailed Analysis of Realistic Defects. [Citation Graph (0, 0)][DBLP ] Conf ] Wieslaw Kuzmicz , Witold A. Pleskacz , Jaan Raik , Raimund Ubar Defect-Oriented Fault Simulation and Test Generation in Digital Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Chien-Nan Jimmy Liu , Chia-Chih Yen , Jing-Yang Jou Automatic Functional Vector Generation Using the Interacting FSM Model. [Citation Graph (0, 0)][DBLP ] Conf ] Jayant Deodhar , Spyros Tragoudas Color Counting and its Application to Path Delay Fault Coverage. [Citation Graph (0, 0)][DBLP ] Conf ] Maria K. Michael , Spyros Tragoudas ATPG for Path Delay Faults without Path Enumeration. [Citation Graph (0, 0)][DBLP ] Conf ] Rafael Peset Llopis , Marcel Oosterhuis , Ramanathan Sethuraman , Paul E. R. Lippens , Albert van der Werf , Steffen Maul , Jim Lin HW-SW Co-Design and Verification of a Multi-Standard Video and Image Codec. [Citation Graph (0, 0)][DBLP ] Conf ] Martin Speitel , Michael Schlicht , Martin Leyh Acceleration of DAB Chipset Development by Deployment of a Real-time Rapid Prototyping Approach based on Behavioral Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Chih-Yuan Chen , Shing-Wu Tung ELITE Design Methodology of Foundation IP for Improving Synthesis Quality. [Citation Graph (0, 0)][DBLP ] Conf ] Artur Chojnacki , Lech Józwiak High-quality FPGA Designs through Functional Decomposition with Sub-function Input Support Selection Based on Information Relationship Measures. [Citation Graph (0, 0)][DBLP ] Conf ] Kazimierz Wiatr , Ernest Jamro Implementation of Multipliers in FPGA Structures. [Citation Graph (0, 0)][DBLP ] Conf ] Nader Vasseghi , Steve Ohr Consequences of Technology: What is the Impact of Electronic Design on the Quality of Life? [Citation Graph (0, 0)][DBLP ] Conf ] Ron Ross , Keith McCasland Early Detection of Design Sensitivities that Cause Yield Loss for New Products. [Citation Graph (0, 0)][DBLP ] Conf ] Emrah Acar , Lawrence T. Pileggi , Sani R. Nassif , Ying Liu Assessment of True Worst Case Circuit Performance Under Interconnect Parameter Variations. [Citation Graph (0, 0)][DBLP ] Conf ] Anne E. Gattiker , Sani R. Nassif , Rashmi Dinakar , Chris Long Timing Yield Estimation from Static Timing Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Tae-Jin Kwon , Sang-Hoon Lee , Tae-Seon Kim , Hoe-Jin Lee , Young-Kwan Park , Taek-Soo Kim , Seok-Jin Kim , Jeong-Taek Kong Performance Improvement for High Speed Devices Using E-tests and the SPICE Model. [Citation Graph (0, 0)][DBLP ] Conf ] Pierluigi Daglio , M. Araldi , M. Morbarigazzi , Carlo Roma A Fully Qualified Analog Design Flow for Non Volatile Memories Technologies. [Citation Graph (0, 0)][DBLP ] Conf ] Konstantinos Tatas , Antonios Argyriou , Minas Dasygenis , Dimitrios Soudris , Nikolaos D. Zervas Memory Hierarchy Optimization of Multimedia Applications on Programmable Embedded Cores 1. [Citation Graph (0, 0)][DBLP ] Conf ] Nai-Yin Sung , Tsung-Yi Wu A Method of Embedded Memory Access Time Measurement. [Citation Graph (0, 0)][DBLP ] Conf ] Amit Mehrotra Noise in Radio Frequency Circuits: Analysis and Design Implications. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Bendix Spice Model Quality: Process Development Viewpoint. [Citation Graph (0, 0)][DBLP ] Conf ] Yoshitaka Murasaka , Makoto Nagata , Takafumi Ohmoto , Takashi Morie , Atsushi Iwata Chip-Level Substrate Noise Analysis with Network Reduction by Fundamental Matrix Computation. [Citation Graph (0, 0)][DBLP ] Conf ] Stefano Zanella , Andrea Neviani , Enrico Zanoni , Paolo Miliozzi , Edoardo Charbon , Carlo Guardiani , Luca P. Carloni , Alberto L. Sangiovanni-Vincentelli Modeling of Substrate Noise Injected by Digital Libraries. [Citation Graph (0, 0)][DBLP ] Conf ] 