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Conferences in DBLP

International Symposium on Quality Electronic Design (isqed)
2001 (conf/isqed/2001)

  1. Yervant Zorian
    System-on-Chip: Embedded Test Strategies. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:7- [Conf]
  2. Kaushik Roy, Ali Keshavarzi
    Design and Test of Low Voltage CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:7- [Conf]
  3. Mo Tamjidi, Bejoy G. Oomman
    Redundancy Requirements for Embedded Memories. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:8- [Conf]
  4. Phil Dworsky, Warren Savage
    Fundamental Methods to Enable SoC Design and Reuse. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:9- [Conf]
  5. Andrew B. Kahng, Ronald Collett, Ton. H. van de Kraats
    Design Metrics to Achieve Design Quality. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:9- [Conf]
  6. Charvaka Duvvury
    Issues in Deep Submicron State-of-the-Art ESD Design. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:10- [Conf]
  7. Magdy S. Abadir, Li-C. Wang
    Verification and Validation of Complex Digital Systems: An Industrial Perspective. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:11-12 [Conf]
  8. Noel R. Strader, Gérard Memmi, Carl Pixley
    Application of Formal Verification to Design Creation and Implementation. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:11- [Conf]
  9. Daniel Foty, David Binkley
    Re-Connecting MOS Modeling and Circuit Design: New Methods for Design Quality. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:13- [Conf]
  10. Narain Arora, N. S. Nagaraj
    Interconnect Modeling for Timing, Signal Integrity and Reliability. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:13- [Conf]
  11. David Blaauw, Rajendran Panda
    On-Chip Inductance Extraction and Modelin. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:14- [Conf]
  12. Rick Merritt, Richard Goering
    The 50-Million Transistor Chip: The Quality Challenge for 2001. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:15-0 [Conf]
  13. Tak Young
    Monterey Design. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:19-20 [Conf]
  14. Hajimi Sasaki
    Future Platform for Mobile Communication. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:21-22 [Conf]
  15. Joe Costello
    Delivering Quality Delivers Profits. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:23-24 [Conf]
  16. Raul Camposano
    The Expanding Use of Formal Techniques in Electronic Design. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:25-26 [Conf]
  17. Edward C. Ross
    IC Design Methodology in the Foundry Era: Introducing , Heads-Up(tm) Design. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:27-0 [Conf]
  18. Amjad Hajjar, Tom Chen, Isabelle Munn, Anneliese Amschler Andrews, Maria Bjorkman
    Stopping Criteria Comparison: Towards High Quality Behavioral Verification. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:31-37 [Conf]
  19. Umberto Rossi, Andrea Fedeli, Marco Boschini, Franco Toto
    Concrete Impact of Formal Verification on Quality in IP Design and Implementation. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:38-43 [Conf]
  20. Zan Yang, Byeong Min, Gwan Choi
    Simulation Using Code-Perturbation: Black- and White-Box Approach. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:44-49 [Conf]
  21. F. Sforza, L. Battú, M. Brunelli, A. Castelnuovo, M. Magnaghi
    A "Design for Verification" Methodology. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:50-55 [Conf]
  22. Mohammed El Shobaki, Lennart Lindh
    A Hardware and Software Monitor for High-Level System-on-Chip Verification. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:56-0 [Conf]
  23. Paul Kartschoke, Shervin Hojat
    Techniques that Improved the Timing Convergence of the Gekko PowerPC Microprocessor. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:65-70 [Conf]
  24. Gulsun Yasar, Charles Chiu, Robert A. Proctor, James P. Libous
    I/O Cell Placement and Electrical Checking Methodology for ASICs with Peripheral I/Os. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:71-75 [Conf]
  25. Giora Ben-Yaacov, Edward P. Stone, Richard Goldman
    Applying Moore's Technology Adoption Life Cycle Model to Quality of EDA Software. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:76-80 [Conf]
  26. Andrew B. Kahng, Stefanus Mantik
    A System for Automatic Recording and Prediction of Design Quality Metrics. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:81-86 [Conf]
  27. Pinhong Chen, Kurt Keutzer, Desmond Kirkpatrick
    Scripting for EDA Tools: A Case Study. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:87-0 [Conf]
  28. Akira Matsuzawa
    High Quality Analog CMOS and Mixed Signal LSI Design. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:97-104 [Conf]
  29. Kenneth L. Shepard
    CAD Issues for CMOS VLSI Design in SOI. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:105-110 [Conf]
  30. Sheldon Wu, Fred Wang, Lie-Szu Juang
    Foundry's Perspective of System Integration: Quality Design and Time-to-Volume. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:111-116 [Conf]
  31. Choshu Ito, Kaustav Banerjee, Robert W. Dutton
    Analysis and Design of ESD Protection Circuits for High-Frequency/RF Applications. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:117-122 [Conf]
  32. J. W. McPherson
    Scaling-Induced Reductions in CMOS Reliability Margins and the Escalating Need for Increased Design-In Reliability Efforts. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:123-0 [Conf]
  33. Ninglong Lu, Ibrahim N. Hajj
    A Fast Coupling Aware Delay Estimation Scheme Based on Simplified Circuit Model. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:133-138 [Conf]
  34. Pirouz Bazargan-Sabet, Fabrice Ilponse
    A Model for Crosstalk Noise Evaluation in Deep Submicron Processes. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:139-144 [Conf]
  35. Andrew B. Kahng, Sudhakar Muddu, Niranjan Pol, Devendra Vidhani
    Noise Model for Multiple Segmented Coupled RC Interconnects. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:145-150 [Conf]
  36. Qingjian Yu, Ernest S. Kuh
    New Efficient and Accurate Moment Matching Based Model for Crosstalk Estimation in Coupled RC Trees. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:151-157 [Conf]
  37. Murat R. Becer, David Blaauw, Supamas Sirichotiyakul, Chanhee Oh, Vladimir Zolotov, Jingyan Zuo, Rafi Levy, Ibrahim N. Hajj
    A Global Driver Sizing Tool for Functional Crosstalk Noise Avoidance. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:158-0 [Conf]
  38. Asim Husain
    Models For Interconnect Capacitance Extraction. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:167-172 [Conf]
  39. Tom Chen
    Impact of On-Chip Inductance When Transitioning from Al to Cu Based Technology. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:173-178 [Conf]
  40. Yusuke Nakashima, Makoto Ikeda, Kunihiro Asada
    Computational Cost Reduction in Extracting Inductance. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:179-184 [Conf]
  41. Yu Cao, Xuejue Huang, Chenming Hu, Norman Chang, Shen Lin, O. Sam Nakagawa, Weize Xie
    Effective On-chip Inductance Modeling for Multiple Signal Lines and Application on Repeater Insertion. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:185-190 [Conf]
  42. Mehdi M. Mechaik
    Signal Attenuation in Transmission Lines. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:191-0 [Conf]
  43. Wei-Chung Cheng, Massoud Pedram
    Memory Bus Encoding for Low Power: A Tutorial. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:199-204 [Conf]
  44. Geng Bai, Sudhakar Bobba, Ibrahim N. Hajj
    RC Power Bus Maximum Voltage Drop in Digital VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:205-210 [Conf]
  45. Zhenyu Tang, Lei He, Norman Chang, Shen Lin, Weize Xie, Sam Nakagawa
    Instruction Prediction for Step Power Reduction. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:211-216 [Conf]
  46. Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes
    Power Trends and Performance Characterization of 3-Dimensional Integration for Future Technology Generations. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:217-222 [Conf]
  47. Juan A. Montiel-Nelson, V. de Armas, Roberto Sarmiento, Antonio Núñez
    A Compact Layout Technique for Reducing Switching Current Effects in High Speed Circuits. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:223-0 [Conf]
  48. Bill Alexander, Jacques Benkoski
    0.13 micron: Will the Speed Bumps Slow the Race to Market? [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:229-0 [Conf]
  49. Wojciech Maly
    Quality of Design from an IC Manufacturing Perspective. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:235-236 [Conf]
  50. Vinod Agrawal
    Embedded Test Leads to Embedded Quality. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:237-238 [Conf]
  51. Aki Fujimura
    Quality on Time. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:239-240 [Conf]
  52. Philippe Magarshack
    Quality of SoC Designs through Quality of the Design Flow: Status and Needs. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:241-0 [Conf]
  53. Nguyen Quang Trung, Krystyna Siekierska
    Soft Core Based Model of a Microcomputer Family. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:245-246 [Conf]
  54. Tung-Yang Chen, Ming-Dou Ker
    Design on ESD Protection Circuit with Very Low and Constant Input Capacitance. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:247-248 [Conf]
  55. Subhasish Mitra, Edward J. McCluskey
    Diversity Techniques for Concurrent Error Detection. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:249-250 [Conf]
  56. Peter Verplaetse
    Refinements of Rent's Rule Allowing Accurate Interconnect Complexity Modeling. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:251-252 [Conf]
  57. Vlado Vorisek
    Test Pattern Generators for Distributed and Embedded Built-in Self-Test at Register Transfer Level. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:253-254 [Conf]
  58. S. Klupsch
    Design, Integration and Validation of Heterogeneous Systems. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:255-256 [Conf]
  59. Geng Bai, Sudhakar Bobba, Ibrahim N. Hajj
    RC Power Bus Maximum Voltage Drop in Digital VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:257-0 [Conf]
  60. Ming-Dou Ker, Wen-Yu Lo, Tung-Yang Chen, Howard Tang, S.-S. Chen, M.-C. Wang
    Compact Layout Rule Extraction for Latchup Prevention in a 0.25-?m Shallow-Trench-Isolation Silicided Bulk CMOS Process. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:267-272 [Conf]
  61. Alexander Zemliak
    One Approach to Analog System Design Problem Formulation. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:273-278 [Conf]
  62. Mark Birnbaum, Charlene C. Johnson
    VSIA Quality Metrics for IP and SoC. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:279-283 [Conf]
  63. Wei Li, Qiang Li, J. S. Yuan, Joshua McConkey, Yuan Chen, Sundar Chetlur, Jonathan Zhou, A. S. Oates
    Hot-carrier-Induced Circuit Degradation for 0.18 µm CMOS Technology. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:284-289 [Conf]
  64. Tom Egan, Samiha Mourad
    Verification of Embedded Phase-Locked Loops. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:290-295 [Conf]
  65. Alexander Korshak, Jyh-Chwen Lee
    An Effective Current Source Cell Model for VDSM Delay Calculation. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:296-300 [Conf]
  66. Mehdi M. Mechaik
    An Evaluation of Single-Ended and Differential Impedance in PCBs. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:301-306 [Conf]
  67. Yi-Min Jiang, Han Young Koh, Kwang-Ting Cheng
    HRM - A Hierarchical Simulator for Full-Chip Power Network Reliability Analysis. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:307-312 [Conf]
  68. Ning Zhu, Han Young Koh
    Power Grid Modeling Technique for Hierarchical Power Network Analysis. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:313-318 [Conf]
  69. Imed Ben Dhaou, Hannu Tenhunen, Vijay Sundararajan, Keshab K. Parhi
    Energy Efficient Signaling in Deep Submicron CMOS Technology. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:319-324 [Conf]
  70. Rong Lin
    Trading Bitwidth For Array Size: A Unified Reconfigurable Arithmetic Processor Design. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:325-330 [Conf]
  71. Mihaela Radu, Dan Pitica, Radu Munteanu, Cristian Posteuca
    Complex Reliability Evaluation of Voters for Fault Tolerant Designs. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:331-336 [Conf]
  72. Josef Schmid, Timo Schüring, Christoph Smalla
    Using the Boundary Scan Delay Chain for Cross-Chip Delay Measurement and Characterization of Delay Modeling Flow. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:337-342 [Conf]
  73. Nektarios Kranitis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian
    An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:343-349 [Conf]
  74. Dimitris Bakalis, Dimitris Nikolos, Haridimos T. Vergos, Xrysovalantis Kavousianos
    On Accumulator-Based Bit-Serial Test Response Compaction Schemes. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:350-0 [Conf]
  75. Michel Renovell
    Revisiting the Classical Fault Models through a Detailed Analysis of Realistic Defects. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:359-364 [Conf]
  76. Wieslaw Kuzmicz, Witold A. Pleskacz, Jaan Raik, Raimund Ubar
    Defect-Oriented Fault Simulation and Test Generation in Digital Circuits. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:365-371 [Conf]
  77. Chien-Nan Jimmy Liu, Chia-Chih Yen, Jing-Yang Jou
    Automatic Functional Vector Generation Using the Interacting FSM Model. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:372-377 [Conf]
  78. Jayant Deodhar, Spyros Tragoudas
    Color Counting and its Application to Path Delay Fault Coverage. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:378-383 [Conf]
  79. Maria K. Michael, Spyros Tragoudas
    ATPG for Path Delay Faults without Path Enumeration. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:384-0 [Conf]
  80. Rafael Peset Llopis, Marcel Oosterhuis, Ramanathan Sethuraman, Paul E. R. Lippens, Albert van der Werf, Steffen Maul, Jim Lin
    HW-SW Co-Design and Verification of a Multi-Standard Video and Image Codec. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:393-398 [Conf]
  81. Martin Speitel, Michael Schlicht, Martin Leyh
    Acceleration of DAB Chipset Development by Deployment of a Real-time Rapid Prototyping Approach based on Behavioral Synthesis. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:399-404 [Conf]
  82. Chih-Yuan Chen, Shing-Wu Tung
    ELITE Design Methodology of Foundation IP for Improving Synthesis Quality. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:405-408 [Conf]
  83. Artur Chojnacki, Lech Józwiak
    High-quality FPGA Designs through Functional Decomposition with Sub-function Input Support Selection Based on Information Relationship Measures. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:409-414 [Conf]
  84. Kazimierz Wiatr, Ernest Jamro
    Implementation of Multipliers in FPGA Structures. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:415-0 [Conf]
  85. Nader Vasseghi, Steve Ohr
    Consequences of Technology: What is the Impact of Electronic Design on the Quality of Life? [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:421-0 [Conf]
  86. Ron Ross, Keith McCasland
    Early Detection of Design Sensitivities that Cause Yield Loss for New Products. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:427-430 [Conf]
  87. Emrah Acar, Lawrence T. Pileggi, Sani R. Nassif, Ying Liu
    Assessment of True Worst Case Circuit Performance Under Interconnect Parameter Variations. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:431-436 [Conf]
  88. Anne E. Gattiker, Sani R. Nassif, Rashmi Dinakar, Chris Long
    Timing Yield Estimation from Static Timing Analysis. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:437-442 [Conf]
  89. Tae-Jin Kwon, Sang-Hoon Lee, Tae-Seon Kim, Hoe-Jin Lee, Young-Kwan Park, Taek-Soo Kim, Seok-Jin Kim, Jeong-Taek Kong
    Performance Improvement for High Speed Devices Using E-tests and the SPICE Model. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:443-0 [Conf]
  90. Pierluigi Daglio, M. Araldi, M. Morbarigazzi, Carlo Roma
    A Fully Qualified Analog Design Flow for Non Volatile Memories Technologies. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:451-455 [Conf]
  91. Konstantinos Tatas, Antonios Argyriou, Minas Dasygenis, Dimitrios Soudris, Nikolaos D. Zervas
    Memory Hierarchy Optimization of Multimedia Applications on Programmable Embedded Cores 1. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:456-461 [Conf]
  92. Nai-Yin Sung, Tsung-Yi Wu
    A Method of Embedded Memory Access Time Measurement. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:462-0 [Conf]
  93. Amit Mehrotra
    Noise in Radio Frequency Circuits: Analysis and Design Implications. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:469-476 [Conf]
  94. Peter Bendix
    Spice Model Quality: Process Development Viewpoint. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:477-481 [Conf]
  95. Yoshitaka Murasaka, Makoto Nagata, Takafumi Ohmoto, Takashi Morie, Atsushi Iwata
    Chip-Level Substrate Noise Analysis with Network Reduction by Fundamental Matrix Computation. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:482-487 [Conf]
  96. Stefano Zanella, Andrea Neviani, Enrico Zanoni, Paolo Miliozzi, Edoardo Charbon, Carlo Guardiani, Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli
    Modeling of Substrate Noise Injected by Digital Libraries. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:488-0 [Conf]
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