Conferences in DBLP
Steering/Advisory Committee. [Citation Graph (0, 0)][DBLP ] Conf ] Technical Subcommittees. [Citation Graph (0, 0)][DBLP ] Conf ] Conference at a Glance. [Citation Graph (0, 0)][DBLP ] Conf ] Welcome Notes. [Citation Graph (0, 0)][DBLP ] Conf ] Organizing Committee. [Citation Graph (0, 0)][DBLP ] Conf ] Anirudh Devgan , Ruchir Puri , Sachin Sapatnaker , Tanay Karnik , Rajiv V. Joshi Design of sub-90nm Circuits and Design Methodologies. [Citation Graph (0, 0)][DBLP ] Conf ] Anirudh Devgan , Luca Daniel , Byron Krauter , Lei He Modeling and Design of Chip-Package Interface. [Citation Graph (0, 0)][DBLP ] Conf ] Pallab K. Chatterjee IP Creation and Use What Roadblocks are Ahead or it is Just Clear and Bumpy Road? [Citation Graph (0, 0)][DBLP ] Conf ] John Kibarian Enabling True Design for Manufacturability. [Citation Graph (0, 0)][DBLP ] Conf ] Ashok K. Sinha Recent Progress and Remaining Challenges in Pattern Transfer Technologies for Advanced Chip Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Joseph Sawicki Shifting Perspective on DFM. [Citation Graph (0, 0)][DBLP ] Conf ] Aaron N. Ng , Igor L. Markov Toward Quality EDA Tools and Tool Flows Through High-Performance Computing. [Citation Graph (0, 0)][DBLP ] Conf ] Alex Gyure , Alireza Kasnavi , Sam C. Lo , Peivand F. Tehrani , William Shu , Mahmoud Shahram , Joddy W. Wang , Jindrich Zejda Noise Library Characterization for Large Capacity Static Noise Analysis Tools. [Citation Graph (0, 0)][DBLP ] Conf ] Qianying Tang , Jianwen Zhu Two-Dimensional Layout Migration by Soft Constraint Satisfaction. [Citation Graph (0, 0)][DBLP ] Conf ] Luo Chun , Yang Jun , Shi Longxing , Wu XuFan , Zhang Yu Domain Strategy and Coverage Metric for Validation. [Citation Graph (0, 0)][DBLP ] Conf ] Dongku Kang , Yiran Chen , Kaushik Roy Power Supply Noise-Aware Scheduling and Allocation for DSP Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Shivakumar Swaminathan , Sanjay B. Patel , James Dieffenderfer , Joel Silberman Reducing Power Consumption during TLB Lookups in a PowerPC Embedded Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Kee-Jong Kim , Chris H. Kim , Kaushik Roy TFT-LCD Application Specific Low Power SRAM Using Charge-Recycling Technique. [Citation Graph (0, 0)][DBLP ] Conf ] David Roberts , Todd M. Austin , David Blaauw , Trevor N. Mudge , Krisztián Flautner Error Analysis for the Support of Robust Voltage Scaling. [Citation Graph (0, 0)][DBLP ] Conf ] Bhavana Jharia , Sankar Sarkar , R. P. Agarwal Analytical Study of Impact Ionization and Subthreshold Current in Submicron n-MOSFET. [Citation Graph (0, 0)][DBLP ] Conf ] Afshin Abdollahi , Farzan Fallah , Massoud Pedram Analysis and Optimization of Static Power Considering Transition Dependency of Leakage Current in VLSI Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Jayakumaran Sivagnaname , Hung C. Ngo , Kevin J. Nowka , Robert K. Montoye , Richard B. Brown Controlled-Load Limited Switch Dynamic Logic Circuit. [Citation Graph (0, 0)][DBLP ] Conf ] Harmander Deogun , Rahul M. Rao , Dennis Sylvester , Richard B. Brown , Kevin J. Nowka Dynamically Pulsed MTCMOS with Bus Encoding for Total Power and Crosstalk Minimization. [Citation Graph (0, 0)][DBLP ] Conf ] Jin He , Jane Xi , Mansun Chan , Hui Wan , Mohan V. Dunga , Babak Heydari , Ali M. Niknejad , Chenming Hu Charge-Based Core and the Model Architecture of BSIM5. [Citation Graph (0, 0)][DBLP ] Conf ] Lionel Riviere-Cazaux , Kevin Lucas , Jon Fitch Integration Of Design For Manufacturability (DFM) Practices In Design Flows. [Citation Graph (0, 0)][DBLP ] Conf ] Carlo Roma , Pierluigi Daglio , Guido De Sandre , Marco Pasotti , Marco Poles How Circuit Analysis and Yield Optimization Can Be Used To Detect Circuit Limitations Before Silicon Results. [Citation Graph (0, 0)][DBLP ] Conf ] Mini Nanua , David Blaauw , Chanhee Oh Leakage Current Modeling in PD SOI Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Jasjeet Kaur A Balanced Scorecard for Systemic Quality in Electronic Design Automation: An Implementation Method for an EDA Company. [Citation Graph (0, 0)][DBLP ] Conf ] Arun Shrimali , Anand Venkitachalam , Ravi Arora Issues and Challenges in Ramp to Production. [Citation Graph (0, 0)][DBLP ] Conf ] C. K. Tang , Parag K. Lala , James Patrick Parkerson A Technique for Designing Totally Self-Checking Domino Logic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] C. Talarico , B. Pillilli , K. L. Vakati , J. M. Wang Early Assessment of Leakage Power for System Level Design. [Citation Graph (0, 0)][DBLP ] Conf ] Zhaojun Wo , Israel Koren Technology Mapping for Reliability Enhancement in Logic Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] DiaaEldin Khalil , Mohamed Dessouky , Vincent Bourguet , Marie-Minerve Louërat , Andreia Cathelin , Hani Ragai Evaluation of Capacitor Ratios in Automated Accurate Common-Centroid Capacitor Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Behnam Amelifard , Farzan Fallah , Massoud Pedram Closing the Gap between Carry Select Adder and Ripple Carry Adder: A New Class Closing the Gap between Carry Select Adder and Ripple Carry Adder: A New Class of Low-Power High-Performance Adders. [Citation Graph (0, 0)][DBLP ] Conf ] Atsushi Kurokawa , Masaharu Yamamoto , Nobuto Ono , Tetsuro Kage , Yasuaki Inoue , Hiroo Masuda Capacitance and Yield Evaluations Using a 90-nm Process Technology Based on the Dense Power-Ground Interconnect Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Haixia Gao , Yintang Yang , Xiaohua Ma , Gang Dong Testing for Resistive Shorts in FPGA Interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Ewa Sokolowska , M. Barszcz , Bozena Kaminska TED Thermo Electrical Designer: A New Physical Design Verification Tool. [Citation Graph (0, 0)][DBLP ] Conf ] Yong-Chan Ban , Soo-Han Choi , Ki-Hung Lee , Dong-Hyun Kim , Ji-Suk Hong , Yoo-Hyon Kim , Moon-Hyun Yoo , Jeong-Taek Kong A Fast Lithography Verification Framework for Litho-Friendly Layout Design. [Citation Graph (0, 0)][DBLP ] Conf ] Harmander Deogun , Dennis Sylvester , David Blaauw Gate-Level Mitigation Techniques for Neutron-Induced Soft Error Rate. [Citation Graph (0, 0)][DBLP ] Conf ] Hua Xiang , Kai-Yuan Chao , Martin D. F. Wong Exact Algorithms for Coupling Capacitance Minimization by Adding One Metal Layer. [Citation Graph (0, 0)][DBLP ] Conf ] J. Huynh , B. Ngo , M. Pham , Lili He Design of a 10-bit TSMC 0.25um CMOS Digital to Analog Converter. [Citation Graph (0, 0)][DBLP ] Conf ] R. Castagnetti , R. Venkatraman , B. Bartz , C. Monzel , T. Briscoe , Andres Teene , S. Ramesh A High-Performance SRAM Technology With Reduced Chip-Level Routing Congestion for SoC. [Citation Graph (0, 0)][DBLP ] Conf ] Khadija Stewart , Themistoklis Haniotakis , Spyros Tragoudas Design and Evaluation of a Security Scheme for Sensor Networks. [Citation Graph (0, 0)][DBLP ] Conf ] M. Welling , Spyros Tragoudas , Haibo Wang A Minimum Cut Based Re-Synthesis Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Young-Seok Hong , Heeseok Lee , Joon-Ho Choi , Moon-Hyun Yoo , Jeong-Taek Kong Analysis for Complex Power Distribution Networks Considering Densely Populated Vias. [Citation Graph (0, 0)][DBLP ] Conf ] Yuchun Ma , Xianlong Hong , Sheqin Dong , Song Chen , Chung-Kuan Cheng Buffer Planning Algorithm Based on Partial Clustered Floorplanning. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Keating IP Quality: A Design, Not a Verification Problem. [Citation Graph (0, 0)][DBLP ] Conf ] Emmanouil Kalligeros , D. Kaseridis , Xrysovalantis Kavousianos , Dimitris Nikolos Reseeding-Based Test Set Embedding with Reduced Test Sequences. [Citation Graph (0, 0)][DBLP ] Conf ] Themistoklis Haniotakis , Spyros Tragoudas , G. Pani Reduced Test Application Time Based on Reachability Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Yinhe Han , Yu Hu , Huawei Li , Xiaowei Li Using MUXs Network to Hide Bunches of Scan Chains. [Citation Graph (0, 0)][DBLP ] Conf ] Ahmad A. Al-Yamani , Edward J. McCluskey BIST-Guided ATPG. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy Dynamic Test Compaction for Bridging Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Xin Wang , Charles Chiang , Jamil Kawa , Qing Su A Min-Variance Iterative Method for Fast Smart Dummy Feature Density Assignment in Chemical-Mechanical Polishing. [Citation Graph (0, 0)][DBLP ] Conf ] Michel Côté , Philippe Hurat Standard Cell Printability Grading and Hot Spot Detection. [Citation Graph (0, 0)][DBLP ] Conf ] Puneet Gupta , Andrew B. Kahng , Dennis Sylvester , Jie Yang Performance Driven OPC for Mask Cost Reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Jay Jahangiri , David Abercrombie Meeting Nanometer DPM Requirements Through DFT. [Citation Graph (0, 0)][DBLP ] Conf ] Rahul M. Rao , Kanak Agarwal , Anirudh Devgan , Kevin J. Nowka , Dennis Sylvester , Richard B. Brown Parametric Yield Analysis and Constrained-Based Supply Voltage Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Dipanjan Sengupta , Resve A. Saleh Power-Delay Metrics Revisited for 90nm CMOS Technology. [Citation Graph (0, 0)][DBLP ] Conf ] Justin Gregg , Tom W. Chen Optimization of Individual Well Adaptive Body Biasing (IWABB) Using a Multiple Objective Evolutionary Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Syed M. Alam , Frank L. Wei , Chee Lip Gan , Carl V. Thompson , Donald E. Troxel Electromigration Reliability Comparison of Cu and Al Interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Anat Dahan , Daniel Geist , Leonid Gluhovsky , Dmitry Pidan , Gil Shapir , Yaron Wolfsthal , Lyes Benalycherif , Romain Kamdem , Younes Lahbib Combining System Level Modeling with Assertion Based Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Haihua Yan , Gefu Xu , Adit D. Singh Low Voltage Test in Place of Fast Clock in DDSI Delay Test. [Citation Graph (0, 0)][DBLP ] Conf ] Nicola Bombieri , Franco Fummi , Graziano Pravadelli Functional Verification of Networked Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Maria K. Michael , Stelios Neophytou , Spyros Tragoudas Functions for Quality Transition Fault Tests. [Citation Graph (0, 0)][DBLP ] Conf ] Mikhail Popovich , Eby G. Friedman Noise Aware Decoupling Capacitors for Multi-Voltage Power Distribution Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Aishwarya Dubey P/G Pad Placement Optimization: Problem Forumulation for Best IR Drop. [Citation Graph (0, 0)][DBLP ] Conf ] Navin Srivastava , Xiaoning Qi , Kaustav Banerjee Impact of On-chip Inductance on Power Distribution Network Design for Nanometer Scale Integrated Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Qing K. Zhu , David Ayers Power Grid Planning for Microprocessors and SOCS. [Citation Graph (0, 0)][DBLP ] Conf ] Animesh Datta , Swarup Bhunia , Nilanjan Banerjee , Kaushik Roy A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks. [Citation Graph (0, 0)][DBLP ] Conf ] Suleyman Tosun , Ozcan Ozturk , Nazanin Mansouri , Ercument Arvas , Mahmut T. Kandemir , Yuan Xie , Wei-Lun Hung An ILP Formulation for Reliability-Oriented High-Level Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Haixia Gao , Yintang Yang , Xiaohua Ma , Gang Dong Analysis of the Effect of LUT Size on FPGA Area and Delay Using Theoretical Derivations. [Citation Graph (0, 0)][DBLP ] Conf ] Suleyman Tosun , Nazanin Mansouri , Ercument Arvas , Mahmut T. Kandemir , Yuan Xie , Wei-Lun Hung Reliability-Centric Hardware/Software Co-Design. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaojun Li , Bing Huang , J. Qin , X. Zhang , Michael Talmor , Z. Gur , Joseph B. Bernstein Deep Submicron CMOS Integrated Circuit Reliability Simulation with SPICE. [Citation Graph (0, 0)][DBLP ] Conf ] Henry H. Y. Chan , Zeljko Zilic Modeling Layout Effects for Sensitivity-Based Analog Circuit Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Kambiz Rahimi , Chris Diorio In-Circuit Self-Tuning of Clock Latencies. [Citation Graph (0, 0)][DBLP ] Conf ] Masanori Hashimoto , Tomonori Yamamoto , Hidetoshi Onodera Statistical Analysis of Clock Skew Variation in H-Tree Structure. [Citation Graph (0, 0)][DBLP ] Conf ] Saibal Mukhopadhyay , Keunwoo Kim , Jae-Joon Kim , Shih-Hsien Lo , Rajiv V. Joshi , Ching-Te Chuang , Kaushik Roy Modeling and Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double Gate Devices and Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Ananth Somayaji Goda , Gautam Kapila Design For Degradation : CAD Tools for Managing Transistor Degradation Mechanisms. [Citation Graph (0, 0)][DBLP ] Conf ] Puneet Gupta , Andrew B. Kahng , Puneet Sharma A Practical Transistor-Level Dual Threshold Voltage Assignment Methodology. [Citation Graph (0, 0)][DBLP ] Conf ] Oleg Semenov , H. Sarbishaei , Manoj Sachdev Analysis and Design of LVTSCR-based EOS/ESD Protection Circuits for Burn-in Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Amit Laknaur , Haibo Wang Built-In-Self-Testing Techniques for Programmable Capacitor Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Daniela De Venuto , Grazia Marchione , Leonardo Reyneri A codesign tool to validate and improve an FPGA based test strategy for high resolution audio ADC. [Citation Graph (0, 0)][DBLP ] Conf ] Lampros Dermentzoglou , Y. Tsiatouhas , Angela Arapoyanni A Built-In Self-Test Scheme for Differential Ring Oscillators. [Citation Graph (0, 0)][DBLP ] Conf ] Swarup Bhunia , Hamid Mahmoodi-Meimand , Debjyoti Ghosh , Kaushik Roy Power Reduction in Test-Per-Scan BIST with Supply Gating and Efficient Scan Partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Mark S. Lundstrom , Philip Wong , Kazuo Yano Nanoelectronics: Evolution or Revolution? [Citation Graph (0, 0)][DBLP ] Conf ] Lech Józwiak , Kaustav Banerjee Plenary Session 2P. [Citation Graph (0, 0)][DBLP ] Conf ] Aki Fujimura Quality and EDA. [Citation Graph (0, 0)][DBLP ] Conf ] Kurt A. Wolf IP Quality: A New Model that Faces Methodology and Management Challenges. [Citation Graph (0, 0)][DBLP ] Conf ] Bernard Candaele SoC Engineering Trends as Impacted by New Applications and System Level Requirements. [Citation Graph (0, 0)][DBLP ] Conf ] Jihyun Lee , Yong-Bin Kim ASLIC: A Low Power CMOS Analog Circuit Design Automation. [Citation Graph (0, 0)][DBLP ] Conf ] Yuanzhong (Paul) Zhou , Duane Connerney , Ronald Carroll , Timwah Luk Modeling MOS Snapback for Circuit-Level ESD Simulation Using BSIM3 and VBIC Models. [Citation Graph (0, 0)][DBLP ] Conf ] Subhrajit Bhattacharya , John A. Darringer , Daniel L. Ostapko , Youngsoo Shin A Mask Reuse Methodology for Reducing System-on-a-Chip Cost. [Citation Graph (0, 0)][DBLP ] Conf ] Saibal Mukhopadhyay , Hamid Mahmoodi-Meimand , Kaushik Roy Design of High Performance Sense Amplifier Using Independent Gate Control in sub-50nm Double-Gate MOSFET. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaojun Li , Joerg D. Walter , Joseph B. Bernstein Simulating and Improving Microelectronic Device Reliability by Scaling Voltage and Temperature. [Citation Graph (0, 0)][DBLP ] Conf ] Vishal Gupta , Gabriel A. Rincón-Mora Predicting and Designing for the Impact of Process Variations and Mismatch on the Trim Range and Yield of Bandgap References. [Citation Graph (0, 0)][DBLP ] Conf ] Norman G. Gunther , Emad Hamadeh , Darrell Niemann , Iliya Pesic , Mahmud Rahman Modeling Intrinsic Fluctuations in Decananometer MOS Modeling Intrinsic Fluctuations in Decananometer MOS. [Citation Graph (0, 0)][DBLP ] Conf ] Paul Friedberg , Yu Cao , Jason Cain , Ruth Wang , Jan M. Rabaey , Costas J. Spanos Modeling Within-Die Spatial Correlation Effects for Process-Design Co-Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Vishak Venkatraman , Wayne Burleson Robust Multi-Level Current-Mode On-Chip Interconnect Signaling in the Presence of Process Variations. [Citation Graph (0, 0)][DBLP ] Conf ] Sreeram Chandrasekar , Gaurav Kumar Varshney , V. Visvanathan A Comprehensive Methodology for Noise Characterization of ASIC Cell Libraries. [Citation Graph (0, 0)][DBLP ] Conf ] Shahin Nazarian , Massoud Pedram , Emre Tuncer , Tao Lin Sensitivity-Based Gate Delay Propagation in Static Timing Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Zhenyu Qi , Hang Li , Sheldon X.-D. Tan , Lifeng Wu , Yici Cai , Xianlong Hong Fast Decap Allocation Algorithm For Robust On-Chip Power Delivery. [Citation Graph (0, 0)][DBLP ] Conf ] Deepak C. Sekar Clock trees: differential or single ended?. [Citation Graph (0, 0)][DBLP ] Conf ] Bill McCaffrey Exploring the Challenges in Creating a High-Quality Mainstream Design Solution for System-in-Package (SiP) Design. [Citation Graph (0, 0)][DBLP ] Conf ] Anru Wang , Wayne Wei-Ming Dai Design and Analysis of Area-IO DRAM/Logic Integration with System-in-a-Package(SiP). [Citation Graph (0, 0)][DBLP ] Conf ] Chung-Seok (Andy) Seo , Abhijit Chatterjee , Nan M. Jokerst This paper presents a cost-effective area-IO DRAM A CAD Tool and Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Meigen Shen , Li-Rong Zheng , Esa Tjukanoff , Jouni Isoaho , Hannu Tenhunen Concurrent Chip Package Design for Global Clock Distribution Network Using Standing Wave Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Muzhou Shao , Youxin Gao , Li-Pen Yuan , Hung-Ming Chen , Martin D. F. Wong Current Calculation on VLSI Signal Interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Atsushi Kurokawa , Toshiki Kanamoto , Tetsuya Ibe , Akira Kasebe , Chang Wei Fong , Tetsuro Kage , Yasuaki Inoue , Hiroo Masuda Dummy Filling Methods for Reducing Interconnect Capacitance and Number of Fills. [Citation Graph (0, 0)][DBLP ] Conf ] Vinita V. Deodhar , Jeffrey A. Davis Voltage Scaling, Wire Sizing and Repeater Insertion Design Rules for Wave-Pipelined VLSI Global Interconnect Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Jiaxing Sun , Yun Zheng , Qing Ye , Tianchun Ye Interconnect Delay and Slew Metrics Using the First Three Moments. [Citation Graph (0, 0)][DBLP ] Conf ] Pu Liu , Zhenyu Qi , Sheldon X.-D. Tan Passive Hierarchical Model Order Reduction and Realization of RLCM Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Meng-Chiou Wu , Rung-Bin Lin Reticle Floorplanning and Wafer Dicing for Multiple Project Wafers. [Citation Graph (0, 0)][DBLP ] Conf ] Jingyu Xu , Xianlong Hong , Tong Jing , Yang Yang Obstacle-Avoiding Rectilinear Minimum-Delay Steiner Tree Construction towards IP-Block-Based SOC Design. [Citation Graph (0, 0)][DBLP ] Conf ] Hua Xiang , I-Min Liu , Martin D. F. Wong Wire Planning with Bounded Over-the-Block Wires. [Citation Graph (0, 0)][DBLP ] Conf ] Song Chen , Xianlong Hong , Sheqin Dong , Yuchun Ma , Chung-Kuan Cheng Floorplanning with Consideration of White Space Resource Distribution for Repeater Planning. [Citation Graph (0, 0)][DBLP ] Conf ] Wei-Lun Hung , Yuan Xie , Narayanan Vijaykrishnan , Charles Addo-Quaye , Theo Theocharides , Mary Jane Irwin Thermal-Aware Floorplanning Using Genetic Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Srinivasa R. Sridhara , Naresh R. Shanbhag , Ganesh Balamurugan Joint Equalization and Coding for On-Chip Bus Communication. [Citation Graph (0, 0)][DBLP ] Conf ] Sani R. Nassif , Zhuo Li A More Effective CEFF . [Citation Graph (0, 0)][DBLP ] Conf ] Chung-Kuan Tsai , Malgorzata Marek-Sadowska An Interconnect Insensitive Linear Time-Varying Driver Model for Static Timing Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Ali Zahabi , Omid Shoaei , Yarallah Koolivand Design of a Band-Pass Pseudo-2-Path Switched Capacitor Ladder Filter. [Citation Graph (0, 0)][DBLP ] Conf ] Payam Heydari Design Considerations for Low-Power Ultra Wideband Receivers. [Citation Graph (0, 0)][DBLP ] Conf ] Dinesh Patil , Sunghee Yun , Seung-Jean Kim , Alvin Cheung , Mark Horowitz , Stephen P. Boyd A New Method for Design of Robust Digital Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Hao Yu , Lei He Staggered Twisted-Bundle Interconnect for Crosstalk and Delay Reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Wei Ling , Yvon Savaria Analysis of Wave-Pipelined Domino Logic Circuit and Clocking Styles Subject to Parametric Variations. [Citation Graph (0, 0)][DBLP ] Conf ] Andres Teene , Bob Davis , R. Castagnetti , J. Brown , S. Ramesh Impact of Interconnect Process Variations on Memory Performance and Design. [Citation Graph (0, 0)][DBLP ] Conf ] 