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International Symposium on Quality Electronic Design (isqed)
2004 (conf/isqed/2004)

  1. Jeff Davis
    Interconnect Modeling. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:7- [Conf]
  2. Kerry Bernstein
    Nanometer-Scale CMOS Devices. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:7- [Conf]
  3. Andrew B. Kahng
    Manufacturability . [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:8- [Conf]
  4. Kaushik Roy
    Low-Power Design. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:8- [Conf]
  5. Nagib Hakim
    Coping with Uncertainty. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:9- [Conf]
  6. Tets Maniwa, Pallab K. Chatterjee
    Evening Panel Discussion: DFM PDK's: Where Do They Belong To? Are Process Design Kits (PDKs) the Answer for Modern Design for Manufacturing (DFM) Issues? [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:11-13 [Conf]
  7. John Chilton
    Simplify: Enable Quality, Enable Innovation. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:17- [Conf]
  8. Marc E. Levitt
    Design for Manufacturing? Design for Yield!!! [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:19- [Conf]
  9. Larry Bock
    Why Nano Technology? Why Now? And What Might Its Impact on Electronics. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:21- [Conf]
  10. Fang Fang, Jianwen Zhu
    Calligrapher: A New Layout Migration Engine Based on Geometric Closeness. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:25-30 [Conf]
  11. Kuang-Kuo Lin, Sudhakar Kale, Aditi Nigam
    Methodology for Automated Layout Migration for 90 nm Itanium®2 Processor Design. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:31-35 [Conf]
  12. Masanori Hashimoto, Kazunori Fujimori, Hidetoshi Onodera
    Automatic Generation of Standard Cell Library in VDSM Technologies. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:36-41 [Conf]
  13. Jin He, Xuemei Xi, Mansun Chan, Chung-Hsun Lin, Ali M. Niknejad, Chenming Hu
    A Non-Charge-Sheet Based Analytical Model of Undoped Symmetric Double-Gate MOSFETs Using SPP Approach. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:45-50 [Conf]
  14. Y. Z. Xu, O. Pohland, C. Cai, H. Puchner
    Leakage Increase of Narrow and Short BCPMOS. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:51-54 [Conf]
  15. Huifang Qin, Yu Cao, Dejan Markovic, Andrei Vladimirescu, Jan M. Rabaey
    SRAM Leakage Suppression by Minimizing Standby Supply Voltage. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:55-60 [Conf]
  16. Zhu Pan, Yici Cai, Sheldon X.-D. Tan, Zuying Luo, Xianlong Hong
    Transient Analysis of On-Chip Power Distribution Networks Using Equivalent Circuit Modeling. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:63-68 [Conf]
  17. Lucanus Simonson, King Ho Tam, Nataraj Akkiraju, Mosur Mohan, Lei He
    Leveraging Delay Slack in Flip-Flop and Buffer Insertion for Power Reduction. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:69-74 [Conf]
  18. Herng-Jer Lee, Chia-Chi Chu, Wu-Shiung Feng
    Moment Computations of Nonuniform Distributed Coupled RLC Trees with Applications to Estimating Crosstalk Noise. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:75-80 [Conf]
  19. Daniela De Venuto
    New Test Access for High Resolution SD ADC's by Using the Noise Transfer Function Evaluation. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:81-85 [Conf]
  20. Stuart McCracken, Zeljko Zilic
    Design for Testability of FPGA Blocks. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:86-91 [Conf]
  21. Nikos Konofaos, G. Ph. Alexiou
    New Challenges Emerging on the Design of VLSI Circuits Made of MOSFETs Using New Gate Dielectric Materials. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:92-97 [Conf]
  22. Dongku Kang, Mark C. Johnson, Kaushik Roy
    Simultaneous Multiple-Vdd Scheduling and Allocation for Partitioned Floorplan. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:98-103 [Conf]
  23. Volkan Kursun, Eby G. Friedman
    Node Voltage Dependent Subthreshold Leakage Current Characteristics of Dynamic Circuits. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:104-109 [Conf]
  24. Youngsik Kim, Shekhar Kopuri, Nazanin Mansouri
    Automated Formal Verification of Scheduling Process Using Finite State Machines with Datapath (FSMD). [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:110-115 [Conf]
  25. Eren Kursun, Soheil Ghiasi, Majid Sarrafzadeh
    Transistor Level Budgeting for Power Optimization. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:116-121 [Conf]
  26. Sunil Yu, Dusan Petranovic, Shoba Krishnan, Kwyro Lee, Cary Y. Yang
    Resistance Matrix in Crosstalk Modeling for Muliconductor Systems. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:122-125 [Conf]
  27. Bo-Sung Kim, Young-Gi Kim, Soon-Yang Hong
    Low Power 260 k Color TFT LCD One-Chip Driver IC. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:126-130 [Conf]
  28. Woo Hyung Lee, Sanjay Pant, David Blaauw
    Analysis and Reduction of On-Chip Inductance Effects in Power Supply Grids. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:131-136 [Conf]
  29. Jong-Eun Koo, Kyung-Ho Lee, Young-Hoe Cheon, Joon-Ho Choi, Moon-Hyun Yoo, Jeong-Taek Kong
    A Variable Reduction Technique for the Analysis of Ultra Large-Scale Power Distribution Networks. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:137-142 [Conf]
  30. M. Moiz Khan, Spyros Tragoudas
    Rewiring for Watermarking Digital Circuits. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:143-148 [Conf]
  31. Michael Keating
    The IP Quality Revolution. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:151-155 [Conf]
  32. Michel Côté, Philippe Hurat
    Layout Printability Optimization Using a Silicon Simulation Methodology. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:159-164 [Conf]
  33. Frank Gennari, Andrew R. Neureuther
    A Pattern Matching System for Linking TCAD and EDA. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:165-170 [Conf]
  34. John Ferguson
    Shifting Methods: Adopting a Design for Manufacture Flow. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:171-175 [Conf]
  35. Lalitha Immaneni, Anju Kapur, Brett Neal
    Design Tools for Packaging. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:179-183 [Conf]
  36. Meigen Shen, Li-Rong Zheng, Hannu Tenhunen
    Robustness Enhancement through Chip-Package Co-Design for High-Speed Electronics. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:184-189 [Conf]
  37. Roderick P. Cruz
    Flip Chip Advanced Package Solder Joint Embrittlement Fault Isolation Using TDR. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:190-195 [Conf]
  38. Janet Meiling Wang, Kishore Kumar Muchherla, Jai Ganesh Kumar
    A Clustering Based Area I/O Planning for Flip-Chip Technology. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:196-201 [Conf]
  39. Maciej Bellos, Dimitris Bakalis, Dimitris Nikolos, Xrysovalantis Kavousianos
    Low Power Testing by Test Vector Ordering with Vector Repetition. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:205-210 [Conf]
  40. Yonsang Cho, Irith Pomeranz, Sudhakar M. Reddy
    Test Application Time Reduction for Scan Circuits Using Limited Scan Operations. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:211-216 [Conf]
  41. J. Sosa, Juan A. Montiel-Nelson, Héctor Navarro, José C. García
    Functional Vector Generation for Combinational Circuits Based on Data Path Coverage Metric and Mixed Integer Linear Programming. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:217-222 [Conf]
  42. Valeriy Sukharev
    Physically-Based Simulation of Electromigration Induced Failures in Copper Dual-Damascene Interconnect. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:225-231 [Conf]
  43. Chanhee Oh, Haldun Haznedar, Martin Gall, Amir Grinshpon, Vladimir Zolotov, Pon Sun Ku, Rajendran Panda
    A Methodology for Chip-Level Electromigration Risk Assessment and Product Qualification. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:232-237 [Conf]
  44. Syed M. Alam, Chee Lip Gan, Carl V. Thompson, Donald E. Troxel
    Circuit Level Reliability Analysis of Cu Interconnects. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:238-243 [Conf]
  45. Pavel V. Nikitin, Vikram Jandhyala, Daniel White, Nathan Champagne, John D. Rockway, C.-J. Richard Shi, Chuanyi Yang, Yong Wang, Gong Ouyang, Rob Sharpe, John W. Rockway
    Modeling and Simulation of Circuit-Electromagnetic Effects in Electronic Design Flow. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:244-249 [Conf]
  46. Fangqing Yu, Weiping Shi
    A Divide-and-Conquer Algorithm for 3D Capacitance Extraction. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:253-258 [Conf]
  47. Anirban Basu, Sheng-Chih Lin, Christoph Wasshuber, Adrian M. Ionescu, Kaustav Banerjee
    A Comprehensive Analytical Capacitance Model of a Two Dimensional Nanodot Array. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:259-264 [Conf]
  48. Y. Quéré, T. LeGouguec, P. M. Martin, F. Huret
    Interconnect Mode Conversion in High-Speed VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:265-270 [Conf]
  49. Ye Liu, Mei Xue, Zheng-Fan Li, Rui-Feng Xue
    Efficient Capacitance Extraction for Periodic Structures by Shanks Transformation. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:271-275 [Conf]
  50. Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi
    PARADE: PARAmetric Delay Evaluation under Process Variation. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:276-280 [Conf]
  51. Ranjit Gharpurey, Edoardo Charbon
    Substrate Coupling: Modeling, Simulation and Design Perspectives. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:283-290 [Conf]
  52. Shahab Ardalan, Manoj Sachdev
    An Overview of Substrate Noise Reduction Techniques. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:291-296 [Conf]
  53. Meng-Fan Chang, Kuei-Ann Wen, Ding-Ming Kwai
    Supply and Substrate Noise Tolerance Using Dynamic Tracking Clusters in Configurable Memory Designs. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:297-302 [Conf]
  54. Georgios Veronis, Yi-Chang Lu, Robert W. Dutton
    Modeling of Wave Behavior of Substrate Noise Coupling for Mixed-Signal IC Design. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:303-308 [Conf]
  55. Henry H. Y. Chan, Zeljko Zilic
    Estimating Phase-Locked Loop Jitter due to Substrate Coupling: A Cyclostationary Approach. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:309-314 [Conf]
  56. Ron Wilson, Phil Dworsky
    Evening Panel Discussion: IP Industry: Nordstrom or K-Mart? The Trend Toward Tighter Relationships between Suppliers and Users. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:317-319 [Conf]
  57. Hiroto Yasuura
    Digitally Named World: Challenges for New Social Infrastructures. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:323- [Conf]
  58. Pierre G. Paulin
    Designing High Quality, Scaleable SoC??s with Heterogeneous Components. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:325- [Conf]
  59. Krishna Saraswat
    Performance Limitations of Devices and Interconnects and Possible Alternatives for Nanoelectronics. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:327- [Conf]
  60. Medha Kulkarni, Tom Chen
    A Sensitivity Based Approach to Analyzing Signal Delay Uncertainty of Coupled Interconnects. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:331-336 [Conf]
  61. Seongkyun Shin, Yungseon Eo, William R. Eisenstadt, Jongin Shim
    Analytical Dynamic Time Delay Model of Strongly Coupled RLC Interconnect Lines Dependent on Switching. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:337-342 [Conf]
  62. Cristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh
    A Scalable Communication-Centric SoC Interconnect Architecture. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:343-348 [Conf]
  63. Manidip Sengupta, Sharad Saxena, Lidia Daldoss, Glen Kramer, Sean Minehane, Jianjun Cheng
    Application Specific Worst Case Corners Using Response Surfaces and Statistical Models. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:351-356 [Conf]
  64. Ting-Yuan Wang, Charlie Chung-Ping Chen
    SPICE-Compatible Thermal Simulation with Lumped Circuit Modeling for Thermal Reliability Analysis Based on Modeling Order Reduction. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:357-362 [Conf]
  65. Janet Meiling Wang, Omar Hafiz
    Predicting Interconnect Uncertainty with a New Robust Model Order Reduction Method. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:363-368 [Conf]
  66. Sandeep Koranne
    A High Performance SIMD Framework for Design Rule Checking on Sony??s PlayStation 2 Emotion Engine Platform. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:371-376 [Conf]
  67. Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
    Exact Wiring Fault Minimization via Comprehensive Layout Synthesis for CMOS Logic Cells. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:377-380 [Conf]
  68. Rishi Chaturvedi, Jiang Hu
    Buffered Clock Tree for High Quality IC Design. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:381-386 [Conf]
  69. Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy
    Frequency Specification Testing of Analog Filters Using Wavelet Transform of Dynamic Supply Current. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:389-394 [Conf]
  70. Yongquan Fan, Zeljko Zilic, Man Wah Chiang
    A Versatile High Speed Bit Error Rate Testing Scheme. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:395-400 [Conf]
  71. Achintya Halder, Abhijit Chatterjee
    Automated Test Generation and Test Point Selection for Specification Test of Analog Circuits. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:401-406 [Conf]
  72. Man Lung Mui, Kaustav Banerjee, Amit Mehrotra
    Power Supply Optimization in sub-130 nm Leakage Dominant Technologies . [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:409-414 [Conf]
  73. Bhaskar Chatterjee, Manoj Sachdev, Ram Krishnamurthy
    Leakage Control Techniques for Designing Robust, Low Power Wide-OR Domino Logic for sub-130 nm CMOS Technologies. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:415-420 [Conf]
  74. Ge Yang, Zhongda Wang, Sung-Mo Kang
    Low Power and High Performance Circuit Techniques for High Fan-In Dynamic Gates. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:421-424 [Conf]
  75. Khushwinder Jasrotia, Jianwen Zhu
    Stacked FSMD: A Power Efficient Micro-Architecture for High Level Synthesis. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:425-430 [Conf]
  76. Ming-Dou Ker, Wei-Jen Chang, Wen-Yu Lo
    Low-Voltage-Triggered PNP Devices for ESD Protection Design in Mixed-Voltage I/O Interface with Over-VDD and Under-VSS Signal Levels. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:433-438 [Conf]
  77. Sachio Hayashi, Fumihiro Minami, Masaaki Yamada
    Full-Chip Analysis Method of ESD Protection Network. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:439-444 [Conf]
  78. Ming-Dou Ker, Wen-Yi Chen
    Design to Avoid the Over-Gate-Driven Effect on ESD Protection Circuits in Deep-Submicron CMOS Processes. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:445-450 [Conf]
  79. Justin Gregg, Tom W. Chen
    Post Silicon Power/Performance Optimization in the Presence of ProcessVariations Using Individual Well Adaptive Body Biasing (IWABB). [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:453-458 [Conf]
  80. Sobeeh Almukhaizim, Petros Drineas, Yiorgos Makris
    Concurrent Error Detection for Combinational and Sequential Logic via Output Compaction. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:459-464 [Conf]
  81. Karthik Sundararaman, Shambhu J. Upadhyaya, Martin Margala
    Cost Model Analysis of DFT Based Fault Tolerant SOC Designs. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:465-469 [Conf]
  82. Lane Albanese
    Managing Derivative SoC Design Projects to Better Results. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:470-477 [Conf]
  83. Hans-Jürgen Brand, Steffen Rülke, Martin Radetzki
    IPQ: IP Qualification for Efficient System Design. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:478-482 [Conf]
  84. Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski
    Delay Fault Diagnosis Using Timing Information. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:485-490 [Conf]
  85. Saravanan Padmanaban, Spyros Tragoudas
    An Adaptive Path Delay Fault Diagnosis Methodology. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:491-496 [Conf]
  86. Hangkyu Lee, Irith Pomeranz, Sudhakar M. Reddy
    Scan BIST Targeting Transition Faults Using a Markov Source. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:497-502 [Conf]
  87. Vijay Degalahal, R. Ramanarayanan, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin
    The Effect of Threshold Voltages on the Soft Error Rate. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:503-508 [Conf]
  88. Hari Ananthan, Aditya Bansal, Kaushik Roy
    FinFET SRAM - Device and Circuit Design Considerations. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:511-516 [Conf]
  89. Volkan Kursun, Siva Narendra, Vivek De, Eby G. Friedman
    High Input Voltage Step-Down DC-DC Converters for Integration in a Low Voltage CMOS Process. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:517-521 [Conf]
  90. Ji Luo, Joseph B. Bernstein, J. Ari Tuchman, Hu Huang, Kuan-Jung Chung, Anthony L. Wilson
    A High Performance Radiation-Hard Field Programmable Analog Array . [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:522-527 [Conf]
  91. Ahmad Yazdi, Payam Heydari
    The Design and Analysis of Non-Uniform Down-Sized Differential Distributed Amplifiers. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:528-533 [Conf]
  92. Navid Azizi, Farid N. Najm
    An Asymmetric SRAM Cell to Lower Gate Leakage. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:534-539 [Conf]
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