Conferences in DBLP
Warren Savage , John Chilton , Raul Camposano IP Reuse in the System on a Chip Era. [Citation Graph (0, 0)][DBLP ] Conf ] Vivek Sinha , Frederic Doucet , Chuck Siska , Rajesh K. Gupta , Stan Y. Liao , Abhijit Ghosh YAML: A Tool for Hardware Design Visualization and Capture. [Citation Graph (0, 0)][DBLP ] Conf ] Yung-Hsiang Lu , Giovanni De Micheli , Luca Benini Requester-Aware Power Reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Luca Benini , Giuliano Castelli , Alberto Macii , Enrico Macii , Riccardo Scarsi Battery-Driven Dynamic Power Management of Portable Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Cagdas Akturan , Margarida F. Jacome FDRA: A Software-Pipelining Algorithm for Embedded VLIW Processors. [Citation Graph (0, 0)][DBLP ] Conf ] F. Jesús Sánchez , Antonio González Instruction Scheduling for Clustered VLIW Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Natalino G. Busá , Albert van der Werf , Marco Bekooij Scheduling Coarse-Grain Operations for VLIW Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Chingren Lee , Jenq Kuen Lee , TingTing Hwang , Shi-Chun Tsai Compiler Optimization on Instruction Scheduling for Low Power. [Citation Graph (0, 0)][DBLP ] Conf ] Mateo Valero Architectures for One Billion of Transistors. [Citation Graph (0, 0)][DBLP ] Conf ] Apostolos A. Kountouris , Christophe Wolinski Hierarchical Conditional Dependency Graphs as a Unifying Design Representation in the CODESIS High-Level Synthesis System. [Citation Graph (0, 0)][DBLP ] Conf ] Olga Peñalba , José M. Mendías , María C. Molina Execution Condition Analysis in High Level Synthesis: A Unified Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Hyunuk Jung , Kangnyoung Lee , Soonhoi Ha Efficient Hardware Controller Synthesis for Synchronous Dataflow Graph in System Level Design. [Citation Graph (0, 0)][DBLP ] Conf ] Wander O. Cesário , Zoltan Sugar , Imed Moussa , Ahmed Amine Jerraya Efficient Integration of Behavioral Synthesis with Existing Design Flows. [Citation Graph (0, 0)][DBLP ] Conf ] Neal K. Bambha , Shuvra S. Bhattacharyya A Joint Power/Performance Optimization Algorithm for Multiprocessor Systems using a Period Graph Construct. [Citation Graph (0, 0)][DBLP ] Conf ] Juanjo Noguera , Rosa M. Badia Run-Time HW/SW Codesign for Discrete Event Systems using Dynamically Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Rafael Maestre , Fadi J. Kurdahi , Milagros Fernández , Nader Bagherzadeh , Hartej Singh Configuration Management in Multi-Context Reconfigurable Systems for Simultaneous Performance and Power Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Tanja Van Achteren , Rudy Lauwereins , Francky Catthoor Systematic Data Reuse Exploration Methodology for Irregular Access Patterns. [Citation Graph (0, 0)][DBLP ] Conf ] Martin Grajcar Conditional Scheduling for Embedded Systems using Genetic List Scheduling. [Citation Graph (0, 0)][DBLP ] Conf ] Fabian Wolf , Rolf Ernst Intervals in Software Execution Cost Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Marek Jersak , Ying Cai , Dirk Ziegenbein , Rolf Ernst A Transformational Approach to Constraint Relaxation of a Time-driven Simulation Model. [Citation Graph (0, 0)][DBLP ] Conf ] Matthias Meerwein , C. Baumgartner , T. Wieja , W. Glauert Embedded Systems Verification with FPGA-Enhanced In-Circuit Emulator. [Citation Graph (0, 0)][DBLP ] Conf ] Luis Alejandro Cortés , Petru Eles , Zebo Peng Verification of Embedded Systems using a Petri Net based Representation. [Citation Graph (0, 0)][DBLP ] Conf ] Annette Muth , Georg Färber SDL as a System Level Specification Language for Application-Specific Hardware in a Rapid Prototyping Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Tony Givargis , Frank Vahid , Jörg Henkel Instruction-based System-level Power Evaluation of System-On-A-Chip Peripheral Cores. [Citation Graph (0, 0)][DBLP ] Conf ] Wolfgang Rosenstiel Embedded Java. [Citation Graph (0, 0)][DBLP ] Conf ] Rainer Leupers Code Generation for Embedded Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Lars Kruse , Eike Schmidt , Gerd Jochens , Ansgar Stammermann , Wolfgang Nebel Lower Bound Estimation for Low Power High-Level Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Carlo Brandolese , William Fornaciari , Luigi Pomante , Fabio Salice , Donatella Sciuto A Multi-Level Strategy for Software Power Estimation. [Citation Graph (0, 0)][DBLP ] Conf ] Tajana Simunic , Giovanni De Micheli , Luca Benini , Mat Hans Source Code Optimization and Profiling of Energy Consumption in Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Erik Brockmeyer , Arnout Vandecappelle , Sven Wuytack , Francky Catthoor Low Power Storage Cycle Budget Distribution Tool Support for Hierarchical Graphs. [Citation Graph (0, 0)][DBLP ] Conf ] Jeffrey Kang , Albert van der Werf , Paul E. R. Lippens Mapping Array Communication onto FIFO Communication - Towards an Implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Chanik Park , Soonhoi Ha Hardware Synthesis from SPDF Representation for Multimedia Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Roman L. Lysecky , Frank Vahid , Tony Givargis Experiments with the Peripheral Virtual Component Interface. [Citation Graph (0, 0)][DBLP ] Conf ] Rafael Gadea Gironés , Joaquín Cerdá , Francisco J. Ballester , Antonio Mocholí Salcedo Artificial Neural Network Implementation on a Single FPGA of a Pipelined On-Line Backpropagation. [Citation Graph (0, 0)][DBLP ] Conf ] 