The SCEAS System
Navigation Menu

Conferences in DBLP

International Symposium on Systems Synthesis (isss)
2000 (conf/isss/2000)

  1. Warren Savage, John Chilton, Raul Camposano
    IP Reuse in the System on a Chip Era. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:2-8 [Conf]
  2. Vivek Sinha, Frederic Doucet, Chuck Siska, Rajesh K. Gupta, Stan Y. Liao, Abhijit Ghosh
    YAML: A Tool for Hardware Design Visualization and Capture. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:9-17 [Conf]
  3. Yung-Hsiang Lu, Giovanni De Micheli, Luca Benini
    Requester-Aware Power Reduction. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:18-24 [Conf]
  4. Luca Benini, Giuliano Castelli, Alberto Macii, Enrico Macii, Riccardo Scarsi
    Battery-Driven Dynamic Power Management of Portable Systems. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:25-33 [Conf]
  5. Cagdas Akturan, Margarida F. Jacome
    FDRA: A Software-Pipelining Algorithm for Embedded VLIW Processors. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:34-40 [Conf]
  6. F. Jesús Sánchez, Antonio González
    Instruction Scheduling for Clustered VLIW Architectures. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:41-46 [Conf]
  7. Natalino G. Busá, Albert van der Werf, Marco Bekooij
    Scheduling Coarse-Grain Operations for VLIW Processors. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:47-54 [Conf]
  8. Chingren Lee, Jenq Kuen Lee, TingTing Hwang, Shi-Chun Tsai
    Compiler Optimization on Instruction Scheduling for Low Power. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:55-61 [Conf]
  9. Mateo Valero
    Architectures for One Billion of Transistors. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:62- [Conf]
  10. Apostolos A. Kountouris, Christophe Wolinski
    Hierarchical Conditional Dependency Graphs as a Unifying Design Representation in the CODESIS High-Level Synthesis System. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:66-72 [Conf]
  11. Olga Peñalba, José M. Mendías, María C. Molina
    Execution Condition Analysis in High Level Synthesis: A Unified Approach. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:73-78 [Conf]
  12. Hyunuk Jung, Kangnyoung Lee, Soonhoi Ha
    Efficient Hardware Controller Synthesis for Synchronous Dataflow Graph in System Level Design. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:79-84 [Conf]
  13. Wander O. Cesário, Zoltan Sugar, Imed Moussa, Ahmed Amine Jerraya
    Efficient Integration of Behavioral Synthesis with Existing Design Flows. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:85-90 [Conf]
  14. Neal K. Bambha, Shuvra S. Bhattacharyya
    A Joint Power/Performance Optimization Algorithm for Multiprocessor Systems using a Period Graph Construct. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:91-99 [Conf]
  15. Juanjo Noguera, Rosa M. Badia
    Run-Time HW/SW Codesign for Discrete Event Systems using Dynamically Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:100-106 [Conf]
  16. Rafael Maestre, Fadi J. Kurdahi, Milagros Fernández, Nader Bagherzadeh, Hartej Singh
    Configuration Management in Multi-Context Reconfigurable Systems for Simultaneous Performance and Power Optimization. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:107-114 [Conf]
  17. Tanja Van Achteren, Rudy Lauwereins, Francky Catthoor
    Systematic Data Reuse Exploration Methodology for Irregular Access Patterns. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:115-122 [Conf]
  18. Martin Grajcar
    Conditional Scheduling for Embedded Systems using Genetic List Scheduling. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:123-129 [Conf]
  19. Fabian Wolf, Rolf Ernst
    Intervals in Software Execution Cost Analysis. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:130-136 [Conf]
  20. Marek Jersak, Ying Cai, Dirk Ziegenbein, Rolf Ernst
    A Transformational Approach to Constraint Relaxation of a Time-driven Simulation Model. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:137-142 [Conf]
  21. Matthias Meerwein, C. Baumgartner, T. Wieja, W. Glauert
    Embedded Systems Verification with FPGA-Enhanced In-Circuit Emulator. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:143-148 [Conf]
  22. Luis Alejandro Cortés, Petru Eles, Zebo Peng
    Verification of Embedded Systems using a Petri Net based Representation. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:149-156 [Conf]
  23. Annette Muth, Georg Färber
    SDL as a System Level Specification Language for Application-Specific Hardware in a Rapid Prototyping Environment. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:157-162 [Conf]
  24. Tony Givargis, Frank Vahid, Jörg Henkel
    Instruction-based System-level Power Evaluation of System-On-A-Chip Peripheral Cores. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:163-171 [Conf]
  25. Wolfgang Rosenstiel
    Embedded Java. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:172- [Conf]
  26. Rainer Leupers
    Code Generation for Embedded Processors. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:173-179 [Conf]
  27. Lars Kruse, Eike Schmidt, Gerd Jochens, Ansgar Stammermann, Wolfgang Nebel
    Lower Bound Estimation for Low Power High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:180-186 [Conf]
  28. Carlo Brandolese, William Fornaciari, Luigi Pomante, Fabio Salice, Donatella Sciuto
    A Multi-Level Strategy for Software Power Estimation. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:187-192 [Conf]
  29. Tajana Simunic, Giovanni De Micheli, Luca Benini, Mat Hans
    Source Code Optimization and Profiling of Energy Consumption in Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:193-199 [Conf]
  30. Erik Brockmeyer, Arnout Vandecappelle, Sven Wuytack, Francky Catthoor
    Low Power Storage Cycle Budget Distribution Tool Support for Hierarchical Graphs. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:200-206 [Conf]
  31. Jeffrey Kang, Albert van der Werf, Paul E. R. Lippens
    Mapping Array Communication onto FIFO Communication - Towards an Implementation. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:207-214 [Conf]
  32. Chanik Park, Soonhoi Ha
    Hardware Synthesis from SPDF Representation for Multimedia Applications. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:215-220 [Conf]
  33. Roman L. Lysecky, Frank Vahid, Tony Givargis
    Experiments with the Peripheral Virtual Component Interface. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:221-224 [Conf]
  34. Rafael Gadea Gironés, Joaquín Cerdá, Francisco J. Ballester, Antonio Mocholí Salcedo
    Artificial Neural Network Implementation on a Single FPGA of a Pipelined On-Line Backpropagation. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:225-230 [Conf]
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
System created by [] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002