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Conferences in DBLP

International Symposium on Systems Synthesis (isss)
2001 (conf/isss/2001)

  1. Om Prakash Gangwal, André Nieuwland, Paul E. R. Lippens
    A scalable and flexible data synchronization scheme for embedded HW-SW shared-memory systems. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:1-6 [Conf]
  2. Mahmut T. Kandemir, Ismail Kadayif, Ugur Sezer
    Exploiting scratch-pad memory using Presburger formulas. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:7-12 [Conf]
  3. Tycho van Meeuwen, Arnout Vandecappelle, Allert van Zelst, Francky Catthoor, Diederik Verkest
    System-level interconnect architecture exploration for custom memory organizations. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:13-18 [Conf]
  4. Samy Meftali, Ferid Gharsalli, Frédéric Rousseau, Ahmed Amine Jerraya
    An optimal memory allocation for application-specific multiprocessor system-on-chip. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:19-24 [Conf]
  5. Peter Grun, Nikil D. Dutt, Alexandru Nicolau
    APEX. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:25-32 [Conf]
  6. Luca Benini, Giovanni De Micheli
    Powering networks on chips. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:33-38 [Conf]
  7. Kaiyu Chen, Sharad Malik, David I. August
    Retargetable static timing analysis for embedded software. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:39-44 [Conf]
  8. Per Bjuréus, Axel Jantsch
    Performance analysis with confidence intervals for embedded software processes. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:45-50 [Conf]
  9. Cristiana Bolchini, Luigi Pomante, Fabio Salice, Donatella Sciuto
    On-line fault detection in a hardware/software co-design environment. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:51-56 [Conf]
  10. Gunnar Braun, Andreas Hoffmann, Achim Nohl, Heinrich Meyr
    Using static scheduling techniques for the retargeting of high speed, compiled simulators for embedded processors from an abstract machine description. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:57-62 [Conf]
  11. Haris Lekatsas, Jörg Henkel, Wayne Wolf
    Design and simulation of a pipelined decompression architecture for embedded systems. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:63-68 [Conf]
  12. Brian Bailey, Daniel Gajski
    RTL semantics and methodology. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:69-74 [Conf]
  13. Preeti Ranjan Panda
    SystemC. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:75-80 [Conf]
  14. Masahiro Fujita, Hiroshi Nakamura
    The standard SpecC language. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:81-86 [Conf]
  15. Frederic Doucet, Rajesh K. Gupta, Masato Otsuka, Patrick Schaumont, Sandeep K. Shukla
    Interoperability as a design issue in C++ based modeling environments. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:87-92 [Conf]
  16. Guang R. Gao
    Bridging the gap between ISA compilers and silicon compilers a challenge for future SoC design. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:93- [Conf]
  17. Wolfgang Rosenstiel, Brian Bailey, Masahiro Fujita, Guang R. Gao, Rajesh K. Gupta, Preeti Ranjan Panda
    New design paradigms. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:94- [Conf]
  18. Antoine Fraboulet, Karen Kodary, Anne Mignotte
    Loop fusion for memory space optimization. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:95-100 [Conf]
  19. Preeti Ranjan Panda, Luc Séméria, Giovanni De Micheli
    Cache-efficient memory layout of aggregate data structures. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:101-106 [Conf]
  20. Miguel Miranda, C. Ghez, Chidamber Kulkarni, Francky Catthoor, Diederik Verkest
    Systematic speed-power memory data-layout exploration for cache controlled embedded multimedia applications. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:107-112 [Conf]
  21. Peter Petrov, Alex Orailoglu
    Data cache energy minimizations through programmable tag size matching to the applications. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:113-117 [Conf]
  22. Marco Bekooij, Jochen A. G. Jess, Jef L. van Meerbergen
    Phase coupled operation assignment for VLIW processors with distributed register files. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:118-123 [Conf]
  23. Lama H. Chandrasena, Priyadarshana Chandrasena, Michael J. Liebelt
    An energy efficient rate selection algorithm for voltage quantized dynamic voltage scaling. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:124-129 [Conf]
  24. Radu Muresan, Catherine H. Gebotys
    Current consumption dynamics at instruction and program level for a VLIW DSP processor. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:130-135 [Conf]
  25. Giovanni Beltrame, Carlo Brandolese, William Fornaciari, Fabio Salice, Donatella Sciuto, Vito Trianni
    Dynamic modeling of inter-instruction effects for execution time estimation. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:136-141 [Conf]
  26. Ansgar Stammermann, Lars Kruse, Wolfgang Nebel, Alexander Pratsch, Eike Schmidt, Milan Schulte, Arne Schulz
    System level optimization and design space exploration for low power. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:142-146 [Conf]
  27. Kyu-won Choi, Abhijit Chatterjee
    Efficient instruction-level optimization methodology for low-power embedded systems. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:147-152 [Conf]
  28. Eui-Young Chung, Luca Benini, Giovanni De Micheli
    Source code transformation based on software cost analysis. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:153-158 [Conf]
  29. Qin Zhao, Twan Basten, Bart Mesman, C. A. J. van Eijk, Jochen A. G. Jess
    Static resource models of instruction sets. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:159-164 [Conf]
  30. Steven Derrien, Sanjay V. Rajopadhye, Susmita Sur-Kolay
    Combined instruction and loop parallelism in array synthesis for FPGAs. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:165-170 [Conf]
  31. Sumit Gupta, Nick Savoiu, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau
    Conditional speculation and its effects on performance and area for high-level snthesis. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:171-176 [Conf]
  32. Marcos Sanchez-Elez, Milagros Fernández, Román Hermida, Rafael Maestre, Fadi J. Kurdahi, Nader Bagherzadeh
    A data scheduler for multi-context reconfigurable architectures. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:177-182 [Conf]
  33. Zhong Wang, Qingfeng Zhuge, Edwin Hsing-Mean Sha
    Scheduling and partitioning for multiple loop nests. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:183-188 [Conf]
  34. Tommy Kuhn, Tobias Oppold, C. Schulz-Key, Markus Winterholer, Wolfgang Rosenstiel, Mark Edwards, Yaron Kashai
    Object oriented hardware synthesis and verification. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:189-194 [Conf]
  35. Pierre G. Paulin
    Embedded systems technologies for application-specific architecture platforms. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:195- [Conf]
  36. Richard Norman
    System design of a telecommunication router. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:196- [Conf]
  37. Feliks J. Welfeld
    Network processing in content inspection applications. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:197-201 [Conf]
  38. Ahmed Amine Jerraya, Pierre G. Paulin, Richard Norman, Feliks J. Welfeld
    Programming models for network processors (Panel). [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:202- [Conf]
  39. Chien-In Henry Chen
    Synthesis of configurable linear feedback shifter registers for detecting random-pattern-resistant faults. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:203-208 [Conf]
  40. Noureddine Chabini, Yvon Savaria
    Methods for optimizing register placement in synchronous circuits derived using software pipelining techniques. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:209-214 [Conf]
  41. Maria-Cristina V. Marinescu, Martin C. Rinard
    High-level automatic pipelining for sequential circuits. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:215-220 [Conf]
  42. Joonseok Park, Pedro C. Diniz
    Synthesis of pipelined memory access controllers for streamed data applications on FPGA-based computing engines. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:221-226 [Conf]
  43. Alessandro Fin, Franco Fummi, Giovanni Perbellini
    Soft-cores generation by instruction set analysis. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:227-232 [Conf]
  44. Hung-Pin Wen, Chien-Yu Lin, Youn-Long Lin
    Concurrent-simulation-based remote IP evaluation over the internet for system-on-a-chip design. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:233-238 [Conf]
  45. Pontus Åström, Stefan Johansson, Peter Nilsson
    Application of Software design patterns to DSP library design. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:239-243 [Conf]
  46. Ying Zhao, Sharad Malik, Matthew W. Moskewicz, Conor F. Madigan
    Accelerating boolean satisfiability through application specific processing. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:244-249 [Conf]
  47. Marcus T. Schmitz, Bashir M. Al-Hashimi
    Considering power variations of DVS processing elements for energy minimisation in distributed systems. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:250-255 [Conf]
  48. Prabhat Mishra, Nikil D. Dutt, Alexandru Nicolau
    Functional abstraction driven design space exploration of heterogeneous programmable architectures. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:256-261 [Conf]
  49. JoAnn M. Paul, Arne J. Suppé, Donald E. Thomas
    Modeling and simulation of steady state and transient behaviors for emergent SoCs. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:262-267 [Conf]
  50. Ahmed Khoumsi
    Synthesizing distributed real-time systems modeled by a timed version of a subset of LOTOS. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:268-273 [Conf]
  51. Abhijit K. Deb, Johnny Öberg, Axel Jantsch
    Control and communication performance analysis of embedded DSP systems in the MASIC methodology. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:274-273 [Conf]
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for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002