Conferences in DBLP
Om Prakash Gangwal , André Nieuwland , Paul E. R. Lippens A scalable and flexible data synchronization scheme for embedded HW-SW shared-memory systems. [Citation Graph (0, 0)][DBLP ] Conf ] Mahmut T. Kandemir , Ismail Kadayif , Ugur Sezer Exploiting scratch-pad memory using Presburger formulas. [Citation Graph (0, 0)][DBLP ] Conf ] Tycho van Meeuwen , Arnout Vandecappelle , Allert van Zelst , Francky Catthoor , Diederik Verkest System-level interconnect architecture exploration for custom memory organizations. [Citation Graph (0, 0)][DBLP ] Conf ] Samy Meftali , Ferid Gharsalli , Frédéric Rousseau , Ahmed Amine Jerraya An optimal memory allocation for application-specific multiprocessor system-on-chip. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Grun , Nikil D. Dutt , Alexandru Nicolau APEX. [Citation Graph (0, 0)][DBLP ] Conf ] Luca Benini , Giovanni De Micheli Powering networks on chips. [Citation Graph (0, 0)][DBLP ] Conf ] Kaiyu Chen , Sharad Malik , David I. August Retargetable static timing analysis for embedded software. [Citation Graph (0, 0)][DBLP ] Conf ] Per Bjuréus , Axel Jantsch Performance analysis with confidence intervals for embedded software processes. [Citation Graph (0, 0)][DBLP ] Conf ] Cristiana Bolchini , Luigi Pomante , Fabio Salice , Donatella Sciuto On-line fault detection in a hardware/software co-design environment. [Citation Graph (0, 0)][DBLP ] Conf ] Gunnar Braun , Andreas Hoffmann , Achim Nohl , Heinrich Meyr Using static scheduling techniques for the retargeting of high speed, compiled simulators for embedded processors from an abstract machine description. [Citation Graph (0, 0)][DBLP ] Conf ] Haris Lekatsas , Jörg Henkel , Wayne Wolf Design and simulation of a pipelined decompression architecture for embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Brian Bailey , Daniel Gajski RTL semantics and methodology. [Citation Graph (0, 0)][DBLP ] Conf ] Preeti Ranjan Panda SystemC. [Citation Graph (0, 0)][DBLP ] Conf ] Masahiro Fujita , Hiroshi Nakamura The standard SpecC language. [Citation Graph (0, 0)][DBLP ] Conf ] Frederic Doucet , Rajesh K. Gupta , Masato Otsuka , Patrick Schaumont , Sandeep K. Shukla Interoperability as a design issue in C++ based modeling environments. [Citation Graph (0, 0)][DBLP ] Conf ] Guang R. Gao Bridging the gap between ISA compilers and silicon compilers a challenge for future SoC design. [Citation Graph (0, 0)][DBLP ] Conf ] Wolfgang Rosenstiel , Brian Bailey , Masahiro Fujita , Guang R. Gao , Rajesh K. Gupta , Preeti Ranjan Panda New design paradigms. [Citation Graph (0, 0)][DBLP ] Conf ] Antoine Fraboulet , Karen Kodary , Anne Mignotte Loop fusion for memory space optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Preeti Ranjan Panda , Luc Séméria , Giovanni De Micheli Cache-efficient memory layout of aggregate data structures. [Citation Graph (0, 0)][DBLP ] Conf ] Miguel Miranda , C. Ghez , Chidamber Kulkarni , Francky Catthoor , Diederik Verkest Systematic speed-power memory data-layout exploration for cache controlled embedded multimedia applications. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Petrov , Alex Orailoglu Data cache energy minimizations through programmable tag size matching to the applications. [Citation Graph (0, 0)][DBLP ] Conf ] Marco Bekooij , Jochen A. G. Jess , Jef L. van Meerbergen Phase coupled operation assignment for VLIW processors with distributed register files. [Citation Graph (0, 0)][DBLP ] Conf ] Lama H. Chandrasena , Priyadarshana Chandrasena , Michael J. Liebelt An energy efficient rate selection algorithm for voltage quantized dynamic voltage scaling. [Citation Graph (0, 0)][DBLP ] Conf ] Radu Muresan , Catherine H. Gebotys Current consumption dynamics at instruction and program level for a VLIW DSP processor. [Citation Graph (0, 0)][DBLP ] Conf ] Giovanni Beltrame , Carlo Brandolese , William Fornaciari , Fabio Salice , Donatella Sciuto , Vito Trianni Dynamic modeling of inter-instruction effects for execution time estimation. [Citation Graph (0, 0)][DBLP ] Conf ] Ansgar Stammermann , Lars Kruse , Wolfgang Nebel , Alexander Pratsch , Eike Schmidt , Milan Schulte , Arne Schulz System level optimization and design space exploration for low power. [Citation Graph (0, 0)][DBLP ] Conf ] Kyu-won Choi , Abhijit Chatterjee Efficient instruction-level optimization methodology for low-power embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Eui-Young Chung , Luca Benini , Giovanni De Micheli Source code transformation based on software cost analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Qin Zhao , Twan Basten , Bart Mesman , C. A. J. van Eijk , Jochen A. G. Jess Static resource models of instruction sets. [Citation Graph (0, 0)][DBLP ] Conf ] Steven Derrien , Sanjay V. Rajopadhye , Susmita Sur-Kolay Combined instruction and loop parallelism in array synthesis for FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Sumit Gupta , Nick Savoiu , Nikil D. Dutt , Rajesh K. Gupta , Alexandru Nicolau Conditional speculation and its effects on performance and area for high-level snthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Marcos Sanchez-Elez , Milagros Fernández , Román Hermida , Rafael Maestre , Fadi J. Kurdahi , Nader Bagherzadeh A data scheduler for multi-context reconfigurable architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Zhong Wang , Qingfeng Zhuge , Edwin Hsing-Mean Sha Scheduling and partitioning for multiple loop nests. [Citation Graph (0, 0)][DBLP ] Conf ] Tommy Kuhn , Tobias Oppold , C. Schulz-Key , Markus Winterholer , Wolfgang Rosenstiel , Mark Edwards , Yaron Kashai Object oriented hardware synthesis and verification. [Citation Graph (0, 0)][DBLP ] Conf ] Pierre G. Paulin Embedded systems technologies for application-specific architecture platforms. [Citation Graph (0, 0)][DBLP ] Conf ] Richard Norman System design of a telecommunication router. [Citation Graph (0, 0)][DBLP ] Conf ] Feliks J. Welfeld Network processing in content inspection applications. [Citation Graph (0, 0)][DBLP ] Conf ] Ahmed Amine Jerraya , Pierre G. Paulin , Richard Norman , Feliks J. Welfeld Programming models for network processors (Panel). [Citation Graph (0, 0)][DBLP ] Conf ] Chien-In Henry Chen Synthesis of configurable linear feedback shifter registers for detecting random-pattern-resistant faults. [Citation Graph (0, 0)][DBLP ] Conf ] Noureddine Chabini , Yvon Savaria Methods for optimizing register placement in synchronous circuits derived using software pipelining techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Maria-Cristina V. Marinescu , Martin C. Rinard High-level automatic pipelining for sequential circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Joonseok Park , Pedro C. Diniz Synthesis of pipelined memory access controllers for streamed data applications on FPGA-based computing engines. [Citation Graph (0, 0)][DBLP ] Conf ] Alessandro Fin , Franco Fummi , Giovanni Perbellini Soft-cores generation by instruction set analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Hung-Pin Wen , Chien-Yu Lin , Youn-Long Lin Concurrent-simulation-based remote IP evaluation over the internet for system-on-a-chip design. [Citation Graph (0, 0)][DBLP ] Conf ] Pontus Åström , Stefan Johansson , Peter Nilsson Application of Software design patterns to DSP library design. [Citation Graph (0, 0)][DBLP ] Conf ] Ying Zhao , Sharad Malik , Matthew W. Moskewicz , Conor F. Madigan Accelerating boolean satisfiability through application specific processing. [Citation Graph (0, 0)][DBLP ] Conf ] Marcus T. Schmitz , Bashir M. Al-Hashimi Considering power variations of DVS processing elements for energy minimisation in distributed systems. [Citation Graph (0, 0)][DBLP ] Conf ] Prabhat Mishra , Nikil D. Dutt , Alexandru Nicolau Functional abstraction driven design space exploration of heterogeneous programmable architectures. [Citation Graph (0, 0)][DBLP ] Conf ] JoAnn M. Paul , Arne J. Suppé , Donald E. Thomas Modeling and simulation of steady state and transient behaviors for emergent SoCs. [Citation Graph (0, 0)][DBLP ] Conf ] Ahmed Khoumsi Synthesizing distributed real-time systems modeled by a timed version of a subset of LOTOS. [Citation Graph (0, 0)][DBLP ] Conf ] Abhijit K. Deb , Johnny Öberg , Axel Jantsch Control and communication performance analysis of embedded DSP systems in the MASIC methodology. [Citation Graph (0, 0)][DBLP ] Conf ] 