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Conferences in DBLP
- Eric Foster
Design of a Set-Top Box System on a Chip. [Citation Graph (0, 0)][DBLP]
ISSS, 1999, pp:2- [Conf]
- Brian Kelley
On the Rapid Prototyping and Design of a Wireless Communication System on a Chip. [Citation Graph (0, 0)][DBLP]
ISSS, 1999, pp:3- [Conf]
- Brian M. Barry, John Duimovich
Embedded Java: Techniques and Applications. [Citation Graph (0, 0)][DBLP]
ISSS, 1999, pp:6-7 [Conf]
- Daniel Gajski, Reinaldo A. Bergamaschi
Panel Statement. [Citation Graph (0, 0)][DBLP]
ISSS, 1999, pp:8-9 [Conf]
- Nadim Maluf
Micro-Electromechanical Systems (MEMS): Miniaturization Beyond Microelectronics. [Citation Graph (0, 0)][DBLP]
ISSS, 1999, pp:10-11 [Conf]
- Douglas C. Schmidt
Middleware Techniques and Optimizations for Real-Time, Embedded Systems. [Citation Graph (0, 0)][DBLP]
ISSS, 1999, pp:12-17 [Conf]
- Tajana Simunic, Giovanni De Micheli, Luca Benini
Event-Driven Power Management of Portable Systems. [Citation Graph (0, 0)][DBLP]
ISSS, 1999, pp:18-23 [Conf]
- Takanori Okuma, Tohru Ishihara, Hiroto Yasuura
Real-Time Task Scheduling for a Variable Voltage Processor. [Citation Graph (0, 0)][DBLP]
ISSS, 1999, pp:24-29 [Conf]
- Vincent John Mooney III
Path-based Edge Activation for Dynamic Run-Time Scheduling. [Citation Graph (0, 0)][DBLP]
ISSS, 1999, pp:30-37 [Conf]
- Jens Horstmannshoff, Heinrich Meyr
Optimized System Synthesis of Complex RT Level Building Blocks from Multirate Dataflow Graphs. [Citation Graph (0, 0)][DBLP]
ISSS, 1999, pp:38-43 [Conf]
- Peter Grun, Ashok Halambi, Nikil D. Dutt, Alexandru Nicolau
RTGEN: An Algorithm for Automatic Generation of Reservation Tables from Architectural Descriptions. [Citation Graph (0, 0)][DBLP]
ISSS, 1999, pp:44-50 [Conf]
- Roman L. Lysecky, Frank Vahid, Rilesh Patel, Tony Givargis
Pre-Fetching for Improved Core Interfacing. [Citation Graph (0, 0)][DBLP]
ISSS, 1999, pp:51-55 [Conf]
- Paulo Centoducatte, Ricardo Pannain, Guido Araujo
Compressed Code Execution on DSP Architectures. [Citation Graph (0, 0)][DBLP]
ISSS, 1999, pp:56-63 [Conf]
- Fei Chen, Edwin Hsing-Mean Sha
Loop Scheduling and Partitions for Hiding Memory Latencies. [Citation Graph (0, 0)][DBLP]
ISSS, 1999, pp:64-70 [Conf]
- Antoine Fraboulet, Guillaume Huard, Anne Mignotte
Loop Alignment for Memory Accesses Optimization. [Citation Graph (0, 0)][DBLP]
ISSS, 1999, pp:71-77 [Conf]
- Praveen K. Murthy, Shuvra S. Bhattacharyya
A Buffer Merging Technique for Reducing Memory Requirements of Synchronous Dataflow Specifications. [Citation Graph (0, 0)][DBLP]
ISSS, 1999, pp:78-84 [Conf]
- Chantal Ykman-Couvreur, J. Lambrecht, Diederik Verkest, Francky Catthoor, Hugo De Man
Exploration and Synthesis of Dynamic Data Sets in Telecom Network Applications. [Citation Graph (0, 0)][DBLP]
ISSS, 1999, pp:85-93 [Conf]
- Khurram Muhammad, Kaushik Roy
A Graph Theoretic Approach for Design and Synthesis of Multiplierless FIR Filters. [Citation Graph (0, 0)][DBLP]
ISSS, 1999, pp:94-99 [Conf]
- Bart Mesman, Carlos A. Alba Pinto, Koen van Eijk
Efficient Scheduling of DSP Code on Processors with Distributed Register Files. [Citation Graph (0, 0)][DBLP]
ISSS, 1999, pp:100-106 [Conf]
- Shail Aditya, B. Ramakrishna Rau, Vinod Kathail
Automatic Architectural Synthesis of VLIW and EPIC Processors. [Citation Graph (0, 0)][DBLP]
ISSS, 1999, pp:107-113 [Conf]
- Carlos Carreras, Juan A. López, Octavio Nieto-Taladriz
Bit-Width Selection for Data-Path Implementations. [Citation Graph (0, 0)][DBLP]
ISSS, 1999, pp:114-121 [Conf]
- W. De Rammelaere, K. Eckert, T. Lawell, R. McGarity, F. Steininger, P. Le Moenner, E. Hilkens
Catalyst: A DSIP Design Flow Development in Industry. [Citation Graph (0, 0)][DBLP]
ISSS, 1999, pp:122-127 [Conf]
- Gang Qu, Malena R. Mesarina, Miodrag Potkonjak
System Synthesis of Synchronous Multimedia Applications. [Citation Graph (0, 0)][DBLP]
ISSS, 1999, pp:128-133 [Conf]
- Rafael Maestre, Milagros Fernández, Román Hermida, Nader Bagherzadeh
A Framework for Scheduling and Context Allocation in Reconfigurable Computing. [Citation Graph (0, 0)][DBLP]
ISSS, 1999, pp:134-140 [Conf]
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