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Conferences in DBLP

International Symposium on Systems Synthesis (isss)
2002 (conf/isss/2002)

  1. M. Balakrishnan, Anshul Kumar, Paolo Ienne, Anup Gangwar, Bhuvan Middha
    A Trimaran Based Framework for Exploring the Design Space of VLIW ASIPs with Coarse Grain Functional Units. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:2-7 [Conf]
  2. Frank Vahid, Susan Cotterell
    Tuning of Loop Cache Architectures to Programs in Embedded System Design. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:8-13 [Conf]
  3. Nader Bagherzadeh, Pai H. Chou, Jinfeng Liu
    Combined Functional Partitioning and Communication Speed Selection for Networked Voltage-Scalable Processors. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:14-19 [Conf]
  4. Daniel Gajski, Junyu Peng
    Optimal Message-Passing for Data Coherency in Distributed Architecture. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:20-25 [Conf]
  5. Ahmed Amine Jerraya, Damien Lyonnard, Samy Meftali, Frédéric Rousseau, Ferid Gharsalli
    Unifying Memory and Processor Wrapper Architecture in Multiprocessor SoC Design. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:26-31 [Conf]
  6. Hiroto Yasuura, Yun Cao, Mohammad Mesbah Uddin
    An Accelerated Datapath Width Optimization Scheme for Area Reduction of Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:32-37 [Conf]
  7. Guido Araujo, Sharad Malik, Zhining Huang, Nahri Moreano
    Datapath Merging and Interconnection Sharing for Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:38-43 [Conf]
  8. Carles Rodoreda Sala, Natalino G. Busá
    A Run-Time Word-Level Reconfigurable Coarse-Grain Functional Unit for a VLIW Processor. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:44-49 [Conf]
  9. Sanjay V. Rajopadhye, Steven Derrien
    Energy/Power Estimation of Regular Processor Arrays. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:50-55 [Conf]
  10. Oliver Bringmann, Wolfgang Rosenstiel, Carsten Menn
    Controller Estimation for FPGA Target Architectures during High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:56-61 [Conf]
  11. Andrew S. Cassidy, Christopher P. Andrews, Donald E. Thomas, JoAnn M. Paul
    System-Level Modeling of a Network Switch SoC. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:62-67 [Conf]
  12. Erwin A. de Kock
    Multiprocessor Mapping of Process Networks: A JPEG Decoding Case Study. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:68-73 [Conf]
  13. Takao Onoye, Yukihiro Nakamura, Atsuhito Shigiya, Keishi Chikamura, Kosuke Tsujino, Tomonori Izumi, Hirofumi Yamamoto
    System-Level Design of IEEE1394 Bus Segment Bridge. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:74-79 [Conf]
  14. Catherine H. Gebotys
    Security-Driven Exploration of Cryptography in DSP Cores. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:80-85 [Conf]
  15. Ingo Sander, Axel Jantsch, Zhonghai Lu
    A Case Study of Hardware and Software Synthesis in ForSyDe. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:86-91 [Conf]
  16. Paolo Ienne, Patrick Thiran, Giovanni De Micheli, Frederic Worm
    An Adaptive Low-Power Transmission Scheme for On-Chip Networks. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:92-100 [Conf]
  17. Shuichi Sakai
    CMP on SoC: Architect's View. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:101-102 [Conf]
  18. Satoshi Matsushita
    Design Experience of a Chip Multiprocessor Merlot and Expectation to Functional Verification. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:103-108 [Conf]
  19. Mitsuhisa Sato
    OpenMP: Parallel Programming API for Shared Memory Multiprocessors and On-Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:109-111 [Conf]
  20. Rudy Lauwereins, Chun Wong, Paul Marchal, Johan Vounckx, Patrick David, Stefaan Himpe, Francky Catthoor, Peng Yang
    Managing Dynamic Concurrent Tasks in Embedded Real-Time Multimedia Systems. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:112-119 [Conf]
  21. Alexandru Nicolau, Nikil D. Dutt, Aviral Shrivastava, Partha Biswas, Ashok Halambi
    A Design Space Exploration Framework for Reduced Bit-Width Instruction Set Architecture (rISA) Design . [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:120-125 [Conf]
  22. Abhik Roychoudhury, Xianfeng Li, Tulika Mitra
    Timing Analysis of Embedded Software for Speculative Processors. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:126-131 [Conf]
  23. William Fornaciari, Vito Trianni, Carlo Brandolese, Donatella Sciuto, Fabio Salice, Giovanni Beltrame
    Modeling Assembly Instruction Timing in Superscalar Architectures. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:132-137 [Conf]
  24. Haris Lekatsas, Wayne Wolf, Yuan Xie
    Code Compression for VLIW Processors Using Variable-to-Fixed Coding. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:138-143 [Conf]
  25. Bin Xiao, Zili Shao, Chantana Chantrapornchai, Edwin Hsing-Mean Sha, Qingfeng Zhuge
    Optimal Code Size Reduction for Software-Pipelined and Unfolded Loops. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:144-149 [Conf]
  26. Rainer Dömer, Andreas Gerstlauer, Wolfgang Mueller
    The Formal Execution Semantics of SpecC. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:150-155 [Conf]
  27. Petru Eles, Zebo Peng, Daniel Karlsson
    Formal Verification in a Component-Based Reuse Methodology. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:156-161 [Conf]
  28. Ahmed Amine Jerraya, Sungjoo Yoo, Aimen Bouchhima, Gabriela Nicolescu
    Validation in a Component-Based Design Flow for Multicore SoCs. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:162-167 [Conf]
  29. Rajesh K. Gupta, Sandeep K. Shukla, Nick Savoiu
    Efficient Simulation of Synthesis-Oriented System Level Designs. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:168-173 [Conf]
  30. Soonhoi Ha, Sungchan Kim, Chan-Eun Rhee, Hyunguk Jung, Youngmin Yi, Dohyung Kim
    Virtual Synchronization for Fast Distributed Cosimulation of Dataflow Task Graphs. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:174-179 [Conf]
  31. M. Balakrishnan, Anshul Kumar, C. P. Joshi
    A New Performance Evaluation Approach for System Level Design Space Exploration. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:180-185 [Conf]
  32. Jürgen Ruf, Thomas Kropf, Jochen Klose
    A Visual Approach to Validating System Level Designs. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:186-191 [Conf]
  33. Hiroto Yasuura, Naofumi Takagi, Srivaths Ravi, Michael Torla, Catherine H. Gebotys
    Special Session: Security on SoC. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:192-194 [Conf]
  34. Anand Raghunathan, Nachiketh R. Potlapally, Srivaths Ravi
    Securing Wireless Data: System Architecture Challenges. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:195-200 [Conf]
  35. Hiroto Yasuura, Hiroyuki Tomiyama, Takanori Okuma, Yun Cao
    Data Memory Design Considering Effective Bitwidth for Low-Energy Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:201-206 [Conf]
  36. Nikil D. Dutt, Daniel S. Hirschberg, Mahesh Mamidipaka
    Efficient Power Reduction Techniques for Time Multiplexed Address Buses. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:207-212 [Conf]
  37. M. Balakrishnan, Peter Marwedel, Lars Wehmeyer, Nils Grunwald, Rajeshwari Banakar, Stefan Steinke
    Reducing Energy Consumption by Dynamic Copying of Instructions onto Onchip Memory. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:213-218 [Conf]
  38. Alex Orailoglu, Peter Petrov
    Low-Power Data Memory Communication for Application-Specific Embedded Processors. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:219-224 [Conf]
  39. Abhijit Chatterjee, Peeter Ellervee, Vincent John Mooney III, Jun-Cheol Park, Kyu-won Choi, Kiran Puttaswamy
    System Level Power-Performance Trade-Offs in Embedded Systems Using Voltage and Frequency Scaling of Off-Chip Buses and Memory. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:225-230 [Conf]
  40. Daniel Gajski, Andreas Gerstlauer
    System-Level Abstraction Semantics. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:231-236 [Conf]
  41. Luciano Lavagno, Mihai T. Lazarescu, Stefano Quer, Sergio Nocco, Claudio Passerone, Gianpiero Cabodi
    A Symbolic Approach for the Combined Solution of Scheduling and Allocation. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:237-242 [Conf]
  42. Vincent John Mooney III, George F. Riley, Eung S. Shin
    Round-Robin Arbiter Design and Generation. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:243-248 [Conf]
  43. Tsuneo Nakata, Akio Matsuda, Minoru Shoji, Shinya Kuwamura, Qiang Zhu
    An Object-Oriented Design Process for System-on-Chip Using UML. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:249-254 [Conf]
  44. Juan Carlos López, Fernando Rincón, Francisco Moya, José Manuel Moya
    Improving Embedded System Design by Means of HW-SW Compilation on Reconfigurable Coprocessors. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:255-260 [Conf]
  45. Alexandru Nicolau, Nikil D. Dutt, Rajesh Gupta, Nick Savoiu, Mehrdad Reshadi, Sumit Gupta
    Dynamic Common Sub-Expression Elimination during Scheduling in High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:261-266 [Conf]
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for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002