The SCEAS System
Navigation Menu

Conferences in DBLP

International Symposium on Systems Synthesis (isss)
1996 (conf/isss/1996)

  1. Chunho Lee, Miodrag Potkonjak, Wayne Wolf
    System-Level Synthesis of Application Specific Systems using A* Search and Generalized Force-Directed Heuristics. [Citation Graph (0, 0)][DBLP]
    ISSS, 1996, pp:2-7 [Conf]
  2. Stephen A. Blythe, Robert A. Walker
    Toward a Practical Methodology for Completely Characterizing the Optimal Design Space. [Citation Graph (0, 0)][DBLP]
    ISSS, 1996, pp:8-13 [Conf]
  3. Johnny Öberg, Anshul Kumar, Ahmed Hemani
    Grammar-Based Hardware Synthesis of Data Communication Protocols. [Citation Graph (0, 0)][DBLP]
    ISSS, 1996, pp:14-19 [Conf]
  4. Miguel Miranda, Francky Catthoor, Martin Janssen, Hugo De Man
    ADOPT: Efficient Hardware Address Generation in Distributed Memory Architectures. [Citation Graph (0, 0)][DBLP]
    ISSS, 1996, pp:20-25 [Conf]
  5. Gernot Koch, Udo Kebschull, Wolfgang Rosenstiel
    Breakpoints and Breakpoint Detection in Source Level Emulation. [Citation Graph (0, 0)][DBLP]
    ISSS, 1996, pp:26-0 [Conf]
  6. Min Xu, Fadi J. Kurdahi
    Layout-Driven RTL Binding Techniques for High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    ISSS, 1996, pp:33-38 [Conf]
  7. Alan Su 0002, Ta-Yung Liu, Yu-Chin Hsu, Mike Tien-Chien Lee
    Eliminating False Loops Caused by Sharing in Control Path. [Citation Graph (0, 0)][DBLP]
    ISSS, 1996, pp:39-44 [Conf]
  8. Michael Münch, Manfred Glesner, Norbert Wehn
    An Efficient ILP-Based Scheduling Algorithm for Control-Dominated VHDL Descriptions. [Citation Graph (0, 0)][DBLP]
    ISSS, 1996, pp:45-50 [Conf]
  9. Luiz C. V. dos Santos, Marc J. M. Heijligers, C. A. J. van Eijk, Jos T. J. van Eijndhoven, Jochen A. G. Jess
    A Constructive Method for Exploiting Code Motion. [Citation Graph (0, 0)][DBLP]
    ISSS, 1996, pp:51-56 [Conf]
  10. Luca Benini, Patrick Vuillod, Claudionor José Nunes Coelho Jr., Giovanni De Micheli
    Synthesis of Low-Power Selectively-Clocked Systems from High-Level Specification. [Citation Graph (0, 0)][DBLP]
    ISSS, 1996, pp:57-0 [Conf]
  11. Michael Gasteier, Manfred Glesner
    Bus-Based Communication Synthesis on System-Level. [Citation Graph (0, 0)][DBLP]
    ISSS, 1996, pp:65-70 [Conf]
  12. Petru Eles, Zebo Peng, Krzysztof Kuchcinski, Alex Doboli
    Hardware/Software Partitioning with Iterative Improvement Heuristics. [Citation Graph (0, 0)][DBLP]
    ISSS, 1996, pp:71-76 [Conf]
  13. Alessandro Balboni, William Fornaciari, M. Vincenzi, Donatella Sciuto
    The Use of a Virtual Instruction Set for the Software Synthesis of HW/SW Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ISSS, 1996, pp:77-82 [Conf]
  14. Laurent Freund, Michel Israël, Frédéric Rousseau, J. M. Bergé, Michel Auguin, Cécile Belleudy, Guy Gogniat
    A Codesign Experiment in Acoustic Echo Cancellation: GMDFa. [Citation Graph (0, 0)][DBLP]
    ISSS, 1996, pp:83-0 [Conf]
  15. Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau
    Memory Organization for Improved Data Cache Performance in Embedded Processors. [Citation Graph (0, 0)][DBLP]
    ISSS, 1996, pp:90-95 [Conf]
  16. Hiroyuki Tomiyama, Hiroto Yasuura
    Size-Constrained Code Placement for Cache Miss Rate Reduction. [Citation Graph (0, 0)][DBLP]
    ISSS, 1996, pp:96-104 [Conf]
  17. Guido Araujo, Ashok Sudarsanam, Sharad Malik
    Instruction Set Design and Optimizations for Address Computation in DSP Architectures. [Citation Graph (0, 0)][DBLP]
    ISSS, 1996, pp:102-107 [Conf]
  18. Vojin Zivojnovic, Stefan Pees, C. Schälger, Markus Willems, R. Schoenen, Heinrich Meyr
    DSP Processor/Compiler Co-Design: A Quantitative Approach. [Citation Graph (0, 0)][DBLP]
    ISSS, 1996, pp:108-0 [Conf]
  19. James E. Beck, Daniel P. Siewiorek
    Modeling Multicomputer Task Allocation as a Vector Packing Problem. [Citation Graph (0, 0)][DBLP]
    ISSS, 1996, pp:115-120 [Conf]
  20. Frank Vahid, Thuy Dm Le, Yu-Chin Hsu
    A Comparison of Functional and Structural Partitioning. [Citation Graph (0, 0)][DBLP]
    ISSS, 1996, pp:121-126 [Conf]
  21. Sven Wuytack, Francky Catthoor, Gjalt G. de Jong, Bill Lin, Hugo De Man
    Flow Graph Balancing for Minimizing the Required Memory Bandwidth. [Citation Graph (0, 0)][DBLP]
    ISSS, 1996, pp:127-132 [Conf]
  22. Stephen Docy, Inki Hong, Miodrag Potkonjak
    Throughput Optimization in Disk-Based Real-Time Application Specific Systems. [Citation Graph (0, 0)][DBLP]
    ISSS, 1996, pp:133-138 [Conf]
  23. Frank F. Hsu, Elizabeth M. Rudnick, Janak H. Patel
    Testability Insertion in Behavioral Descriptions. [Citation Graph (0, 0)][DBLP]
    ISSS, 1996, pp:139-144 [Conf]
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
System created by [] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002