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Conferences in DBLP

International Symposium on Systems Synthesis (isss)
1998 (conf/isss/1998)

  1. Rainer Leupers, Fabian David
    A Uniform Optimization Technique for Offset Assignment Problems. [Citation Graph (0, 0)][DBLP]
    ISSS, 1998, pp:3-8 [Conf]
  2. Luc De Coster, Marleen Adé, Rudy Lauwereins, J. A. Peperstraete
    Code Generation for Compiled Bit-True Simulation of DSP Applications. [Citation Graph (0, 0)][DBLP]
    ISSS, 1998, pp:9-14 [Conf]
  3. Wei-Kai Cheng, Youn-Long Lin
    Addressing Optimization for Loop Execution Targeting DSP with Auto-Increment/Decrement Architecture. [Citation Graph (0, 0)][DBLP]
    ISSS, 1998, pp:15-22 [Conf]
  4. Doris Keitel-Schulz, Norbert Wehn
    Issues in Embedded DRAM Development and Applications. [Citation Graph (0, 0)][DBLP]
    ISSS, 1998, pp:23-30 [Conf]
  5. Chuck Siska
    A Processor Description Language Supporting Retargetable Multi-Pipeline DSP Program Development Tools. [Citation Graph (0, 0)][DBLP]
    ISSS, 1998, pp:31-36 [Conf]
  6. Enrica Filippi, Luciano Lavagno, L. Licciardi, A. Montanaro, M. Paolini, Roberto Passerone, Marco Sgroi, Alberto L. Sangiovanni-Vincentelli
    Intellectual Property Re-use in Embedded System Co-design: An Industrial Case Study. [Citation Graph (0, 0)][DBLP]
    ISSS, 1998, pp:37-42 [Conf]
  7. Frank Vahid, Tony Givargis
    Incorporating Cores into System-Level Specification. [Citation Graph (0, 0)][DBLP]
    ISSS, 1998, pp:43-50 [Conf]
  8. Rainer Leupers
    HDL-Based Modeling of Embedded Processor Behavior for Retargetable Compilation. [Citation Graph (0, 0)][DBLP]
    ISSS, 1998, pp:51-0 [Conf]
  9. Apostolos A. Kountouris, Christophe Wolinski
    False Path Analysis Based on a Hierarchical Control Representation. [Citation Graph (0, 0)][DBLP]
    ISSS, 1998, pp:55-59 [Conf]
  10. Christoph Jäschke, Rainer Laur
    Resource Constrained Modulo Scheduling with Global Resource Sharing. [Citation Graph (0, 0)][DBLP]
    ISSS, 1998, pp:60-65 [Conf]
  11. Hiroyuki Tomiyama, Akihiko Inoue, Hiroto Yasuura
    Statistical Performance-Driven Module Binding in High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    ISSS, 1998, pp:66-71 [Conf]
  12. Cristiana Bolchini, William Fornaciari, Fabio Salice, Donatella Sciuto
    Concurrent Error Detection at Architectural Level. [Citation Graph (0, 0)][DBLP]
    ISSS, 1998, pp:72-75 [Conf]
  13. Yin-Tsung Hwang, Yuan-Hung Wang
    Communication and Interface Synthesis on a Rapid Prototyping Hardware/Software Codesign System. [Citation Graph (0, 0)][DBLP]
    ISSS, 1998, pp:76-82 [Conf]
  14. Allan Rae, Sri Parameswaran
    Application-Specific Heterogeneous Multiprocessor Synthesis Using Differential-Evolution. [Citation Graph (0, 0)][DBLP]
    ISSS, 1998, pp:83-88 [Conf]
  15. Francky Catthoor, Diederik Verkest, Erik Brockmeyer
    Proposal for Unified System Design Meta Flow in Task-Level and Instruction-Level Design Technology Research for Multi-Media Applications. [Citation Graph (0, 0)][DBLP]
    ISSS, 1998, pp:89-95 [Conf]
  16. Zhao Wu, Wayne Wolf
    Data-Path Synthesis of VLIW Video Signal Processors. [Citation Graph (0, 0)][DBLP]
    ISSS, 1998, pp:96-104 [Conf]
  17. Oliver Bringmann, Wolfgang Rosenstiel, Dirk Reichardt
    Synchronization Detection for Multi-Process Hierarchical Synthesis. [Citation Graph (0, 0)][DBLP]
    ISSS, 1998, pp:105-110 [Conf]
  18. Peter Voigt Knudsen, Jan Madsen
    Integrating Communication Protocol Selection with Partitioning in Hardware/Software Codesign. [Citation Graph (0, 0)][DBLP]
    ISSS, 1998, pp:111-116 [Conf]
  19. Tony Givargis, Frank Vahid
    Interface Exploration for Reduced Power in Core-Based Systems. [Citation Graph (0, 0)][DBLP]
    ISSS, 1998, pp:117-124 [Conf]
  20. Takanori Okuma, Hiroyuki Tomiyama, Akihiko Inoue, Eko Fajar, Hiroto Yasuura
    Instruction Encoding Techniques for Area Minimization of Instruction ROM. [Citation Graph (0, 0)][DBLP]
    ISSS, 1998, pp:125-130 [Conf]
  21. Ing-Jer Huang, Ping-Huei Xie
    Application of Instruction Analysis/Synthesis Tools to x86's Functional Unit Allocation. [Citation Graph (0, 0)][DBLP]
    ISSS, 1998, pp:131-136 [Conf]
  22. Wonyong Sung, Junedong Kim, Soonhoi Ha
    Memory Efficient Software Synthesis from Dataflow Graph. [Citation Graph (0, 0)][DBLP]
    ISSS, 1998, pp:137-144 [Conf]
  23. Karam S. Chatha, Ranga Vemuri
    A Tool for Partitioning and Pipelined Scheduling of Hardware-Software Systems. [Citation Graph (0, 0)][DBLP]
    ISSS, 1998, pp:145-151 [Conf]
  24. Frank Vahid
    A Three-Step Approach to the Functional Partitioning of Large Behavioral Processes. [Citation Graph (0, 0)][DBLP]
    ISSS, 1998, pp:152-157 [Conf]
  25. Soha Hassoun
    Fine Grain Incremental Rescheduling Via Architectural Retiming. [Citation Graph (0, 0)][DBLP]
    ISSS, 1998, pp:158-163 [Conf]
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