Conferences in DBLP
Ti-Yen Yen , Wayne Wolf Sensitivity-driven co-synthesis of distributed embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Jay K. Adams , Donald E. Thomas Multiple-process behavioral synthesis for mixed hardware-software systems. [Citation Graph (0, 0)][DBLP ] Conf ] Jan Madsen , Bjarne Hald An approach to interface synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Pai H. Chou , Ross B. Ortega , Gaetano Borriello The Chinook hardware/software co-synthesis system. [Citation Graph (0, 0)][DBLP ] Conf ] Frank Vahid , Daniel D. Gajski Clustering for improved system-level functional partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Guido Araujo , Sharad Malik Optimal code generation for embedded memory non-homogeneous register architectures. [Citation Graph (0, 0)][DBLP ] Conf ] David J. Kolson , Alexandru Nicolau , Nikil Dutt , Ken Kennedy Optimal register assignment to loops for embedded code generation. [Citation Graph (0, 0)][DBLP ] Conf ] Filip Thoen , Marco Cornero , Gert Goossens , Hugo De Man Real-time multi-tasking in software synthesis for information processing systems. [Citation Graph (0, 0)][DBLP ] Conf ] Rainer Leupers , Peter Marwedel Time-constrained code compaction for DSPs. [Citation Graph (0, 0)][DBLP ] Conf ] Clifford Liem , Pierre G. Paulin , Marco Cornero , Ahmed Amine Jerraya Industrial experience using rule-driven retargetable code generation for multimedia applications. [Citation Graph (0, 0)][DBLP ] Conf ] Joseph Sifakis Real-time systems specification and verification. [Citation Graph (0, 0)][DBLP ] Conf ] Patrick Schaumont , Bart Vanthournout , Ivo Bolsens , Hugo De Man Synthesis of pipelined DSP accelerators with dynamic scheduling. [Citation Graph (0, 0)][DBLP ] Conf ] Samit Chaudhuri , Stephen A. Blythe , Robert A. Walker An exact methodology for scheduling in a 3D design space. [Citation Graph (0, 0)][DBLP ] Conf ] Frank Vahid Procedure exlining: a transformation for improved system and behavioral synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Herman Schmit , Donald E. Thomas Array mapping in behavioral synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Mark Genoe , Paul Vanoostende , Geert van Wauwe On the use of VHDL-based behavioral synthesis for telecom ASIC design. [Citation Graph (0, 0)][DBLP ] Conf ] Enric Musoll , Jordi Cortadella Scheduling and resource binding for low power. [Citation Graph (0, 0)][DBLP ] Conf ] Mike Tien-Chien Lee , Vivek Tiwari , Sharad Malik , Masahiro Fujita Power analysis and low-power scheduling techniques for embedded DSP software. [Citation Graph (0, 0)][DBLP ] Conf ] Jörg Henkel , Rolf Ernst A path-based technique for estimating hardware runtime in HW/SW-cosynthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Seong Yong Ohm , Fadi J. Kurdahi , Nikil Dutt , Min Xu A comprehensive estimation technique for high-level synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Matthew F. Parkinson , Sri Parameswaran Profiling in the ASP codesign environment. [Citation Graph (0, 0)][DBLP ] Conf ] Paul-Gerhard Plöger , Jörg Wilberg , Michel Langevin , Raul Camposano WWW based structuring of codesigns. [Citation Graph (0, 0)][DBLP ] Conf ] H. Samsom , Frank H. M. Franssen , Francky Catthoor , Hugo De Man System level verification of video and image processing specifications. [Citation Graph (0, 0)][DBLP ] Conf ] Jean-Marc Daveau , Tarek Ben Ismail , Ahmed Amine Jerraya Synthesis of system-level communication by an allocation-based approach. [Citation Graph (0, 0)][DBLP ] Conf ] Jürgen Teich , Lothar Thiele , Edward A. Lee Modeling and simulation of heterogeneous real-time systems based on a deterministic discrete event model. [Citation Graph (0, 0)][DBLP ] Conf ] M. Schwiegershausen , Peter Pirsch A system level design methodology for the optimization of heterogeneous multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Preeti Ranjan Panda , Nikil D. Dutt 1995 high level synthesis design repository. [Citation Graph (0, 0)][DBLP ] Conf ] 