Conferences in DBLP
Michael T. Niemier , Peter M. Kogge The "4-Diamond Circuit" - A Minimally Complex Nano-Scale Computational Building Block in QCA. [Citation Graph (0, 0)][DBLP ] Conf ] Benjamin Gojman , Eric Rachlin , John E. Savage Decoding of Stochastically Assembled Nanoarrays. [Citation Graph (0, 0)][DBLP ] Conf ] A. J. KleinOsowski , David J. Lilja The NanoBox Project: Exploring Fabrics of Self-Correcting Logic Blocks for High Defect Rate Molecular Device Technologies. [Citation Graph (0, 0)][DBLP ] Conf ] Debayan Bhaduri , Sandeep K. Shukla NANOLAB: A Tool for Evaluating Reliability of Defect-Tolerant Nano Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Lun Li , Mitchell A. Thornton , Stephen A. Szygenda A Genetic Approach for Conjunction Scheduling in Symbolic Equivalence Checking. [Citation Graph (0, 0)][DBLP ] Conf ] Krishnan Srinivasan , Nagender Telkar , Vijay Ramamurthi , Karam S. Chatha System-Level Design Techniques for Throughput and Power Optimization of Multiprocessor SoC Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] M. Pirretti , Greg M. Link , R. R. Brooks , Narayanan Vijaykrishnan , Mahmut T. Kandemir , Mary Jane Irwin Fault Tolerant Algorithms for Network-On-Chip Interconnect. [Citation Graph (0, 0)][DBLP ] Conf ] Suryaprasad Jayadevappa , Ravi Shankar , Imad Mahgoub A Comparative Study of Modeling at Different Levels of Abstraction in System on Chip Designs: A Case Study. [Citation Graph (0, 0)][DBLP ] Conf ] Kristian Hildingsson , Tughrul Arslan , Ahmet T. Erdogan Energy Evaluation Methodology for Platform Based System-on-Chip Design. [Citation Graph (0, 0)][DBLP ] Conf ] Alain Lopez , Denis Deschacht Comparison between Different Data Buses Configurations. [Citation Graph (0, 0)][DBLP ] Conf ] Theo Theocharides , Greg M. Link , E. J. Swankoski , Narayanan Vijaykrishnan , Mary Jane Irwin , Herman Schmit Evaluating Alternative Implementations for LDPC Decoder Check Node Function. [Citation Graph (0, 0)][DBLP ] Conf ] Alireza Hodjat , Ingrid Verbauwhede Minimum Area Cost for a 30 to 70 Gbits/s AES Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Earl E. Swartzlander Jr. A Review of Large Parallel Counter Designs. [Citation Graph (0, 0)][DBLP ] Conf ] María C. Molina , Rafael Ruiz-Sautua , José M. Mendías , Román Hermida Behavioural Scheduling to Balance the Bit-Level Computational Effort. [Citation Graph (0, 0)][DBLP ] Conf ] Mahadevan Gomathisankaran , Akhilesh Tyagi WARM SRAM: A Novel Scheme to Reduce Static Leakage Energy in SRAM Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Walid Elgharbawy , Magdy A. Bayoumi New Bulk Dynamic Threshold NMOS Schemes for Low-Energy Subthreshold Domino-Like Circui. [Citation Graph (0, 0)][DBLP ] Conf ] Adam Strak , Hannu Tenhunen Suppression of Jitter Effects in A/D Converters through Sigma-Delta Sampling. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Celinski , Said F. Al-Sarawi , Derek Abbott , Sorin Cotofana , Stamatis Vassiliadis Logical Effort Based Design Exploration of 64-bit Adders Using a Mixed Dynamic-CMOS/Threshold-Logic Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Juang-Ying Chueh , Conrad H. Ziesler , Marios C. Papaefthymiou Experimental Evaluation of Resonant Clock Distribution. [Citation Graph (0, 0)][DBLP ] Conf ] Peiyi Zhao , Golconda Pradeep Kumar , C. Archana , Magdy A. Bayoumi A Double-Edge Implicit-Pulsed Level Convert Flip-Flop. [Citation Graph (0, 0)][DBLP ] Conf ] Joohee Kim , Conrad H. Ziesler Fixed-Load Energy Recovery Memory for Low Power. [Citation Graph (0, 0)][DBLP ] Conf ] W. Rhett Davis , Ambarish M. Sule , Hao Hua Multi-Parameter Power Minimization of Synthesized Datapaths. [Citation Graph (0, 0)][DBLP ] Conf ] Shu-Shin Chin , Sangjin Hong , Suhwan Kim Usage of Application-Specific Switching Activity for Energy Minimization of Arithmetic Units. [Citation Graph (0, 0)][DBLP ] Conf ] Mihir A. Shah , Janak H. Patel Enhancement of the Illinois Scan Architecture for Use with Multiple Scan Inputs. [Citation Graph (0, 0)][DBLP ] Conf ] Chunsheng Liu , Kumar N. Dwarakanath , Krishnendu Chakrabarty , Ronald D. Blanton Compact Dictionaries for Diagnosis of Unmodeled Faults in Scan-BIST. [Citation Graph (0, 0)][DBLP ] Conf ] Makoto Sugihara , Kazuaki Murakami , Yusuke Matsunaga Practical Test Architecture Optimization for System-on-a-Chip under Floorplanning Constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Ravi Namballa , Nagarajan Ranganathan , Abdel Ejnioui Control and Data Flow Graph Extraction for High-Level Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Hao Li , Wai-Kei Mak , Srinivas Katkoori Force-Directed Performance-Driven Placement Algorithm for FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Sankalp Kallakuri , Alex Doboli , Simona Doboli Stochastic Modeling Based Environment for Synthesis and Comparison of Bus Arbitration Policies. [Citation Graph (0, 0)][DBLP ] Conf ] Ghanshyam Nayak , Tejasvi Das , T. M. Rao , P. R. Mukund DREAM: A Chip-Package Co-Design Tool for RF-Mixed Signal Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Krzysztof Iniewski , Marek Syrzycki Low Power 2.5 Gb/s Serializer for SOC Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Jie Long , Jo Yi Foo , Robert J. Weber A 2.4 GHz Low-Power Low-Phase-Noise CMOS LC VCO. [Citation Graph (0, 0)][DBLP ] Conf ] Indrajit Atluri , Tughrul Arslan Reconfigurability-Power Trade-Offs in Turbo Decoder Design and Implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Erik J. Mentze , Kevin M. Buck , Herbert L. Hess , David F. Cox , Mohammad M. Mojarradi A Low Voltage to High Voltage Level Shifter in a Low Voltage, 0.25 µm, PD SOI Process. [Citation Graph (0, 0)][DBLP ] Conf ] Abdsamad Benkrid , Khaled Benkrid , Danny Crookes Design and Implementation of Novel FIR Filter Architecture for Efficient Signal Boundary Handling on Xilinx VIRTEX FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Ahmet T. Erdogan , Tughrul Arslan Low Power FIR Filter Implementations Based on Coefficient Ordering Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] S. Sukhsawas , Khaled Benkrid A High-Level Implementation of a High Performance Pipeline FFT on Virtex-E FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Kuo-Hsing Cheng , Shun-Wen Cheng , Che-Yu Liao 64-bit Low Threshold Voltage High-Speed Conditional Carry Adder by Complementary Pass-Transistor Logi. [Citation Graph (0, 0)][DBLP ] Conf ] Sophie Bouchoux , El-Bay Bourennane , Johel Mitéran , Michel Paindavoine Implementation of JPEG2000 Arithmetic Decoder on a Dynamically Reconfigurable ATMEL FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Lerong Cheng , William N. N. Hung , Guowu Yang , Xiaoyu Song Congestion Estimation for 3D Routing. [Citation Graph (0, 0)][DBLP ] Conf ] Hiren D. Patel , Sandeep K. Shukla Towards a Heterogeneous Simulation Kernel for System Level Models: A SystemC Kernel for Synchronous Data Flow Models. [Citation Graph (0, 0)][DBLP ] Conf ] Weisheng Chong , Masanori Hariyama , Michitaka Kameyama Low-Power Field-Programmable VLSI Processor Using Dynamic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Sangjin Hong , Shu-Shin Chin Incorporating Power Reduction Mechanism in Arithmetic Core Design. [Citation Graph (0, 0)][DBLP ] Conf ] Robert D. Kenney , Michael J. Schulte Multioperand Decimal Addition. [Citation Graph (0, 0)][DBLP ] Conf ] Abdel Ejnioui , Abdelhalim Alsharqawi Pipeline Design Based on Self-Resetting Stage Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Naotaka Ohsawa , Osamu Sakamoto , Masanori Hariyama , Michitaka Kameyama Program-Counter-Less Bit-Serial Field-Programmable VLSI Processor with Mesh-Connected Cellular Array Structure. [Citation Graph (0, 0)][DBLP ] Conf ] Chandramouli Gopalakrishnan , Srinivas Katkoori Tabu Search Based Behavioral Synthesis of Low Leakage Datapaths. [Citation Graph (0, 0)][DBLP ] Conf ] Arindam Mukherjee On the Reduction of Simultaneous Switching in SoCs. [Citation Graph (0, 0)][DBLP ] Conf ] Nattawut Thepayasuwan , Alex Doboli OSIRIS: Automated Synthesis of Flat and Hierarchical Bus Architectures for Deep Submicron Systems on Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Zipf , Claude Stötzler , Manfred Glesner A Configurable Pipelined State Machine as a Hybrid ASIC and Configurable Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Harpreet S. Narula , John G. Harris Integrated VLSI Potentiostat for Cyclic Voltammetry in Electrolytic Reactions. [Citation Graph (0, 0)][DBLP ] Conf ] Rajarshi Mukherjee , Alex K. Jones , Prithviraj Banerjee Handling Data Streams while Compiling C Programs onto Hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Shankar Krithivasan , Michael J. Schulte , John Glossner A Subword-Parallel Multiplication and Sum-of-Squares Unit. [Citation Graph (0, 0)][DBLP ] Conf ] Troy D. Townsend , Peter Celinski , Said F. Al-Sarawi , Michael J. Liebelt Hybrid Parallel Counters - Domino and Threshold Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Peter-Michael Seidel , Kenneth Fazel Two-Dimensional Folding Strategies for Improved Layouts of Cyclic Shifters. [Citation Graph (0, 0)][DBLP ] Conf ] Gwenolé Corre , Eric Senn , Nathalie Julien , Eric Martin A Memory Aware High Level Synthesis Tool . [Citation Graph (0, 0)][DBLP ] Conf ] Maciej Bellos , Dimitris Bakalis , Dimitris Nikolos Scan Cell Ordering for Low Power BIST. [Citation Graph (0, 0)][DBLP ] Conf ] Xrysovalantis Kavousianos , Dimitris Bakalis , Maciej Bellos , Dimitris Nikolos An Efficient Test Vector Ordering Method for Low Power Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Bassam Shaer Concurrent Pseudo-Exhaustive Testing of Combinational VLSI Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Chandrasekar Rajagopal , Adrián Núñez-Aldana CMOS Analog Programmable Logic Array. [Citation Graph (0, 0)][DBLP ] Conf ] S. Matakias , Y. Tsiatouhas , Th. Haniotakis , Angela Arapoyanni Ultra Fast and Low Cost Parallel Two-Rail Code Checker Targeting High Fan-In Applications . [Citation Graph (0, 0)][DBLP ] Conf ] John Thompson , Nandini Karra , Michael J. Schulte A 64-bit Decimal Floating-Point Adder. [Citation Graph (0, 0)][DBLP ] Conf ] Nick Iliev , James E. Stine , Nathan Jachimiec Parallel Programmable Finite Field GF(2m) Multipliers. [Citation Graph (0, 0)][DBLP ] Conf ] Magesh Sadasivam , Sangjin Hong Autonomous Buffer Controller Design for Concurrent Execution in Block Level Pipelined Dataflow. [Citation Graph (0, 0)][DBLP ] Conf ] Wei Zhang 0002 Compiler-Directed Data Cache Leakage Reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Venu G. Gudise , Ganesh K. Venayagamoorthy FPGA Placement and Routing Using Particle Swarm Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Abdel Ejnioui , Abdelkader Rhiati A Reconfigurable Memory Management Core for Java Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Krishnan Srinivasan , Vijay Ramamurthi , Karam S. Chatha A Technique for Energy versus Quality of Service Trade-Off for MPEG-2 Decoder. [Citation Graph (0, 0)][DBLP ] Conf ] Christian Panis , Ulrich Hirnschrott , Andreas Krall , Gunther Laure , Wolfgang Lazian , Jari Nurmi FSEL - Selective Predicated Execution for a Configurable DSP Core. [Citation Graph (0, 0)][DBLP ] Conf ] Yuan Li , John G. Harris A Spiking Recurrent Neural Network. [Citation Graph (0, 0)][DBLP ] Conf ] 