The SCEAS System
Navigation Menu

Conferences in DBLP

Annual Symposium on VLSI (isvlsi)
2004 (conf/isvlsi/2004)

  1. Michael T. Niemier, Peter M. Kogge
    The "4-Diamond Circuit" - A Minimally Complex Nano-Scale Computational Building Block in QCA. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:3-10 [Conf]
  2. Benjamin Gojman, Eric Rachlin, John E. Savage
    Decoding of Stochastically Assembled Nanoarrays. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:11-18 [Conf]
  3. A. J. KleinOsowski, David J. Lilja
    The NanoBox Project: Exploring Fabrics of Self-Correcting Logic Blocks for High Defect Rate Molecular Device Technologies. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:19-24 [Conf]
  4. Debayan Bhaduri, Sandeep K. Shukla
    NANOLAB: A Tool for Evaluating Reliability of Defect-Tolerant Nano Architectures. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:25-31 [Conf]
  5. Lun Li, Mitchell A. Thornton, Stephen A. Szygenda
    A Genetic Approach for Conjunction Scheduling in Symbolic Equivalence Checking. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:32-38 [Conf]
  6. Krishnan Srinivasan, Nagender Telkar, Vijay Ramamurthi, Karam S. Chatha
    System-Level Design Techniques for Throughput and Power Optimization of Multiprocessor SoC Architectures. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:39-45 [Conf]
  7. M. Pirretti, Greg M. Link, R. R. Brooks, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
    Fault Tolerant Algorithms for Network-On-Chip Interconnect. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:46-51 [Conf]
  8. Suryaprasad Jayadevappa, Ravi Shankar, Imad Mahgoub
    A Comparative Study of Modeling at Different Levels of Abstraction in System on Chip Designs: A Case Study. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:52-60 [Conf]
  9. Kristian Hildingsson, Tughrul Arslan, Ahmet T. Erdogan
    Energy Evaluation Methodology for Platform Based System-on-Chip Design. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:61-68 [Conf]
  10. Alain Lopez, Denis Deschacht
    Comparison between Different Data Buses Configurations. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:69-76 [Conf]
  11. Theo Theocharides, Greg M. Link, E. J. Swankoski, Narayanan Vijaykrishnan, Mary Jane Irwin, Herman Schmit
    Evaluating Alternative Implementations for LDPC Decoder Check Node Function. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:77-82 [Conf]
  12. Alireza Hodjat, Ingrid Verbauwhede
    Minimum Area Cost for a 30 to 70 Gbits/s AES Processor. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:83-88 [Conf]
  13. Earl E. Swartzlander Jr.
    A Review of Large Parallel Counter Designs. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:89-98 [Conf]
  14. María C. Molina, Rafael Ruiz-Sautua, José M. Mendías, Román Hermida
    Behavioural Scheduling to Balance the Bit-Level Computational Effort. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:99-104 [Conf]
  15. Mahadevan Gomathisankaran, Akhilesh Tyagi
    WARM SRAM: A Novel Scheme to Reduce Static Leakage Energy in SRAM Arrays. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:105-114 [Conf]
  16. Walid Elgharbawy, Magdy A. Bayoumi
    New Bulk Dynamic Threshold NMOS Schemes for Low-Energy Subthreshold Domino-Like Circui. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:115-120 [Conf]
  17. Adam Strak, Hannu Tenhunen
    Suppression of Jitter Effects in A/D Converters through Sigma-Delta Sampling. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:121-126 [Conf]
  18. Peter Celinski, Said F. Al-Sarawi, Derek Abbott, Sorin Cotofana, Stamatis Vassiliadis
    Logical Effort Based Design Exploration of 64-bit Adders Using a Mixed Dynamic-CMOS/Threshold-Logic Approach. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:127-134 [Conf]
  19. Juang-Ying Chueh, Conrad H. Ziesler, Marios C. Papaefthymiou
    Experimental Evaluation of Resonant Clock Distribution. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:135-140 [Conf]
  20. Peiyi Zhao, Golconda Pradeep Kumar, C. Archana, Magdy A. Bayoumi
    A Double-Edge Implicit-Pulsed Level Convert Flip-Flop. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:141-144 [Conf]
  21. Joohee Kim, Conrad H. Ziesler
    Fixed-Load Energy Recovery Memory for Low Power. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:145-150 [Conf]
  22. W. Rhett Davis, Ambarish M. Sule, Hao Hua
    Multi-Parameter Power Minimization of Synthesized Datapaths. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:151-157 [Conf]
  23. Shu-Shin Chin, Sangjin Hong, Suhwan Kim
    Usage of Application-Specific Switching Activity for Energy Minimization of Arithmetic Units. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:158-166 [Conf]
  24. Mihir A. Shah, Janak H. Patel
    Enhancement of the Illinois Scan Architecture for Use with Multiple Scan Inputs. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:167-172 [Conf]
  25. Chunsheng Liu, Kumar N. Dwarakanath, Krishnendu Chakrabarty, Ronald D. Blanton
    Compact Dictionaries for Diagnosis of Unmodeled Faults in Scan-BIST. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:173-178 [Conf]
  26. Makoto Sugihara, Kazuaki Murakami, Yusuke Matsunaga
    Practical Test Architecture Optimization for System-on-a-Chip under Floorplanning Constraints. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:179-186 [Conf]
  27. Ravi Namballa, Nagarajan Ranganathan, Abdel Ejnioui
    Control and Data Flow Graph Extraction for High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:192- [Conf]
  28. Hao Li, Wai-Kei Mak, Srinivas Katkoori
    Force-Directed Performance-Driven Placement Algorithm for FPGAs. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:193-198 [Conf]
  29. Sankalp Kallakuri, Alex Doboli, Simona Doboli
    Stochastic Modeling Based Environment for Synthesis and Comparison of Bus Arbitration Policies. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:199-206 [Conf]
  30. Ghanshyam Nayak, Tejasvi Das, T. M. Rao, P. R. Mukund
    DREAM: A Chip-Package Co-Design Tool for RF-Mixed Signal Systems. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:207-210 [Conf]
  31. Krzysztof Iniewski, Marek Syrzycki
    Low Power 2.5 Gb/s Serializer for SOC Applications. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:211-212 [Conf]
  32. Jie Long, Jo Yi Foo, Robert J. Weber
    A 2.4 GHz Low-Power Low-Phase-Noise CMOS LC VCO. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:213-214 [Conf]
  33. Indrajit Atluri, Tughrul Arslan
    Reconfigurability-Power Trade-Offs in Turbo Decoder Design and Implementation. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:215-217 [Conf]
  34. Erik J. Mentze, Kevin M. Buck, Herbert L. Hess, David F. Cox, Mohammad M. Mojarradi
    A Low Voltage to High Voltage Level Shifter in a Low Voltage, 0.25 µm, PD SOI Process. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:218-221 [Conf]
  35. Abdsamad Benkrid, Khaled Benkrid, Danny Crookes
    Design and Implementation of Novel FIR Filter Architecture for Efficient Signal Boundary Handling on Xilinx VIRTEX FPGAs. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:222-225 [Conf]
  36. Ahmet T. Erdogan, Tughrul Arslan
    Low Power FIR Filter Implementations Based on Coefficient Ordering Algorithm. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:226-228 [Conf]
  37. S. Sukhsawas, Khaled Benkrid
    A High-Level Implementation of a High Performance Pipeline FFT on Virtex-E FPGAs. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:229-232 [Conf]
  38. Kuo-Hsing Cheng, Shun-Wen Cheng, Che-Yu Liao
    64-bit Low Threshold Voltage High-Speed Conditional Carry Adder by Complementary Pass-Transistor Logi. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:233-236 [Conf]
  39. Sophie Bouchoux, El-Bay Bourennane, Johel Mitéran, Michel Paindavoine
    Implementation of JPEG2000 Arithmetic Decoder on a Dynamically Reconfigurable ATMEL FPGA. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:237-238 [Conf]
  40. Lerong Cheng, William N. N. Hung, Guowu Yang, Xiaoyu Song
    Congestion Estimation for 3D Routing. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:239-240 [Conf]
  41. Hiren D. Patel, Sandeep K. Shukla
    Towards a Heterogeneous Simulation Kernel for System Level Models: A SystemC Kernel for Synchronous Data Flow Models. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:241-242 [Conf]
  42. Weisheng Chong, Masanori Hariyama, Michitaka Kameyama
    Low-Power Field-Programmable VLSI Processor Using Dynamic Circuits. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:243-248 [Conf]
  43. Sangjin Hong, Shu-Shin Chin
    Incorporating Power Reduction Mechanism in Arithmetic Core Design. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:249-250 [Conf]
  44. Robert D. Kenney, Michael J. Schulte
    Multioperand Decimal Addition. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:251-253 [Conf]
  45. Abdel Ejnioui, Abdelhalim Alsharqawi
    Pipeline Design Based on Self-Resetting Stage Logic. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:254-257 [Conf]
  46. Naotaka Ohsawa, Osamu Sakamoto, Masanori Hariyama, Michitaka Kameyama
    Program-Counter-Less Bit-Serial Field-Programmable VLSI Processor with Mesh-Connected Cellular Array Structure. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:258-259 [Conf]
  47. Chandramouli Gopalakrishnan, Srinivas Katkoori
    Tabu Search Based Behavioral Synthesis of Low Leakage Datapaths. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:260-261 [Conf]
  48. Arindam Mukherjee
    On the Reduction of Simultaneous Switching in SoCs. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:262-263 [Conf]
  49. Nattawut Thepayasuwan, Alex Doboli
    OSIRIS: Automated Synthesis of Flat and Hierarchical Bus Architectures for Deep Submicron Systems on Chip. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:264-265 [Conf]
  50. Peter Zipf, Claude Stötzler, Manfred Glesner
    A Configurable Pipelined State Machine as a Hybrid ASIC and Configurable Architecture. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:266-267 [Conf]
  51. Harpreet S. Narula, John G. Harris
    Integrated VLSI Potentiostat for Cyclic Voltammetry in Electrolytic Reactions. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:268-270 [Conf]
  52. Rajarshi Mukherjee, Alex K. Jones, Prithviraj Banerjee
    Handling Data Streams while Compiling C Programs onto Hardware. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:271-272 [Conf]
  53. Shankar Krithivasan, Michael J. Schulte, John Glossner
    A Subword-Parallel Multiplication and Sum-of-Squares Unit. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:273-274 [Conf]
  54. Troy D. Townsend, Peter Celinski, Said F. Al-Sarawi, Michael J. Liebelt
    Hybrid Parallel Counters - Domino and Threshold Logic. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:275-276 [Conf]
  55. Peter-Michael Seidel, Kenneth Fazel
    Two-Dimensional Folding Strategies for Improved Layouts of Cyclic Shifters. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:277-278 [Conf]
  56. Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin
    A Memory Aware High Level Synthesis Tool . [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:279-280 [Conf]
  57. Maciej Bellos, Dimitris Bakalis, Dimitris Nikolos
    Scan Cell Ordering for Low Power BIST. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:281-284 [Conf]
  58. Xrysovalantis Kavousianos, Dimitris Bakalis, Maciej Bellos, Dimitris Nikolos
    An Efficient Test Vector Ordering Method for Low Power Testing. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:285-288 [Conf]
  59. Bassam Shaer
    Concurrent Pseudo-Exhaustive Testing of Combinational VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:289-290 [Conf]
  60. Chandrasekar Rajagopal, Adrián Núñez-Aldana
    CMOS Analog Programmable Logic Array. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:291-292 [Conf]
  61. S. Matakias, Y. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni
    Ultra Fast and Low Cost Parallel Two-Rail Code Checker Targeting High Fan-In Applications . [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:293-296 [Conf]
  62. John Thompson, Nandini Karra, Michael J. Schulte
    A 64-bit Decimal Floating-Point Adder. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:297-298 [Conf]
  63. Nick Iliev, James E. Stine, Nathan Jachimiec
    Parallel Programmable Finite Field GF(2m) Multipliers. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:299-302 [Conf]
  64. Magesh Sadasivam, Sangjin Hong
    Autonomous Buffer Controller Design for Concurrent Execution in Block Level Pipelined Dataflow. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:303-304 [Conf]
  65. Wei Zhang 0002
    Compiler-Directed Data Cache Leakage Reduction. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:305-306 [Conf]
  66. Venu G. Gudise, Ganesh K. Venayagamoorthy
    FPGA Placement and Routing Using Particle Swarm Optimization. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:307-308 [Conf]
  67. Abdel Ejnioui, Abdelkader Rhiati
    A Reconfigurable Memory Management Core for Java Applications. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:309-312 [Conf]
  68. Krishnan Srinivasan, Vijay Ramamurthi, Karam S. Chatha
    A Technique for Energy versus Quality of Service Trade-Off for MPEG-2 Decoder. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:313-316 [Conf]
  69. Christian Panis, Ulrich Hirnschrott, Andreas Krall, Gunther Laure, Wolfgang Lazian, Jari Nurmi
    FSEL - Selective Predicated Execution for a Configurable DSP Core. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:317-320 [Conf]
  70. Yuan Li, John G. Harris
    A Spiking Recurrent Neural Network. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:321-322 [Conf]
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002