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Conferences in DBLP

Annual Symposium on VLSI (isvlsi)
2003 (conf/isvlsi/2003)

  1. Justin E. Harlow III
    Toward Design Technology in 2020: Trends, Issues, and Challenges. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:3-4 [Conf]
  2. José A. B. Fortes
    Future Challenges in VLSI Design. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:5-7 [Conf]
  3. Radu Marculescu
    Networks-On-Chip: The Quest for On-Chip Fault-Tolerant Communication. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:8-12 [Conf]
  4. Shamik Das, Anantha Chandrakasan, Rafael Reif
    Three-Dimensional Integrated Circuits: Performance, Design Methodology, and CAD Tools. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:13-18 [Conf]
  5. Sarah E. Frost, Arun Rodrigues, Charles A. Giefer, Peter M. Kogge
    Bouncing Threads: Merging a New Execution Model into a Nanotechnology Memory. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:19-28 [Conf]
  6. Koushik K. Das, Richard B. Brown
    Novel Circuit Styles for Minimization of Floating Body Effects in Scaled PD-SOI CMOS. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:29-34 [Conf]
  7. E. Malley, A. Salinas, K. Ismail, Lawrence T. Pileggi
    Power Comparison of Throughput Optimized IC Busses. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:35-44 [Conf]
  8. Yonghee Im, Kaushik Roy
    LALM: A Logic-Aware Layout Methodology to Enhance the Noise Immunity of Domino Circuits. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:45-54 [Conf]
  9. Srividya Srinivasaraghavan, Wayne Burleson
    Interconnect Effort - A Unification of Repeater Insertion and Logical Effort. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:55-61 [Conf]
  10. Makram M. Mansour, Mohammad M. Mansour, Amit Mehrotra
    Modified Sakurai-Newton Current Model and its Applications to CMOS Digital Circuit Design. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:62-69 [Conf]
  11. Robert B. Reese, Mitchell A. Thornton, Cherrice Traver
    A Fine-Grain Phased Logic CPU. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:70-79 [Conf]
  12. Kwang-Hyun Baek, Myung-Jun Choe, Sung-Mo Kang
    An Efficient Calibration Technique for Systematic Current-Mismatch of D/A Converters. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:80-86 [Conf]
  13. Chuanjun Zhang, Frank Vahid, Walid A. Najjar
    Energy Benefits of a Configurable Line Size Cache for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:87-91 [Conf]
  14. S. Kagan Agun, J. Morris Chang
    Reconfigurable Fast Memory Management System Design for Application Specific Processors. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:92-100 [Conf]
  15. Jolin M. Warren, Thomas L. Martin, Asim Smailagic, Daniel P. Siewiorek
    System Design Approach To Power Aware Mobile Computers. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:101-106 [Conf]
  16. Jürgen Becker, Martin Vorbach
    Architecture, Memory and Interface Technology Integration of an Industrial/Academic Configurable System-on-Chip (CSoC). [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:107-112 [Conf]
  17. Catherine H. Gebotys, Robert J. Gebotys
    A Framework for Security on NoC Technologies. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:113-120 [Conf]
  18. Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi
    Peak Power Minimization Through Datapath Scheduling. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:121-126 [Conf]
  19. Jie S. Hu, Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut T. Kandemir
    Using Dynamic Branch Behavior for Power-Efficient Instruction Fetch. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:127-132 [Conf]
  20. Conrad H. Ziesler, Joohee Kim, Marios C. Papaefthymiou
    Energy Recovering ASIC Design. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:133-138 [Conf]
  21. Yu Bai, R. Iris Bahar
    A Dynamically Reconfigurable Mixed In-Order/Out-of-Order Issue Queue for Power-Aware Microprocessors. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:139-148 [Conf]
  22. Robert Bai, Sarvesh H. Kulkarni, Wesley Kwong, Ashish Srivastava, Dennis Sylvester, David Blaauw
    An Implementation of a 32-bit ARM Processor Using Dual Power Supplies and Dual Threshold Voltages. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:149-154 [Conf]
  23. Maciej Bellos, Dimitri Kagaris, Dimitris Nikolos
    Low Power Test Set Embedding Based on Phase Shifters. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:155-160 [Conf]
  24. W. Kuang, J. S. Yuan, Abdel Ejnioui
    Supply Voltage Scalable System Design Using Self-Timed Circuits. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:161-166 [Conf]
  25. Ravishankar Arunachalam, Emrah Acar, Sani R. Nassif
    Optimal shielding/spacing metrics for low power design. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:167-172 [Conf]
  26. Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Kyu-won Choi, Abhijit Chatterjee
    An O(N)Supply Voltage Assignment Algorithm for Low-Energy Serially Connected CMOS Modules and a Heuristic Extension to Acyclic Data Flow Graphs. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:173-182 [Conf]
  27. Andrew B. Kahng, Bao Liu
    Q-Tree: A New Iterative Improvement Approach for Buffered Interconnect Optimization. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:183-188 [Conf]
  28. Mohamed A. Elgamel, Kannan S. Tharmalingam, Magdy A. Bayoumi
    Crosstalk Noise Analysis in Ultra Deep Submicrometer Technologies. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:189-192 [Conf]
  29. Tapani Ahonen, Tero Nurmi, Jari Nurmi, Jouni Isoaho
    Block-wise Extraction of Rent's Exponents for an Extensible Processor. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:193-202 [Conf]
  30. Sumeer Goel, Tarek Darwish, Magdy A. Bayoumi
    A Novel Technique for Noise-Tolerance in Dynamic Circuits. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:203-206 [Conf]
  31. Shang Xue, Bengt Oelmann
    Efficient VLSI Implementation of a VLC Decoder for Universal Variable Length Code. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:207-208 [Conf]
  32. Hanho Lee
    An Area-Efficient Euclidean Algorithm Block for Reed-Solomon Decoder. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:209-210 [Conf]
  33. Chandramouli Gopalakrishnan, Srinivas Katkoori
    An Architectural Leakage Power Simulator for VHDL Structural Datapaths. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:211-212 [Conf]
  34. Ming-Jung Seow, Hau T. Ngo, Vijayan K. Asari
    Systolic Array Implementation of Block Based Hopfield Neural Network for Pattern Association. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:213-214 [Conf]
  35. Satish Ravichandran, Vijayan K. Asari
    Pre-computatio of Rotatio Bits in Unidirectional CORDIC for Trigonometric and Hyperbolic Computations. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:215-216 [Conf]
  36. Jung-Lin Yang, Erik Brunvand
    Self-Timed Design with Dynamic Domino Circuits. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:217-219 [Conf]
  37. Jiangjiang Liu, Nihar R. Mahapatra, Krishnan Sundaresan
    Hardware-Only Compression to Reduce Cost and Improve Utilization of Address Buses. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:220-221 [Conf]
  38. Marc Leeman, Chantal Ykman, David Atienza, Vincenzo De Florio, Geert Deconinck
    Automated Dynamic Memory Data Type Implementation Exploration and Optimization. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:222-224 [Conf]
  39. Per Larsson-Edefors, Daniel Eckerbert, Henrik Eriksson, Lars J. Svensson
    Dual Threshold Voltage Circuits in the Presence of Resistive Interconnects. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:225-230 [Conf]
  40. Andrea Lodi, Luca Ciccarelli, Andrea Cappelli, Fabio Campi, Mario Toma
    Decoder-Based Multi-Context Interconnect Architecture. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:231-233 [Conf]
  41. Ioannis Papaefstathiou
    Titan II : An IPComp Processor for 10Gbit/sec networks. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:234-235 [Conf]
  42. Hyung-Jin Lee, Dong Sam Ha
    Frequency Domain Approach for CMOS Ultra-Wideband Radios. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:236-237 [Conf]
  43. W. Rhett Davis
    Getting High-Performance Silicon from System-Level Design. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:238-243 [Conf]
  44. Bassam Shaer, Kailash Aurangabadkar, Nitin Agarwal
    Testable Sequential Circuit Design: Partitioning for Pseudoexhaustive Test. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:244-245 [Conf]
  45. Shalini Ghosh, Sugato Basu, Nur A. Touba
    Joint Minimization of Power and Area in Scan Testing by Scan Cell Reordering. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:246-249 [Conf]
  46. Luca Benini, Davide Bruni, Alberto Macii, Enrico Macii
    Hardw are Implementation of Data Compression Algorithms for Memory Energy Optimization. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:250-251 [Conf]
  47. M. Madhu, V. Srinivasa Murty, V. Kamakoti
    Dynamic Coding Technique For Low-Power Data Bus. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:252-253 [Conf]
  48. Hongping Li, John K. Antonio, Sudarshan K. Dhall
    Fast and Precise Power Prediction for Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:254-259 [Conf]
  49. Jia Di, Jiann S. Yuan, Ronald F. DeMara
    High Throughput Power-Aware FIR Filter Design Based on Fine-Grain Pipelining Multipliers and Adders. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:260-261 [Conf]
  50. Krishnan Sundaresan, Nihar R. Mahapatra
    Code Compression Techniques for Embedded Systems and Their Effectiveness. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:262-263 [Conf]
  51. Sandeep K. Kondapuram, Peter M. Maurer
    Random Characterization of Design Automation Algorithms. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:264-265 [Conf]
  52. Hua Tang, Hui Zhang, Alex Doboli
    Layout-Aware Analog System Synthesis Based on Symbolic Layout Description and Combined Block Parameter Exploration, Placement and Global Routing. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:266-271 [Conf]
  53. Jihong Ren, Mark R. Greenstreet
    Equalizing Filter Design for Crosstalk Cancellation. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:272-274 [Conf]
  54. Jan Lundgren, Bengt Oelmann, Trond Ytterdal, Patrik Eriksson, Munir Abdalla, Mattias O'Nils
    Behavioral Simulation of Power Line Noise Coupling in Mixed-Signal Systems using SystemC. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:275-277 [Conf]
  55. Li Yang, J. S. Yuan
    Enhanced Techniques for Current Balanced Logic in Mixed-Signal ICs. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:278-279 [Conf]
  56. Jincheol Yoo, Kyusun Choi, Jahan Ghaznavi
    Quantum Voltage Comparator for 0.07 mum CMOS Flash A/D Converters. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:280-282 [Conf]
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NOTICE2
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