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Annual Symposium on VLSI (isvlsi)
2005 (conf/isvlsi/2005)


  1. Symposium Committees. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:- [Conf]

  2. Message from the Technical Program Chair. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:- [Conf]
  3. Melvin A. Breuer
    Let's Think Analog. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:2-5 [Conf]
  4. Eric Rachlin, John E. Savage, Benjamin Gojman
    Analysis of a Mask-Based Nanowire Decoder. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:6-13 [Conf]
  5. Guowu Yang, Xiaoyu Song, William N. N. Hung, Marek A. Perkowski
    Bi-Direction Synthesis for Reversible Circuits. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:14-19 [Conf]
  6. Visvesh S. Sathe, Marios C. Papaefthymiou, Conrad H. Ziesler
    Boost Logic: A High Speed Energy Recovery Circuit Family. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:22-27 [Conf]
  7. J. Lee, Narayanan Vijaykrishnan, Mary Jane Irwin
    High Performance Array Processor for Video Decoding. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:28-33 [Conf]
  8. Xinyu Guo, Carl Sechen
    High Speed Redundant Adder and Divider in Output Prediction Logic. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:34-41 [Conf]
  9. Aiyappan Natarajan, Vijay Shankar, Atul Maheshwari, Wayne Burleson
    Sensing Design Issues in Deep Submicron CMOS SRAMs. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:42-45 [Conf]
  10. Masanori Hariyama, Weisheng Chong, Sho Ogata, Michitaka Kameyama
    Novel Switch Block Architecture Using Non-Volatile Functional Pass-Gate for Multi-Context FPGAs. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:46-50 [Conf]
  11. Sheng Sun, Yi Han, Xinyu Guo, Kian Haur Chong, Larry McMurchie, Carl Sechen
    409ps 4.7 FO4 64b Adder Based on Output Prediction Logic in 0.18um CMOS. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:52-58 [Conf]
  12. Rüdiger Ebendt, Rolf Drechsler
    Quasi-Exact BDD Minimization Using Relaxed Best-First Search. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:59-64 [Conf]
  13. Juang-Ying Chueh, Marios C. Papaefthymiou, Conrad H. Ziesler
    Two-Phase Resonant Clock Distribution. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:65-70 [Conf]
  14. Huiying Yang, Anuradha Agarwal, Ranga Vemuri
    Fast Analog Circuit Synthesis Using Multiparameter Sensitivity Analysis Based on Element-Coefficient Diagrams. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:71-76 [Conf]
  15. Ana Rusu, Mohammed Ismail, Hannu Tenhunen
    A Modified Cascaded Sigma-Delta Modulator with Improved Linearity. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:77-82 [Conf]
  16. Jinwook Jang, Sheng Xu, Wayne Burleson
    Jitter in Deep Sub-Micron Interconnect. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:84-89 [Conf]
  17. Guilin Chen, Guangyu Chen, Ozcan Ozturk, Mahmut T. Kandemir
    Exploiting Inter-Processor Data Sharing for Improving Behavior of Multi-Processor SoCs. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:90-95 [Conf]
  18. Asim Smailagic, Daniel P. Siewiorek, Uwe Maurer, Anthony Rowe, Karen P. Tang
    eWatch: Context Sensitive System Design Case Study. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:98-103 [Conf]
  19. Hendra Saputra, Ozcan Ozturk, Narayanan Vijaykrishnan, Mahmut T. Kandemir, R. R. Brooks
    A Data-Driven Approach for Embedded Security. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:104-109 [Conf]
  20. Vijaykumar Ramamurthi, Jason McCollum, Christopher Ostler, Karam S. Chatha
    System Level Methodology for Programming CMP Based Multi-Threaded Network Processor Architectures. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:110-116 [Conf]
  21. Alexander Thomas, Jürgen Becker
    Multi-Grained Reconfigurable Datapath Structures for Online-Adaptive Reconfigurable Hardware Architectures. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:118-123 [Conf]
  22. Jong-Ru Guo, Chao You, Michael Chu, Okan Erdogan, Russell P. Kraft, John F. McDonald
    A High Speed Reconfigurable Gate Array for Gigahertz Applications. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:124-129 [Conf]
  23. Lun Li, Alex Fit-Florea, Mitchell A. Thornton, David W. Matula
    Hardware Implementation of an Additive Bit-Serial Algorithm for the Discrete Logarithm Modulo 2k. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:130-135 [Conf]
  24. Minoru Watanabe, Fuminori Kobayashi
    An Improved Dynamic Optically Reconfigurable Gate Array. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:136-141 [Conf]
  25. Tobias Schubert, Bernd Becker
    Lemma Exchange in a Microcontroller Based Parallel SAT Solver. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:142-147 [Conf]
  26. Zhengtao Yu, Xun Liu
    Power Analysis of Rotary Clock. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:150-155 [Conf]
  27. Wei Li, Sudhakar M. Reddy, Irith Pomeranz
    On Reducing Peak Current and Power during Test. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:156-161 [Conf]
  28. Soumik Ghosh, Soujanya Venigalla, Magdy Bayoumi
    Design and Implementaion of a 2D-DCT Architecture Using Coefficient Distributed Arithmetic. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:162-166 [Conf]
  29. Ranganath Gopalan, Chandramouli Gopalakrishnan, Srinivas Katkoori
    Leakage Power Driven Behavioral Synthesis of Pipelined Datapaths. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:167-172 [Conf]
  30. J. H. Han, Ahmet T. Erdogan, Tughrul Arslan
    High Speed Max-Log-MAP Turbo SISO Decoder Implementation Using Branch Metric Normalization. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:173-178 [Conf]
  31. V. Mahalingam, N. Ranganathan
    A Nonlinear Programming Based Power Optimization Methodology for Gate Sizing and Voltage Selection. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:180-185 [Conf]
  32. Daniel Hostetler, Yuan Xie
    Adaptive Power Management in Software Radios Using Resolution Adaptive Analog to Digital Converters. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:186-191 [Conf]
  33. Il-soo Lee, Jae-Hoon Jeong, Anthony P. Ambler
    Using the Nonlinear Property of FSR and Dictionary Coding for Reduction of Test Volume. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:194-199 [Conf]
  34. Avijit Dutta, Terence Rodrigues, Nur A. Touba
    Low Cost Test Vector Compression/Decompression Scheme for Circuits with a Reconfigurable Serial Multiplier. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:200-205 [Conf]
  35. Irith Pomeranz, Srikanth Venkataraman, Sudhakar M. Reddy
    Fault Diagnosis and Fault Model Aliasing. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:206-211 [Conf]
  36. Junhao Shi, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel
    PASSAT: Efficient SAT-Based Test Pattern Generation for Industrial Circuits. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:212-217 [Conf]
  37. Tian Xia, Hao Zheng, Jing Li, Ahmed Ginawi
    Self-Refereed On-Chip Jitter Measurement Circuit Using Vernier Oscillators. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:218-223 [Conf]
  38. Muzhou Shao, Youxin Gao, Li-Pen Yuan, Martin D. F. Wong
    IR Drop and Ground Bounce Awareness Timing Model. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:226-231 [Conf]
  39. Deepak Rautela, Rajendra Katti
    Design and Implementation of FPGA Router for Efficient Utilization of Heterogeneous Routing Resources. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:232-237 [Conf]
  40. Jurjen Westra, Patrick Groeneveld
    Post-Placement Pin Optimiztion. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:238-243 [Conf]
  41. Yijun Liu, Stephen B. Furber
    A Low Power Embedded Dataflow Coprocessor. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:246-247 [Conf]
  42. Saraju P. Mohanty, Ramakrishna Velagapudi, Valmiki Mukherjee, Hao Li
    Reduction of Direct Tunneling Power Dissipation during Behavioral Synthesis of Nanometer CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:248-249 [Conf]
  43. Renqiu Huang, Ranga Vemuri
    Sensitivity Analysis of a Cluster-Based Interconnect Model for FPGAs. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:250-251 [Conf]
  44. Joshua R. Dick, Kenneth B. Kent
    Analysis of Incremental Communication for Multilayer Neural Networks on a Field Programmable Gate Array. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:252-254 [Conf]
  45. Il-soo Lee, Yu-Ting Lin, Anthony P. Ambler
    Reduction of Power and Test Time by Removing Cluster of Don't-Care from Test Data Set. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:255-256 [Conf]
  46. Marco Ottavi, Luca Schiano, Fabrizio Lombardi, Salvatore Pontarelli, Gian-Carlo Cardarilli
    Evaluating the Data Integrity of Memory Systems by Configurable Markov Models. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:257-259 [Conf]
  47. Abdelhalim Alsharqawi, Abdel Ejnioui
    Synthesis of Self-Resetting Stage Logic Pipelines. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:260-262 [Conf]
  48. Indrajit Atluri, Ashwin K. Kumaraswamy
    Energy Efficient Architectures for the Log-MAP Decoder through Intelligent Memory Usage. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:263-265 [Conf]
  49. Kaiping Zeng, Sorin A. Huss
    RAMS: A VHDL-AMS Code Refactoring Tool Supporting High Level Analog Synthesis. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:266-267 [Conf]
  50. Bertrand Le Gal, Emmanuel Casseau, Sylvain Huet, Eric Martin
    Pipelined Memory Controllers for DSP Applications Handling Unpredictable Data Accesses. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:268-269 [Conf]
  51. A. Rao, Th. Haniotakis, Y. Tsiatouhas, H. Djemil
    The Use of Pre-Evaluation Phase in Dynamic CMOS Logic. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:270-271 [Conf]
  52. Vassilios A. Chouliaras, Tom R. Jacobs, Ashwin K. Kumaraswamy, José L. Núñez-Yáñez
    Configurable Multiprocessors for High-Performance MPEG-4 Video Coding. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:272-273 [Conf]
  53. Mototsugu Miyano, Minoru Watanabe, Fuminori Kobayashi
    Optically Differential Reconfigurable Gate Array Using an Optical System with VCSELs. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:274-275 [Conf]
  54. Takanori Kyogoku, Junpei Inoue, Hidenari Nakashima, Takumi Uezono, Kenichi Okada, Kazuya Masu
    Wire Length Distribution Model Considering Core Utilization for System on Chip. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:276-277 [Conf]
  55. Young Uk Yim, John F. McDonald, Russell P. Kraft
    12-23 GHz Ultra Wide Tuning Range Voltage-Controlled Ring Oscillator with Hybrid Control Schemes. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:278-279 [Conf]
  56. Hau T. Ngo, Rajkiran Gottumukkal, Vijayan K. Asari
    A Flexible and Efficient Hardware Architecture for Real-Time Face Recognition Based on Eigenface. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:280-281 [Conf]
  57. Suryanarayana Tatapudi, José G. Delgado-Frias
    A High Performance Hybrid Wave-Pipelined Multiplier. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:282-283 [Conf]
  58. Jurjen Westra, Patrick Groeneveld
    Towards Integration of Quadratic Placement and Pin Assignment. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:284-286 [Conf]
  59. Hui Guo, Sri Parameswaran
    Balancing System Level Pipelines with Stage Voltage Scaling. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:287-289 [Conf]
  60. Alexander Maili, Christian Steger, Reinhold Weiss, Rob Quigley, Damian Dalton
    Reducing the Communication Bottleneck via On-Chip Cosimulation of Gate-Level HDL and C-Models on a Hardware Accelerator. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:290-291 [Conf]
  61. Marco Ottavi, Vamsi Vankamamidi, Fabrizio Lombardi, Salvatore Pontarelli, Adelio Salsano
    Design of a QCA Memory with Parallel Read/Serial Write. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:292-294 [Conf]
  62. Charan Thondapu, Praveen Elakkumanan, Ramalingam Sridhar
    RG-SRAM: A Low Gate Leakage Memory Design. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:295-296 [Conf]
  63. Feihui Li, Mahmut T. Kandemir
    Increasing Data TLB Resilience to Transient Errors. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:297-298 [Conf]
  64. Yuantao Peng, Xun Liu
    RITC: Repeater Insertion with Timing Target Compensation. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:299-300 [Conf]
  65. Adam R. Livingston, Hau T. Ngo, Ming Z. Zhang, Li Tao, Vijayan K. Asari
    Design of a Real Time System for Nonlinear Enhancement of Video Streams by an Integrated Neighborhood Dependent Approach. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:301-302 [Conf]
  66. Ming Z. Zhang, Hau T. Ngo, Adam R. Livingston, Vijayan K. Asari
    An Efficient VLSI Architecture for 2-D Convolution with Quadrant Symmetric Kernels. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:303-304 [Conf]
  67. Oswaldo Cadenas, Graham M. Megson, Daniel Jones
    A New Organization for a Perceptron-Based Branch Predictor and Its FPGA Implementation. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:305-306 [Conf]
  68. Fei He, Xiaoyu Song, Lerong Cheng, Guowu Yang, Zhiwei Tang, Ming Gu, Jia-Guang Sun
    A Hierachical Method for Wiring and Congestion Prediction. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:307-308 [Conf]
  69. D. P. Vasudevan, Parag K. Lala, James Patrick Parkerson
    CMOS Realization of Online Testable Reversible Logic Gates. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:309-310 [Conf]
  70. Jörg-Christian Niemann, Mario Porrmann, Ulrich Rückert
    A Scalable Parallel SoC Architecture for Network Processors. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:311-313 [Conf]
  71. Meng-Chiou Wu, Rung-Bin Lin
    A Comparative Study on Dicing of Multiple Project Wafers. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:314-315 [Conf]
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