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Conferences in DBLP

Annual Symposium on VLSI (isvlsi)
2006 (conf/isvlsi/2006)

  1. Norbert Wehn
    Advanced Channel Decoding Algorithms and Their Implementation for Future Communication Systems. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:3- [Conf]
  2. Wayne Wolf
    Multiprocessor Systems-on-Chips. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:4- [Conf]
  3. Tsung-Ying Sun, Sheng-Ta Hsieh, Hsiang-Min Wang, Cheng-Wei Lin
    Floorplanning Based on Particle Swarm Optimization. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:7-11 [Conf]
  4. Zahid Khan, John S. Thompson, Tughrul Arslan, Ahmet T. Erdogan
    Enhanced Dual Strategy based VLSI Architecture for Computing Pseudo Inverse of Channel Matrix in a MIMO Wireless System. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:12-17 [Conf]
  5. Takashi Nojima, Nobuto Ono, Shigetoshi Nakatake, Toru Fujimura, Koji Okazaki, Yoji Kajitani
    Adaptive Porting of Analog IPs with Reusable Conservative Properties. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:18-23 [Conf]
  6. Wael Adi, Rolf Ernst, Bassel Soudan, Abdulrahman Hanoun
    VLSI Design Exchange with Intellectual Property Protection in FPGA Environment Using both Secret and Public-Key Cryptography. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:24-32 [Conf]
  7. Qing K. Zhu, Paige Kolze
    Metal Fix and Power Network Repair for SOC. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:33-37 [Conf]
  8. Ning Fu, Mitsutoshi Mineshima, Shigetoshi Nakatake
    Multi-SP: A Representation with United Rectangles for Analog Placement and Routing. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:38-43 [Conf]
  9. Tan Yan, Shigetoshi Nakatake, Takashi Nojima
    Formulating the Empirical Strategies in Module Generation of Analog MOS Layout. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:44-49 [Conf]
  10. Ozcan Ozturk, G. Chen, Mahmut T. Kandemir, Mustafa Karaköy
    An Integer Linear Programming Based Approach to Simultaneous Memory Space Partitioning and Data Allocation for Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:50-58 [Conf]
  11. Zhiyu Liu, Volkan Kursun
    High Speed Low Swing Dynamic Circuits with Multiple Supply and Threshold Voltages. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:59-64 [Conf]
  12. Colm McKillen, Sakir Sezer, Xin Yang
    High performance service-time-stamp computation for WFQ IP packet scheduling. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:65-70 [Conf]
  13. Rashad Oreifej, Abdelhalim Alsharqawi, Abdel Ejnioui
    Synthesis of Pipelined SRSL Circuits. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:71-76 [Conf]
  14. Romualdo Begale Prudencio, Leandro Soares Indrusiak, Manfred Glesner
    An Efficient Hardware Implementation of a Self-Adaptable Equalizer for WCDMA Downlink UMTS Standard. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:77-84 [Conf]
  15. Evangelos F. Stefatos, Tughrul Arslan, Didier Keymeulen, Ian Ferguson
    Autonomous Realization of Boeing/JPL Sensor Electronics based on Reconfigurable System-on-Chip Technology. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:85-90 [Conf]
  16. Rahul Jain, Anindita Mukherjee, Kolin Paul
    Defect-Aware Design Paradigm for Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:91-96 [Conf]
  17. Michael Hübner, Christian Schuck, Matthias Kühnle, Jürgen Becker
    New 2-Dimensional Partial Dynamic Reconfiguration Techniques for Real-time Adaptive Microelectronic Circuits. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:97-102 [Conf]
  18. Victor Aken Ova, Resve Saleh
    A "Soft++" eFPGA Physical Design Approach with Case Studies in 180nm and 90nm. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:103-108 [Conf]
  19. Sunil Shukla, Neil W. Bergmann, Jürgen Becker
    QUKU: A Two-Level Reconfigurable Architecture. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:109-116 [Conf]
  20. Päivi H. Karjalainen, Pekka Heino
    Space-Saving Layout for Passive Components. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:117-121 [Conf]
  21. Supreet Joshi, Dinesh Sharma
    A Novel Low Power Multilevel Current Mode Interconnect System. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:122-127 [Conf]
  22. Sheng-Jang Lin, I-Shun Chen, Bo-Wei Chen, Feng-Hsiang Lo
    The Design of Analog Front-End Circuitry for 1X HD-DVD PRML Read Channel. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:128-132 [Conf]
  23. Miguel Figueroa, Esteban Matamala, Gonzalo Carvajal, Seth Bridges
    Adaptive Signal Processing in Mixed-Signal VLSI with Anti-Hebbian Learning. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:133-140 [Conf]
  24. Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, S. R. Pentakota, Chris Reade
    Verification of Scheduling in High-level Synthesis. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:141-146 [Conf]
  25. Ming Li, Wen-Ben Jone, Qing-An Zeng
    An Efficient Wrapper Scan Chain Configuration Method for Network-on-Chip Testing. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:147-152 [Conf]
  26. Xiaoyu Ruan, Rajendra Katti
    An Efficient Data-Independent Technique for Compressing Test Vectors in Systems-on-a-Chip. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:153-158 [Conf]
  27. Katarina Paulsson, Michael Hübner, Markus Jung, Jürgen Becker
    Methods for Run-time Failure Recognition and Recovery in dynamic and partial Reconfigurable Systems Based on Xilinx Virtex-II Pro FPGAs. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:159-166 [Conf]
  28. Chan-Hao Chang, Diana Marculescu
    Design and Analysis of a Low Power VLIW DSP Core. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:167-172 [Conf]
  29. Pankaj Golani, Peter A. Beerel
    High-Performance Noise-Robust Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:173-178 [Conf]
  30. Ilhan Kaya, Taskin Koçak
    A Low Power Lookup Technique for Multi-Hashing Network Applications. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:179-184 [Conf]
  31. J. H. Han, Ahmet T. Erdogan, Tughrul Arslan
    A Low Power Pipelined Maximum Likelihood Detector for 4x4 QPSK MIMO Wireless Communication Systems. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:185-192 [Conf]
  32. Masanori Hariyama, Michitaka Kameyama, Yasuhiro Kobayashi
    Optimal Periodical Memory Allocation for Logic-in-Memory Image Processors. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:193-198 [Conf]
  33. Esmail Amini, Mehrdad Najibi, Hossein Pedram
    Globally Asynchronous Locally Synchronous Wrapper Circuit based on Clock Gating. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:193-199 [Conf]
  34. Zhonghai Lu, Bei Yin, Axel Jantsch
    Connection-oriented Multicasting in Wormhole-switched Networks on Chip. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:205-2110 [Conf]
  35. Nikolay Kavaldjiev, Gerard J. M. Smit, Pierre G. Jansen, Pascal T. Wolkotte
    A Virtual Channel Network-on-Chip for GT and BE traffic. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:211-216 [Conf]
  36. Ethiopia Nigussie, Juha Plosila, Jouni Isoaho
    Delay-Insensitive On-Chip Communication Link using Low-Swing Simultaneous Bidirectional Signaling. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:217-224 [Conf]
  37. Eric Rachlin, John E. Savage
    Nanowire Addressing in the Face of Uncertainty. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:225-230 [Conf]
  38. Ryuji Ohba, Daisuke Matsushita, Koichi Muraoka, Shinichi Yasuda, Tetsufumi Tanamoto, Ken Uchida, Shinobu Fujita
    Si Nanocrystal MOSFET with Silicon Nitride Tunnel Insulator for High-rate Random Number Generation. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:231-236 [Conf]
  39. Jialin Mi, Chunhong Chen
    Finite State Machine Implementation with Single-Electron Tunneling Technology. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:237-241 [Conf]
  40. Xiaobo Sharon Hu, Michael Crocker, Michael T. Niemier, Minjun Yan, Gary Bernstein
    PLAs in Quantum-dot Cellular Automata. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:242-250 [Conf]
  41. Pascal Benoit, Lionel Torres, Gilles Sassatelli, Michel Robert, Gaston Cambon, Jürgen Becker
    Dynamic Hardware Multiplexing: Improving Adaptability with a Run Time Reconfiguration Manager. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:251-256 [Conf]
  42. Francisco-Javier Veredas, Michael Scheppler, Bumei Zhai, Hans-Jörg Pfleiderer
    Regular Routing Architecture for a LUT-based MPGA. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:257-262 [Conf]
  43. Zied Marrakchi, Hayder Mrabet, Habib Mehrez
    A new Multilevel Hierarchical MFPGA and its suitable configuration tools. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:263-268 [Conf]
  44. Nicolas Bruchon, Lionel Torres, Gilles Sassatelli, Gaston Cambon
    New non-volatile FPGA concept using Magnetic Tunneling Junction. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:269-276 [Conf]
  45. Kugan Vivekanandarajah, Thambipillai Srikanthan, Christopher T. Clarke
    Profile Directed Instruction Cache Tuning for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:277-282 [Conf]
  46. Yuriy Sheynin, Elena Suvorova, Felix Shutenko
    Complexity and Low Power Issues for On-chip Interconnections in MPSoC System Level Design. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:283-288 [Conf]
  47. Peter Hallschmid, Resve Saleh
    Fast Configuration of an Energy-Efficient Branch Predictor. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:289-294 [Conf]
  48. Feihui Li, Mahmut T. Kandemir, Ibrahim Kolcu
    Exploiting Software Pipelining for Network-on-Chip architectures. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:295-302 [Conf]
  49. Osama Neiroukh, Stephen A. Edwards, Xiaoyu Song
    An Efficient Algorithm for the Analysis of Cyclic Circuits. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:303-308 [Conf]
  50. Thomas Schlichter, Martin Lukasiewycz, Christian Haubelt, Jürgen Teich
    Improving System Level Design Space Exploration by Incorporating SAT-Solvers into Multi-Objective Evolutionary Algorithms. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:309-316 [Conf]
  51. Robert P. McEvoy, Francis M. Crowe, Colin C. Murphy, William P. Marnane
    Optimisation of the SHA-2 Family of Hash Functions on FPGAs. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:317-322 [Conf]
  52. Vijay Sundaresan, Ranga Vemuri
    A Novel Approach to Performance-Oriented Datapath Allocation and Floorplanning. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:323-328 [Conf]
  53. Nagarajan Ranganathan, Ravi Namballa, Narender Hanchate
    CHESS: A Comprehensive Tool for CDFG Extraction and Synthesis of Low Power Designs from VHDL. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:329-334 [Conf]
  54. Christian Genz, Rolf Drechsler
    System Exploration of SystemC Designs. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:335-342 [Conf]
  55. Shengqi Yang, Wayne Wolf, Narayanan Vijaykrishnan, Yuan Xie
    Reliability-Aware SOC Voltage Islands Partition and Floorplan. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:343-348 [Conf]
  56. Pinar Korkmaz, Bilge E. S. Akgul, Krishna V. Palem
    Ultra-Low Energy Computing with Noise: Energy-Performance-Probability Trade-offs. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:349-354 [Conf]
  57. Madhu Mutyam, Melvin Eze, Narayanan Vijaykrishnan, Yuan Xie
    Delay and Energy Efficient Data Transmission for On-Chip Buses. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:355-360 [Conf]
  58. Jialin Mi, Chunhong Chen
    Power-Oriented Delay Budgeting for Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:361-366 [Conf]
  59. Alkan Cengiz, Tom Chen
    Routing-Tree Construction with Concurrent Performance, Power and Congestion Optimization. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:367-372 [Conf]
  60. A. S. Seyedi, S. H. Rasouli, A. Amirabadi, Ali Afzali-Kusha
    Clock Gated Static Pulsed Flip-Flop (CGSPFF) in Sub 100 nm Technology. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:373-377 [Conf]
  61. Zhiyi Yu, Bevan M. Baas
    Performance and Power Analysis of Globally Asynchronous Locally Synchronous Multi-Processor Systems. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:378-383 [Conf]
  62. Kiran Puttaswamy, Gabriel H. Loh
    Implementing Register Files for High-Performance Microprocessors in a Die-Stacked (3D) Technology. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:384-392 [Conf]
  63. Feihui Li, Ozcan Ozturk, Guangyu Chen, Mahmut T. Kandemir, Ibrahim Kolcu
    Leakage-Aware SPM Management. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:393-398 [Conf]
  64. Feng Wang 0004, Yuan Xie, Kerry Bernstein, Yan Luo
    Dependability Analysis of Nano-scale FinFET circuits. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:399-404 [Conf]
  65. Chua-Chin Wang, Gang-Neng Sung
    A Low-Power 2-Dimensional Bypassing Multiplier Using 0.35 um CMOS Technology. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:405-410 [Conf]
  66. Ali Jahanian, Morteza Saheb Zamani
    Multi-Level Buffer Block Planning and Buffer Insertion for Large Design Circuits. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:411-415 [Conf]
  67. Seyed E. Esmaeili, Nabil I. Khachab, Moustafa Y. Ghannam
    Effect of Glitches on the Efficiency of Components' Region-Constrained Placement as a Fast Approach to Reduce FPGA's Dynamic Power Consumption. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:416-417 [Conf]
  68. Ali Habibi, Haja Moinudeen, Amer Samarah, Sofiène Tahar
    Towards a Faster Simulation of SystemC Designs. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:418-419 [Conf]
  69. Mahnaz Sadoughi Yarandi, Armin Alaghi, Zainalabedin Navabi
    An Optimized BIST Architecture for FPGA Look-Up Table Testing. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:420-421 [Conf]
  70. Suresh Srinivasan, Narayanan Vijaykrishnan
    Variation Aware Placement for FPGAs. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:422-423 [Conf]
  71. Claudio Menezes, Cristina Meinhardt, Ricardo Reis, Reginaldo Tavares
    A Regular Layout Approach for ASICs. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:424-425 [Conf]
  72. José Carlos S. Palma, Ricardo A. L. Reis, Leandro Soares Indrusiak, Alberto García Ortiz, Manfred Glesner, Fernando Gehm Moraes
    Evaluating the Impact of Data Encoding Techniques on the Power Consumption in Networks-on-Chip. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:426-427 [Conf]
  73. Johannes Grad, James E. Stine
    Dual-Mode High-Speed Low-Energy Binary Addition. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:428-429 [Conf]
  74. Erwan Piriou, Christophe Jégo, Patrick Adde, Michel Jézéquel
    A Flexible Architecture For Block Turbo Decoders Using BCH Or Reed-Solomon Components Codes. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:430-431 [Conf]
  75. Krzysztof Kosciuszkiewicz, Krzysztof Kepa, Fearghal Morgan
    Transparent Management of Reconfigurable Hardware in Embedded Operating Systems. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:432-433 [Conf]
  76. Alisson V. De Brito, Elmar U. K. Melcher, Wilson Rosas
    An open-source tool for simulation of partially reconfigurable systems using SystemC. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:434-435 [Conf]
  77. Florent Berthelot, Fabienne Nouvel
    Partial and Dynamic Reconfiguration of FPGAs: a top down design methodology for an automatic implementation. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:436-437 [Conf]
  78. David Fang, Filipp Akopyan, Rajit Manohar
    Self-Timed Thermally-Aware Circuits. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:438-439 [Conf]
  79. Masood Dehyadgari, Mohsen Nickray, Ali Afzali-Kusha, Zainalabedin Navabi
    A New Protocol Stack Model for Network on Chip. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:440-441 [Conf]
  80. Jun Zhou, David Kinniment, Gordon Russell, Alex Yakovlev
    A Robust Synchronizer. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:442-443 [Conf]
  81. T. Takahashi, Ahmet T. Erdogan, Tughrul Arslan, J. H. Han
    Low Power Layered Space-Time Channel Detector Architecture for MIMO Systems. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:444-445 [Conf]
  82. Josef Haid, Dietmar Scheiblhofer
    Sensor-Driven Power Management: Enhancing Performance and Reliability of Autonomously Powered Systems. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:446-447 [Conf]
  83. Hakduran Koc, Suleyman Tosun, Ozcan Ozturk, Mahmut T. Kandemir
    Reducing Memory Requirements through Task Recomputation in Embedded Multi-CPU Systems. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:448-449 [Conf]
  84. Guangyu Chen, Feihui Li, Mahmut T. Kandemir, Ozcan Ozturk, I. Demirkiran
    Compiler-Directed Management of Leakage Power in Software-Managed Memories. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:450-451 [Conf]
  85. Theo Theocharides, Narayanan Vijaykrishnan, Mary Jane Irwin
    A Parallel Architecture for Hardware Face Detection. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:452-453 [Conf]
  86. Ciaran Toal, Sakir Sezer, Xin Yang
    A VLSI GFP Frame Delineation Circuit. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:454-455 [Conf]
  87. Itisha Chanodia, Dimitrios Velenis
    Effects of Parameter Variations and Crosstalk Noise on H-Tree Clock Distribution Networks. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:456-457 [Conf]
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002