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Conferences in DBLP

Annual Symposium on VLSI (isvlsi)
2007 (conf/isvlsi/2007)

  1. Jeffrey D. Hoffman, David Arditti Ilitzky, Anthony Chun, Aliaksei Chapyzhenka
    Overview of the Scalable Communications Core. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:3-8 [Conf]
  2. Youssef Atat, Nacer-Eddine Zergainoh
    Simulink-based MPSoC Design: New Approach to Bridge the Gap between Algorithm and Architecture Design. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:9-14 [Conf]
  3. Magnus Själander, Per Larsson-Edefors, Magnus Bjork
    A Flexible Datapath Interconnect for Embedded Applications. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:15-20 [Conf]
  4. Nicolas Saint-Jean, Gilles Sassatelli, Pascal Benoit, Lionel Torres, Michel Robert
    HS-Scale: a Hardware-Software Scalable MP-SOC Architecture for embedded Systems. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:21-28 [Conf]
  5. Nicolas Bruchon, Lionel Torres, Gilles Sassatelli, Gaston Cambon
    Technological hybridization for efficient runtime reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:29-34 [Conf]
  6. Alisson V. De Brito, Matthias Kühnle, Michael Hübner, Jürgen Becker, Elmar U. K. Melcher
    Modelling and Simulation of Dynamic and Partially Reconfigurable Systems using SystemC. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:35-40 [Conf]
  7. Michael Hübner, Lars Braun, Jürgen Becker, Christopher Claus, Walter Stechele
    Physical Configuration On-Line Visualization of Xilinx Virtex-II FPGAs. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:41-46 [Conf]
  8. Mateus B. Rutzig, Antonio Carlos Schneider Beck, Luigi Carro
    Transparent Dataflow Execution for Embedded Applications. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:47-54 [Conf]
  9. Kostas Siozios, Dimitrios Soudris
    A Novel Methodology for Temperature-Aware Placement and Routing of FPGAs. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:55-60 [Conf]
  10. Ricardo Ferreira, Alisson Garcia, Tiago Teixeira, João M. P. Cardoso
    A Polynomial Placement Algorithm for Data Driven Coarse-Grained Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:61-66 [Conf]
  11. Renato Fernandes Hentschke, Guilherme Flach, Felipe Pinto, Ricardo Reis
    3D-Vias Aware Quadratic Placement for 3D VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:67-72 [Conf]
  12. Tuhina Samanta, Prasun Ghosal, Hafizur Rahaman, Parthasarathi Dasgupta
    Minimum-Congestion Placement for Y-interconnects: Some studies and observations. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:73-80 [Conf]
  13. Roberto Pereira-Arroyo, Pablo Alvarado-Moya, Wolfgang H. Krautschneider
    Design of a MCML Gate Library Applying Multiobjective Optimization. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:81-85 [Conf]
  14. Lucas Brusamarello, Roberto da Silva, Ricardo A. L. Reis, Gilson I. Wirth
    Yield Analysis by Error Propagation Using Numerical Derivatives Considering WD and D2D variations. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:86-91 [Conf]
  15. Angelo P. E. Rosiello, Fabrizio Ferrandi, Davide Pandini, Donatella Sciuto
    A Hash-based Approach for Functional Regularity Extraction During Logic Synthesis. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:92-97 [Conf]
  16. Chin-Long Wey, Wei-Chien Tang, Shin-Yo Lin
    Efficient VLSI Implementation of Memory-Based FFT Processors for DVB-T Applications. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:98-106 [Conf]
  17. Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Yasuhiro Morita, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
    A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:107-112 [Conf]
  18. Shanq-Jang Ruan, Shang-Fang Tsai, Yu-Ting Pai
    Design and Analysis of Low Power Dynamic Bus Based on RLC simulation. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:113-118 [Conf]
  19. Liu Yang, Sheqin Dong, Yuchun Ma, Xianlong Hong
    Interconnect Power Optimization Based on Timing Analysis. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:119-124 [Conf]
  20. Mindaugas Drazdziulis, Per Larsson-Edefors, Lars J. Svensson
    Overdrive Power-Gating Techniques for Total Power Minimization. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:125-132 [Conf]
  21. Himanshu Arora, Nikolaus Klemmer, Thomas Jochum, Patrick Wolf
    Phase-Noise Driven System Design of Fractional-N Frequency Synthesizers and Validation With Measured Results. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:133-138 [Conf]
  22. Arthur Nieuwoudt, Tamer Ragheb, Yehia Massoud
    Systematic Design Optimization Methodology for Multi-Band CMOS Low Noise Amplifiers. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:139-144 [Conf]
  23. Angan Das, Ranga Vemuri
    An Automated Passive Analog Circuit Synthesis Framework using Genetic Algorithms. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:145-152 [Conf]
  24. Rajesh Thirugnanam, Dong Sam Ha, T. M. Mak
    Data Recovery Block Design for Impulse Modulated Power Line Communications in a Microprocessor. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:153-158 [Conf]
  25. Djones Lettnin, Markus Winterholer, Axel G. Braun, Joachim Gerlach, Jürgen Ruf, Thomas Kropf, Wolfgang Rosenstiel
    Coverage Driven Verification applied to Embedded Software. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:159-164 [Conf]
  26. Ulrich Kühne, Daniel Große, Rolf Drechsler
    Improving the Quality of Bounded Model Checking by Means of Coverage Estimation. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:165-170 [Conf]
  27. Prashant Dubey, Akhil Garg, Sravan Kumar Bhaskarani
    Low Area Adaptive Fail-Data Compression Methodology for Defect Classification and Production Phase Prognosis. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:171-178 [Conf]
  28. Teng Lin, Jianhua Feng, Yangyuan Wang
    A New Test Data Compression Scheme for Multi-scan Designs. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:179-185 [Conf]
  29. João M. S. Silva, L. Miguel Silveira
    On the Compressibility of Power Grid Models. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:186-191 [Conf]
  30. Tiago R. Balen, Fernanda Lima Kastensmidt, Marcelo Lubaszewski, Michel Renovell
    Single Event Upset in SRAM-based Field Programmable Analog Arrays: Effects and Mitigation. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:192-197 [Conf]
  31. Alair Dias Jr., Diógenes Cecilio da Silva Jr.
    Code-coverage Based Test Vector Generation for SystemC Designs. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:198-206 [Conf]
  32. Jorge Semião, J. Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, J. P. Teixeira
    Enhancing the Tolerance to Power-Supply Instability in Digital Circuits. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:207-212 [Conf]
  33. Taraneh Taghavi, Majid Sarrafzadeh
    Hierarchical Concurrent Congestion and Wirelength Estimation in the Presence of IP Blocks. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:213-218 [Conf]
  34. Hamid Reza Kheirabadi, Morteza Saheb Zamani, Mehdi Saeedi
    An Efficient Analytical Approach to Path-Based Buffer Insertion. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:219-224 [Conf]
  35. Narender Hanchate, Nagarajan Ranganathan
    Integrated Gate and Wire Sizing at Post Layout Level. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:225-232 [Conf]
  36. P. Marques Morgado, Paulo F. Flores, L. Miguel Silveira
    Generating Realistic Stimuli for Accurate Power Grid Analysis. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:233-238 [Conf]
  37. Hailong Yao, Yici Cai, Xianlong Hong
    CMP-aware Maze Routing Algorithm for Yield Enhancement. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:239-244 [Conf]
  38. Narender Hanchate, Nagarajan Ranganathan
    Statistical Gate Sizing for Yield Enhancement at Post Layout Level. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:245-252 [Conf]
  39. Alexandro Baldassin, Paulo Centoducatte, Sandro Rigo, Daniel C. Casarotto, Luiz C. V. dos Santos, Max R. de O. Schultz, Olinto Furtado
    Automatic Retargeting of Binary Utilities for Embedded Code Generation. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:253-258 [Conf]
  40. Michael Meitinger, Rainer Ohlendorf, Thomas Wild, Andreas Herkersdorf
    A Programmable Stream Processing Engine for Packet Manipulation in Network Processors. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:259-264 [Conf]
  41. Frederico De Faria, Marius Strum, Wang Jiang Chau
    A System-level Performance Evaluation Methodology for Netwrok Processors Based on Network Calculus Analytical Modeling. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:265-272 [Conf]
  42. Saihua Lin, Huazhong Yang, Rong Luo
    High Speed Soft-Error-Tolerant Latch and Flip-Flop Design for Multiple VDD Circuit. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:273-278 [Conf]
  43. Zhipeng Liu, Jinian Bian, Qiang Zhou, Hui Dai
    Interconnect Delay and Power Optimization by Module Duplication for Integration of High Level Synthesis and Floorplan. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:279-284 [Conf]
  44. J. Liu, Ian O'Connor, David Navarro, Frédéric Gaffiot
    Design of a Novel CNTFET-based Reconfigurable Logic Gate. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:285-290 [Conf]
  45. Shubhankar Basu, Ranga Vemuri
    Process Variation and NBTI Tolerant Standard Cells to Improve Parametric Yield and Lifetime of ICs. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:291-298 [Conf]
  46. José Carlos S. Palma, Leandro Soares Indrusiak, Fernando Gehm Moraes, Alberto García Ortiz, Manfred Glesner, Ricardo A. L. Reis
    Inserting Data Encoding Techniques into NoC-Based Systems. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:299-304 [Conf]
  47. Brett Feero, Partha Pratim Pande
    Performance Evaluation for Three-Dimensional Networks-On-Chip. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:305-310 [Conf]
  48. Lazaros Papadopoulos, Stylianos Mamagkakis, Francky Catthoor, Dimitrios Soudris
    Application - specific NoC platform design based on System Level Optimization. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:311-316 [Conf]
  49. Amlan Ganguly, Partha Pratim Pande, Benjamin Belzer, Cristian Grecu
    Addressing Signal Integrity in Networks on Chip Interconnects through Crosstalk-Aware Double Error Correction Coding. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:317-324 [Conf]
  50. Di Wu, Johan Eilert, Dake Liu, Dandan Wang, Naofal Al-Dhahir, Hlaing Minn
    Fast Complex Valued Matrix Inversion for Multi-User STBC-MIMO Decoding. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:325-330 [Conf]
  51. Antonino Tumeo, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto
    A Pipelined Fast 2D-DCT Accelerator for FPGA-based SoCs. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:331-336 [Conf]
  52. James E. Stine, Jeff M. Blank
    Partial Product Reduction for Parallel Cubing. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:337-342 [Conf]
  53. Sreehari Veeramachaneni, Kirthi M. Krishna, Lingamneni Avinash, Reddy Puppala Sreekanth, M. B. Srinivas
    Novel, High-Speed 16-Digit BCD Adders Conforming to IEEE 754r Format. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:343-350 [Conf]
  54. Richard Maciel, Bruno Albertini, Sandro Rigo, Guido Araujo, Rodolfo Azevedo
    A Methodology and Toolset to Enable SystemC and VHDL Co-simulation. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:351-356 [Conf]
  55. Mahmoud Ben Naser, Yao Guo, Csaba Andras Moritz
    Designing Memory Subsystems Resilient to Process Variations. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:357-363 [Conf]
  56. Shuai Wang, Hongyan Yang, Jie Hu, Sotirios G. Ziavras
    Asymmetrically Banked Value-Aware Register Files. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:363-368 [Conf]
  57. Andrew Tam, Sazzadur Chowdhury
    A MEMS Ultra-Stable Short Duration Current Pulse Generator. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:369-374 [Conf]
  58. Andrew J. Ricketts, Madhu Mutyam, Narayanan Vijaykrishnan, Mary Jane Irwin
    Investigating Simple Low Latency Reliable Multiported Register Files. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:375-382 [Conf]
  59. Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu
    Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:383-388 [Conf]
  60. Prashant Agrawal, Srinivasa R. S. T. G, Ajit N. Oke, Saurabh Vijay
    A Scalable Modeling Technique to Estimate Dynamic Thermal Design Power of Datapath Intensive Designs. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:389-394 [Conf]
  61. Felipe Klein, Guido Araujo, Rodolfo Azevedo, Roberto Leao, Luiz C. V. dos Santos
    On the Limitations of Power Macromodeling Techniques. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:395-400 [Conf]
  62. K. S. Sainarayanan, Chittarsu Raghunandan, M. B. Srinivas
    Delay and Power Minimization in VLSI Interconnects with Spatio-Temporal Bus-Encoding Scheme. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:401-408 [Conf]
  63. Hyunjin Lee, Sangyeun Cho, Bruce R. Childers
    Performance of Graceful Degradation for Cache Faults. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:409-415 [Conf]
  64. M. Sampson, Dimitrios Voudouris, George K. Papakonstantinou
    A Quantum Algorithm for Finding Minimum Exclusive-Or Expressions. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:416-421 [Conf]
  65. Mehrdad Najibi, Mahtab Niknahad, Hossein Pedram
    Performance Evaluation of Asynchronous Circuits with Choice Using Abstract Probabilistic Timed Petri Nets. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:422-427 [Conf]
  66. Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi
    On the Behavior of Substitution-based Reversible Circuit Synthesis Algorithms: Investigation and Improvement. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:428-436 [Conf]
  67. Abdel Ejnioui
    FPGA Prototyping of a Two-Phase Self-Oscillating Micropipeline. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:437-438 [Conf]
  68. Jer Min Jou, Yun-Lung Lee, Chen-Yen Lin, Chien-Ming Sun
    A Novel Reconfigurable Computation Unit for DSP Applications. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:439-444 [Conf]
  69. Bruno Zatt, Arnaldo Azevedo, Luciano Volcan Agostini, Altamiro Amadeu Susin, Sergio Bampi
    Memory Hierarchy Targeting Bi-Predictive Motion Compensation for H.264/AVC Decoder. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:445-446 [Conf]
  70. Hongyan Yang, Shuai Wang, Sotirios G. Ziavras, Jie Hu
    Vector Processing Support for FPGA-Oriented High Performance Applications. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:447-448 [Conf]
  71. Antonino Tumeo, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto
    An Internal Partial Dynamic Reconfiguration Implementation of the JPEG Encoder for Low-Cost FPGAsb. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:449-450 [Conf]
  72. Erico Bastos, Everton Carara, Daniel Pigatto, Ney Laert Vilar Calazans, Fernando Moraes
    MOTIM - A Scalable Architecture for Ethernet Switches. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:451-452 [Conf]
  73. Avishek Saha, Santosh Ghosh, Shamik Sural, Jayanta Mukherjee
    Toward Memory-efficient Design of Video Encoders for Multimedia Applications. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:453-454 [Conf]
  74. Arun Janarthanan, Vijay Swaminathan, Karen A. Tomko
    MoCReS: an Area-Efficient Multi-Clock On-Chip Network for Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:455-456 [Conf]
  75. S. Corbetta, Fabrizio Ferrandi, M. Morandi, M. Novati, Marco D. Santambrogio, Donatella Sciuto
    Two Novel Approaches to Online Partial Bitstream Relocation in a Dynamically Reconfigurable System. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:457-458 [Conf]
  76. Ewerson Carvalho, Ney Laert Vilar Calazans, Fernando Gehm Moraes
    Congestion-Aware Task Mapping in NoC-based MPSoCs with Dynamic Workload. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:459-460 [Conf]
  77. Fabiano Hessel, César A. M. Marcon, Tatiana Gadelha Serra Dos Santos
    High Level RTOS Scheduler Modeling for a Fast Design Validation. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:461-466 [Conf]
  78. Luciano Severino de Paula, Eric E. Fabris, Sergio Bampi, Altamiro Amadeu Susin
    A High Swing Low Power CMOS Differential Voltage-Controlled Ring Oscillator. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:467-470 [Conf]
  79. Mahtab Niknahad, Behnam Ghavami, Mehrdad Najibi, Hossein Pedram
    A Power Estimation Methodology for QDI Asynchronous Circuits based on High-Level Simulation. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:471-472 [Conf]
  80. Charles Thangaraj, Tom Chen
    Power andPerformance Analysis for Early Design Space Exploration. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:473-478 [Conf]
  81. F. Kharbash, G. M. Chaudhry
    Reliable Binary Signed Digit Number Adder Design. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:479-484 [Conf]
  82. Hector Kirschenbaum, Alejandro De la Plaza
    Voltage Pump Based on Self Clocked Cells. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:485-487 [Conf]
  83. Mohammad Azim Karami, Ali Afzali-Kusha, Reza Faraji-Dana, Masoud Rostami
    Quantitative Comparison of Optical and Electrical H, X, and Y clock Distribution Networks. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:488-489 [Conf]
  84. Vahid Moalemi, Ali Afzali-Kusha
    Subthreshold Pass Transistor Logic for Ultra-Low Power Operation. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:490-491 [Conf]
  85. Zhaolin Li, Gongqiong Li
    Design of A Double-Precision Floating- Point Multiply-Add-Fused Unit with Consideration of Data Dependence. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:492-497 [Conf]
  86. Franco Martin-Pirchio, Alfonso Chacon-Rodriguez, Pedro Julián, Pablo Sergio Mandolesi
    A comparison of low power architectures for digital delay measurement. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:498-499 [Conf]
  87. Salvador Ortiz, Roberto Suaya
    Efficient implementation of conduction modes for modelling skin effect. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:500-505 [Conf]
  88. M. Khalilzadeh, A. Nabavi
    A Low-Power High-Speed 4-Bit ADC for DS-UWB Communications. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:506-507 [Conf]
  89. Nainesh Agarwal, Nikitas J. Dimopoulos
    DSPstone Benchmark of CoDeL's Automated Clock Gating Platform. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:508-509 [Conf]
  90. Yokesh Kumar, Prosenjit Gupta
    An External Memory Circuit Validation Algorithm for Large VLSI Layouts. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:510-511 [Conf]
  91. Paulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas
    Modeling Subthreshold Leakage Current in General Transistor Networks. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:512-513 [Conf]
  92. Vahid Moalemi, Ali Afzali-Kusha
    Subthreshold 1-Bit Full Adder Cells in sub-100 nm Technologies. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:514-515 [Conf]
  93. Soumya Eachempati, Narayanan Vijaykrishnan, Arthur Nieuwoudt, Yehia Massoud
    Impact of Process Variations on Carbon Nanotube Bundle Interconnect for Future FPGA Architectures. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:516-517 [Conf]
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NOTICE2
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