Conferences in DBLP
Mark A. Myers DeltaI vs. DeltaY : A Quantitative Analysis of the Trade-offs Between Higher Capital Investment and Higher Yield in PCB Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Prab Varma , Anthony P. Ambler , Keith Baker An Analysis of the Economics of Self Test. [Citation Graph (0, 0)][DBLP ] Conf ] J. S. Pittman , W. C. Bruce Test Logic Economic Considerations in a Commercial VLSI Chip Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Gordon H. Bowers Jr , B. G. Pratt "Low Cost Testers" : Are They Really Low Cost ? [Citation Graph (0, 0)][DBLP ] Conf ] Joseph L. A. Hughes , Edward J. McCluskey An Analysis of the Multiple Fault Detection Capabilities of Single Stuck-at Fault Test Sets. [Citation Graph (0, 0)][DBLP ] Conf ] J. Paul Roth , Vojin G. Oklobdzija , John F. Beetem Test Generation for FET Switching Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Brian J. Heard , Ramu N. Sheshadri , Ronald B. David , Arvid G. Sammuli Automatic Test Pattern Generation for Asynchronous Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Harry H. Chen , Robert G. Mathews , John A. Newkirk Test Generation for MOS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Erwin Trischler ATWIG, An Automatic Test Pattern Generator with Inherent Guidance. [Citation Graph (0, 0)][DBLP ] Conf ] Tohru Sasaki , Shunichi Kato , Nobuyoshi Nomizu , Hidetoshi Tanaka Logic Design Verification Using Automated Test Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Alexander Holland High Resolution, High Linearity Interpolating A/D Converter. [Citation Graph (0, 0)][DBLP ] Conf ] William B. Abbott IV Time Specification Conformance of VLSI Test Systems O5. [Citation Graph (0, 0)][DBLP ] Conf ] Y. Nishimura , M. Hamada , Y. Hayasaka A New Timing Calibration Method for High Speed Memory Test. [Citation Graph (0, 0)][DBLP ] Conf ] Anthony J. Burke Software Convergence of Test Program Parameters. [Citation Graph (0, 0)][DBLP ] Conf ] Tadaaki Satoh , Akira Takagi , Masami Kita , Katsuhiko Shirakawa , Shimpei Takeshita 21-Bit Precision and High-Speed DC Measurement System. [Citation Graph (0, 0)][DBLP ] Conf ] Dilip K. Bhavsar , Balakrishnan Krishnamurthy Can We Eliminate Fault Escape in Self-Testing by Polynomial Division (Signature Analysis) ? [Citation Graph (0, 0)][DBLP ] Conf ] Yervant Zorian , Vinod K. Agarwal Higher Certainty of Error Coverage by Output Data Modification. [Citation Graph (0, 0)][DBLP ] Conf ] Zuhi Sun , Laung-Terng Wang Self-Testing of Embedded RAMs. [Citation Graph (0, 0)][DBLP ] Conf ] William H. McAnney , Paul H. Bardell , V. P. Gupta Random Testing for Stuck-At Storage Cells in an Embedded Memory. [Citation Graph (0, 0)][DBLP ] Conf ] Tom W. Williams Sufficient Testing In A Self-Testing Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Bulent I. Dervisoglu On Coosing a Hardware Descriptive Language for Digital Systems Testing/Verification. [Citation Graph (0, 0)][DBLP ] Conf ] A. Jesse Wilkinson A Method for Test System Diagnostics Based on the Principles of Artificial Intelligence. [Citation Graph (0, 0)][DBLP ] Conf ] Robert Mullis An Expert System for VLSI Tester Diagnostics. [Citation Graph (0, 0)][DBLP ] Conf ] Gordon D. Robinson Artificial Intelligence and Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Brian C. Crosby Adapting CAE Design Information for In-Circuit Test Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Graeme R. Kinsey Information and Material Flow Within a Production Test Cell. [Citation Graph (0, 0)][DBLP ] Conf ] Dharma P. Agrawal , Sami A. Al-Arian Comprehensive Fault Model and Testing of CMOS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Leslie Turner Smith , Roy R. Rezac Methodology for and Results from the Use of a Hardware Logic Simulation Engine for Fault Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Arthur Babitz , Kurt Lender Using Simulation in the Design Process - A Case Study. [Citation Graph (0, 0)][DBLP ] Conf ] Yashwant K. Malaiya , Shoubao Yang The Coverage Problem for Random Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Ramin Khorram Functional Test Pattern Generation for Integrated Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] M. Melgara , M. Paolini , R. Roncella , S. Morpurgo CVT-FERT : Automatic Generator of Analytical Faults at Register Transfer Level from Electrical and Topological Descriptions. [Citation Graph (0, 0)][DBLP ] Conf ] Frederick G. Hall , Robert G. Hillman , John M. Bednarczyk "Instant On" Semiconductor Memories: Reality or Myth. [Citation Graph (0, 0)][DBLP ] Conf ] E. Kurzweil , L. Jambut Access Time Evaluation of Fast Static MOS Memories. [Citation Graph (0, 0)][DBLP ] Conf ] Kozo Kinoshita , Kewal K. Saluja Built-in Testing of Memory Using On-chip Compact Testing Scheme. [Citation Graph (0, 0)][DBLP ] Conf ] Gene P. Bosse High Speed Redundancy Processor. [Citation Graph (0, 0)][DBLP ] Conf ] John R. Day A Fault-Driven, Comprehensive Redundancy Algorithm for Repair of Dynamic RAMs. [Citation Graph (0, 0)][DBLP ] Conf ] F. Pool , J. Hop , J. P. L. Lagerberg , C. Da Costa Testing a 317K bit High Speed Video Memory with a VSLI Test System. [Citation Graph (0, 0)][DBLP ] Conf ] Paul H. Bardell , William H. McAnney Parallel Pseudorandom Sequences for Built-In Test. [Citation Graph (0, 0)][DBLP ] Conf ] Corot W. Starke Built-In Test for CMOS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Ramaswami Dandapani , Janak H. Patel , Jacob A. Abraham Design of Test Pattern Generators for Built-In Test. [Citation Graph (0, 0)][DBLP ] Conf ] Syed Zahoor Hassan , Edward J. McCluskey Pseudo-Exhaustive Testing of Sequential Machines Using Signature Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Charles R. Kime , H. H. Kwan , J. K. Lemke , Gerald B. Williams A Built-In Test Methodology for VLSI Data Paths. [Citation Graph (0, 0)][DBLP ] Conf ] Yacoub M. El-Ziq , Hamid H. Butt Impact of Mixed-Mode Self Test on Life Cycle Cost of VLSI Based Design. [Citation Graph (0, 0)][DBLP ] Conf ] Dean Bandes Exploratory Data Analysis Makes Testing More Valuable for Semiconductor Manufacturing. [Citation Graph (0, 0)][DBLP ] Conf ] Kou Wada , Satoshi Tazawa , Katsutoshi Kubota A Flexible Database System and Its Application in VLSI Process Development. [Citation Graph (0, 0)][DBLP ] Conf ] Robert W. Atherton , Leonard Ekkelkamp , Chuck Schmitz Logic Device Characterization Using Computer-Aided Test and Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Sushil K. Malik , E. F. Chace MOS Gate Oxide Quality Control and Reliability Assessment by Voltage Ramping. [Citation Graph (0, 0)][DBLP ] Conf ] Wojciech Maly , F. Joel Ferguson , John Paul Shen Systematic Characterization of Physical Defects for Fault Analysis of MOS IC Cells. [Citation Graph (0, 0)][DBLP ] Conf ] G. Siva Bushanam , Vance R. Harwood , Philip N. King , Roger D. Story Measuring Thermal Rises Due to Digital Device Overdriving. [Citation Graph (0, 0)][DBLP ] Conf ] E. A. Sloane Transfer Function Estimation Part I : Theoretical and Practical Considerations. [Citation Graph (0, 0)][DBLP ] Conf ] James F. Campbell Jr. Transfer Function Estimation Part II : Some Experimental Results. [Citation Graph (0, 0)][DBLP ] Conf ] Douglas K. Shirachi CODEC Testing Using Synchronized Analog and Digital Signals. [Citation Graph (0, 0)][DBLP ] Conf ] Terence Lee In-Circuit Analog Component Testing at High Frequencies. [Citation Graph (0, 0)][DBLP ] Conf ] Robert S. Broughton , Michael G. Brashler The Future is Now: Extending CAE into Test of Custom VLSI. [Citation Graph (0, 0)][DBLP ] Conf ] Donald L. Wheater IBM's Cost Performance Array Tester Architecture for the 80's. [Citation Graph (0, 0)][DBLP ] Conf ] Philip C. Jackson , Gregory de Mare , Albert Esser Compaction Technique Universal Pin Electronics. [Citation Graph (0, 0)][DBLP ] Conf ] R. F. Voitus PBX System Test: Fast Functional Testing Without System Assembly. [Citation Graph (0, 0)][DBLP ] Conf ] Eric Sacher Component Level Fault-Isolation Techniques in a Systems Test Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Todd Westerhoff , Andre DiMino The Role of the Engineering Work Station in Test Program Development. [Citation Graph (0, 0)][DBLP ] Conf ] James T. Healy An Information Processing Software System for ATE. [Citation Graph (0, 0)][DBLP ] Conf ] M. V. Limaye , K. Rajanikanth , H. S. Jamadagni Disc Drive Testing Instrument. [Citation Graph (0, 0)][DBLP ] Conf ] Gerard FitzPatrick , David F. Peach , Richard P. Cushman An Automated Test of a Disk Product Power System Independent of the Primary Function of the Machine. [Citation Graph (0, 0)][DBLP ] Conf ] Michael J. Campbell Monitored Burn-In (A Case Study for In-Situ Testing and Reliability Studies). [Citation Graph (0, 0)][DBLP ] Conf ] A. P. van den Heuvel , N. F. Khory A Rational Basis for Setting Burn-In Yield Criteria. [Citation Graph (0, 0)][DBLP ] Conf ] Eugene R. Hnatek Thoughts on VLSI Burn-in. [Citation Graph (0, 0)][DBLP ] Conf ] Francois J. Henley An Automated Laser Prober to Determine VLSI Internal Node Logic States. [Citation Graph (0, 0)][DBLP ] Conf ] Y. Goto , K. Ozaki , T. Ishizuka , A. Ito , Y. Furukawa , T. Inagaki Electron Beam Prober for LSI Testing with 100ps Time Resolution. [Citation Graph (0, 0)][DBLP ] Conf ] P. Küollensperger , A. Krupp , M. Sturm , R. Weyl , F. Widulla , F. Wolfgang Automated Electron Beam Testing of VLSI Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen P. Denker , Judy Cobb Automatic Visual Testing: A New, Comprehensive Element of Cost-Effective PCB Testing Strategies. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen R. Teta Using a Synchronous High-Speed Sensor System to Diagnose Microprocessor Boards. [Citation Graph (0, 0)][DBLP ] Conf ] Douglas W. Raymond In-Circuit Testability Factors: Shoot With a Rifle. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen Caplow Conquering Testability Problems by Combining In-Circuit and Functional Techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Mark S. Hoffman , Joseph F. Wrinn Channel Card Architecture for Multimode Board Test Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Ramaswamy Balasubramaniam , Peretz Feder Test Strategy for a 32-Bit Microprocessor Module with Memory Management. [Citation Graph (0, 0)][DBLP ] Conf ] Terence King Advanced Test System Software Architecture Blends High Speed with User Friendliness. [Citation Graph (0, 0)][DBLP ] Conf ] S. Daniel Lee , Tom Middleton Behavioral Simulation of VLSI Test System Aids Debugging and Analysis of Test Programs. [Citation Graph (0, 0)][DBLP ] Conf ] Vin Ratford , Mike Gill Software Verification Techniques. [Citation Graph (0, 0)][DBLP ] Conf ] G. Heretz , L. T. Matlock A Real-time Executive for a Distributed Processing System. [Citation Graph (0, 0)][DBLP ] Conf ] R. E. Kizis , G. C. Wickham Multi-Port Test Data Supply System. [Citation Graph (0, 0)][DBLP ] Conf ] Steven L. Watkins , Kenny Liu , Mitchell Schrift , Robert Patrie C : An Important Tool for Test Software Development. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth D. Mandl CMOS VLSI Challenges to Test. [Citation Graph (0, 0)][DBLP ] Conf ] Yvon Savaria , Vinod K. Agarwal , Nicholas C. Rumin , Jeremiah F. Hayes A Design for Machines with Built-In Tolerance to Soft Errors. [Citation Graph (0, 0)][DBLP ] Conf ] Tonysheng Lin , Stephen Y. H. Su Functional Test Generation of Digital LSI/VLSI Systems Using Machine Symbolic Execution Technique. [Citation Graph (0, 0)][DBLP ] Conf ] Scott Davidson Fault Simulation at the Architectural Level. [Citation Graph (0, 0)][DBLP ] Conf ] Catherine Bellon , Gabriele Saucier CADOC : A System for Computer Aided Functional Test. [Citation Graph (0, 0)][DBLP ] Conf ] David M. Singer Testability Analysis of MOS VLSI Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Bill Underwood , M. Ray Mercer Correlating Testability with Fault Detection. [Citation Graph (0, 0)][DBLP ] Conf ] Franc Brglez , Philip Pownall , Robert Hum Applications of Testability Analysis: From ATPG to Critical Delay Path Tracing. [Citation Graph (0, 0)][DBLP ] Conf ] David M. Wu , Charles E. Radke , C. C. Beh Improve Yield and Quality Through Testability Analysis of VLSI Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Vishwani D. Agrawal Will Testability Analysis Replace Fault Simulation ? [Citation Graph (0, 0)][DBLP ] Conf ] J. Lawrence Carter A Vote in Favor of Fault Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Prabhakar Goel Testability Analysis will not Replace Fault Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] F. C. Wang Testability Analysis: What Role Should it Play in IC Design ? [Citation Graph (0, 0)][DBLP ] Conf ] Robert Willoner The Importance of Fault Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Steve Broyles Automating Functional Programming for Micro-Based Boards. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Hansen A Multimode Programming Strategy for VLSI Boards. [Citation Graph (0, 0)][DBLP ] Conf ] Robert G. Jacobson PAL and Logic Array In-Circuit Testing Considerations. [Citation Graph (0, 0)][DBLP ] Conf ] Herb Boulton Design Verification, Product Characterization and Production Testing of Hybrids and Printed Circuit Cards Using High-Sensitivity Thermography Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Jeff Angwin , Paul Drake , Glenn Reader The Need for Real-Time Intelligence When Testing VLSI. [Citation Graph (0, 0)][DBLP ] Conf ] D. P. Ahrens , P. J. Bednarczyk , D. L. Denburg , R. M. Robertson TPG2 : An Automatic Test Program Generator for Custom ICs. [Citation Graph (0, 0)][DBLP ] Conf ] David Giles , Gregory A. Maston Device Models : A New Methodology for a Perennial Problem. [Citation Graph (0, 0)][DBLP ] Conf ] Edward S. Hirgelt Knowledge Representation in an In-Circuit Test Program Generator. [Citation Graph (0, 0)][DBLP ] Conf ] Beau R. Wilson Jr. , Eugene R. Hnatek Problems Encountered in Developing VLSI Test Programs for COT (A Practical Outlook). [Citation Graph (0, 0)][DBLP ] Conf ] A. J. Kombol Processing of Test Data between Design and Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Axel Hunger , Axel Gaertner Functional Characterization of Microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] C. Bellon , Raoul Velazco Hardware and Software Tools for Microprocessor Functional Test. [Citation Graph (0, 0)][DBLP ] Conf ] John Kuban , John Salick Testability Features of the MC68020. [Citation Graph (0, 0)][DBLP ] Conf ] Nobuo Arai , Yoshio Yamanaka Parallel Testing of Random Logic LSIs. [Citation Graph (0, 0)][DBLP ] Conf ] M. Gerner , H. Nertinger Scan Path in CMOS Semicustom LSI Chips ? [Citation Graph (0, 0)][DBLP ] Conf ] Alfred K. Susskind A Technique for Making Asynchronous Sequential Circuits Readily Testable. [Citation Graph (0, 0)][DBLP ] Conf ] Bhargab B. Bhattacharya , Bidyut Gupta Logical Modeling of Physical Failures and Their Inherent Syndrome Testability in MOS LSI/VLSI Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Saied Bozorgui-Nesbat , Edward J. McCluskey Lower Overhead Design for Testability of Programmable Logic Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Sridhar R. Manthani , Sudhakar M. Reddy On CMOS Totally Self-Checking Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Jon Turino A Totally Universal Reset, Initialization (and) Nodal Observation Circuit. [Citation Graph (0, 0)][DBLP ] Conf ] 