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Conferences in DBLP

International Test Conference (ITC) (itc)
1989 (conf/itc/1989)

  1. Xaiolin Wang, Frederick J. Hill, Zhengkin Mi
    A Sequential Circuit Fault Simulation by Surrogate Fault Propagation. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:9-18 [Conf]
  2. Sybille Hellebrand, Hans-Joachim Wunderlich
    The Pseudo-Exhaustive Test of Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:19-27 [Conf]
  3. Michael H. Schulz, Elisabeth Auth
    Essential: An Efficient Self-Learning Test Pattern Generation Algorithm for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:28-37 [Conf]
  4. Rahul Razdan, M. Anwaruddin, Predrag G. Kovijanic, R. Ganesh, H-C. Shih
    An Interactive Sequential Test Pattern Generation System. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:38-46 [Conf]
  5. Sue Vining
    Tradeoff Decisions Made for P11149.1 Controller Design. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:47-54 [Conf]
  6. Anton T. Dahbura, M. Ümit Uyar, Chi W. Yau
    An Optimal Test Sequence for the JTAG/IEEE P1149.1 Test Access Port Controller. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:55-62 [Conf]
  7. Najmi T. Jarwala, Chi W. Yau
    A New Framework for Analyzing Test Generation and Diagnosis Algorithms for Wiring Interconnects. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:63-70 [Conf]
  8. Najmi T. Jarwala, Chi W. Yau
    A Unified Theory for Designing Optimal Test Generation and Diagnosis Algorithms for Board Interconnects. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:71-77 [Conf]
  9. Moshe Ben-Bassat, Defna Ben-Arie, Israel Beniaminy, Jonathan Cheifetz, Michael Klinger
    A Proposed Benchmark Unit for Evaluating Electronic Troubleshooting Expert Systems. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:78-86 [Conf]
  10. David K. Oka
    Transmission Line Simulation for Testing ISDN Devices. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:87-93 [Conf]
  11. Carol Pyron, Rex Sallade
    CAE Functionality for Verification of Diagnostic Programs. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:94-102 [Conf]
  12. Miroslaw Malek, Antoine N. Mourad, Mihir Pandya
    Topological Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:103-110 [Conf]
  13. Solomon Max
    Fast Accurate and Complete ADC Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:111-117 [Conf]
  14. Alice McKeon, Antony Wakeling
    Fault Diagnosis in Analogue Circuits Using AI Techniques. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:118-123 [Conf]
  15. Kohei Akiyama, Hiroshi Nishimura, Kyoji Anazawa, Akito Kishida, Nobuyuki Kasuga
    High-Resolution Analog Measurement on Mixed-Signal LSI Tester. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:124-128 [Conf]
  16. Kenneth R. Chin
    Functional Testing of Circuits and SMD Boards with Limited Nodal Access. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:129-143 [Conf]
  17. Srinivas Devadas
    Delay Test Generation for Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:144-152 [Conf]
  18. Jacques Benkoski, Andrzej J. Strojwas
    Computation of Delay Defect and Delay Fault Probabilities Using a Statistical Timing Simulator. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:153-160 [Conf]
  19. Kazumi Hatayama, Mitsuji Ikeda, Terumine Hayashi, Masahiro Takakura, Kuniaki Kishida, Shun Ishiyama
    Enhanced Delay Test Generator for High-Speed Logic LSIs. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:161-165 [Conf]
  20. Peter Hansen
    Testing Conventional Logic and Memory Clusters Using Boundary Scan Devices as Virtual ATE Channels. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:166-173 [Conf]
  21. Andy Halliday, Greg Young, Alfred L. Crouch
    Prototype Testing Simplified by Scannable Buffers and Latches. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:174-181 [Conf]
  22. W. David Ballew, Lauren M. Streb
    Board-Level Boundary-Scan: Regaining Observability with an Additional IC. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:182-189 [Conf]
  23. J. R. Birchak, H. K. Haill
    Coupling Coefficients for Signal Lines Separated by Ground Lines on PC Boards. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:190-198 [Conf]
  24. Ching-Wen Hsue
    Clock Signal Distribution Network for High-Speed Testers. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:199-207 [Conf]
  25. Norman Nadeau, Sylvie Perreault
    An Analysis of Tungsten Probes' Effect on Yield in a Production Wafer Probe Environment. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:208-215 [Conf]
  26. John L. LaMay, Dan C. Caldwell
    A Telecommunications Line Interface Test System Architecture. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:216-221 [Conf]
  27. Kenneth Lanier
    Methods of Test Waveform Synthesis for High-Speed Data Communication Devices. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:222-230 [Conf]
  28. Thomas H. Morrin
    Mixed-Mode Simulation for Time-Domain Fault Analysis. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:231-241 [Conf]
  29. Richard Absher, J. E. (Ned) Lecky
    Engineering Curricula for "Meeting the Tests of Time". [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:242-244 [Conf]
  30. Sami A. Al-Arian
    Design and Test in the Universities. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:245-245 [Conf]
  31. Donald W. Bouldin
    The Push for Test in Universities. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:246-246 [Conf]
  32. Kenneth Rose
    Design Assurance in a University Setting. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:247-248 [Conf]
  33. Melisa N. Vittrup, Glendon S. Frashure
    A Fundamental Approach to SPC Implementation. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:249-251 [Conf]
  34. Paul H. Bardell
    Calculating the Effects of Linear Dependencies in m-Sequences Used as Test Stimuli. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:252-256 [Conf]
  35. Sheldon B. Akers, Winston Jansz
    Test Set Embedding in a Built-In Self-Test Environment. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:257-263 [Conf]
  36. Franc Brglez, Gershon Kedem, Clay Gloster
    Hardware-Based Weighted Random Pattern Generation for Boundary Scan. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:264-274 [Conf]
  37. David L. Landis
    A Self-Test System Architecture for Reconfigurable WSI. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:275-282 [Conf]
  38. Yoichi Tsubuku, Takao Nishida, Hiroshi Shiga, Ken Ohga, Hirohisa Nishine, Mamoru Kaneko
    Main Frame Diagnosis Support System. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:283-289 [Conf]
  39. Robert F. Lusch, Endre F. Sarkany
    Techniques for Improved Testability in the IBM ES/9370 System. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:290-294 [Conf]
  40. James Westover
    Practical Test Strategies for Users of 100 PPM ICs. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:295-303 [Conf]
  41. Ron Santella
    The Role of Test in a "Continuous Improvement" Environment. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:304-308 [Conf]
  42. Kenneth R. Stuchlik
    IC Characteristic Matching for Optimal System Performance. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:309-315 [Conf]
  43. Rainer Kraus, Oskar Kowarik, Kurt Hoffmann, Dieter Oberle
    Design for Test of Mbit DRAMs. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:316-321 [Conf]
  44. Yoshio Matsuda, Kazutami Arimoto, Masaki Tsukude, Tsukasa Oishi, Kazuyasu Fujishima
    A New Array Architecture for Parallel Testing in VLSI Memories. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:322-326 [Conf]
  45. Manoj Franklin, Kewal K. Saluja, Kozo Kinoshita
    Design of a BIST RAM with Row/Column Pattern Sensitive Fault Detection Capability. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:327-336 [Conf]
  46. C. C. Chuang, Anup K. Gupta
    The Analysis of Parallel BIST by the Combined Markov Chain (CMC) Model. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:337-343 [Conf]
  47. Dhiren Xavier, Robert C. Aitken, André Ivanov, Vinod K. Agarwal
    : Experiments on Aliasing in Signature Analysis Registers. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:344-354 [Conf]
  48. Régis Leveugle, Gabriele Saucier
    Optimized Synthesis of Dedicated Controllers with Concurrent Checking Capabilities. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:355-363 [Conf]
  49. Raghu V. Hudli, Sharad C. Seth
    Testability Analysis of Synchronous Sequential Circuits Based on Structural Data. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:364-372 [Conf]
  50. C. H. Chen, Premachandran R. Menon
    An Approach to Functional Level Testability Analysis. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:373-380 [Conf]
  51. Kurt H. Thearling, Jacob A. Abraham
    An Easily Computed Functional Level Testability Measure. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:381-390 [Conf]
  52. Mattia Lanzoni, Piero Olivo, Bruno Riccò
    A Testing Technique to Characterize E^2PROM's Aging and Endurance. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:391-396 [Conf]
  53. Eugene R. Hnatek, Billy R. Livesay
    Quality Issues of High Pin Count Fine Pitch VLSI Packages. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:397-422 [Conf]
  54. Jerry M. Soden, R. Keith Treece, Michael R. Taylor, Charles F. Hawkins
    CMOS IC Stuck-Open Fault Electrical Effects and Design Considerations. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:423-430 [Conf]
  55. W. Malzfeldt, W. Mohr, H.-D. Oberle, K. Kodalle
    Fast Automatic Failbit Analysis for DRAMs. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:431-438 [Conf]
  56. Jacob Savir, William H. McAnney, Salvatore R. Vecchio
    Testing for Coupled Cells in Random-Access Memories. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:439-451 [Conf]
  57. Kenrick Koo, Steve Ramseyer, Al Tejeda
    A Testing Methodology for New-Generation Specialty Memory Devices. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:452-460 [Conf]
  58. P. N. Anirudhan, Premachandran R. Menon
    Symbolic Test Generation for Hierarchically Modeled Digital Systems. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:461-469 [Conf]
  59. Thomas M. Sarfert, Remo G. Markgraf, Erwin Trischler, Michael H. Schulz
    Hierarchical Test Pattern Generation Based on High-Level Primitives. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:470-479 [Conf]
  60. John D. Calhoun, Franc Brglez
    A Framework and Method for Hierarchical Test Generation. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:480-490 [Conf]
  61. Srinivas Devadas, Hi-Keung Tony Ma, A. Richard Newton
    Redundancies and Don't Cares in Sequential Logic Synthesis. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:491-500 [Conf]
  62. Daniel Brand, Vijay S. Iyengar
    Synthesis of Pseudo-Random Pattern Testable Designs. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:501-508 [Conf]
  63. Sreejit Chakravarty
    A Testable Realization of CMOS Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:509-518 [Conf]
  64. David Grabel
    Data Verification: A Prerequisite for Heuristic Diagnostics. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:519-526 [Conf]
  65. Wojciech Maly, Samir B. Naik
    Process Monitoring Oriented IC Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:527-532 [Conf]
  66. J. Patterson
    Improved System Design Through Proper Nesting of Test Levels. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:533-542 [Conf]
  67. Gary J. Lesmeister
    The Linear Array Systolic Tester (LAST). [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:543-549 [Conf]
  68. Robert W. Bassett, Barry J. Butkus, Stephen L. Dingle, Marc R. Faucher, Pamela S. Gillis, Jeannie H. Panner, John G. Petrovick, Donald L. Wheater
    Low Cost Testing of High Density Logic Components. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:550-557 [Conf]
  69. Shuji Kikuchi, Yoshihiko Hayashi, Takashi Matsumoto, Ryozou Yoshino, Ryuichi Takagi
    A 250 MHz Shared-Resource VLSI Test System with High Pin Count and Memory Test Capability. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:558-566 [Conf]
  70. Bruce A. Webster
    An Integrated Analog Test Simulation Environment. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:567-571 [Conf]
  71. Wayne D. Dettloff, Melodie D. Tebbs
    The Omnitest System: A No-Generate, No-Compile, Interactive Test Methodology. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:572-576 [Conf]
  72. Eric Paradis, David Stannard
    SASPL: A Test Program Productivity Analysis Tool. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:577-584 [Conf]
  73. Eric Rosenfeld
    Issues for Mixed-Signal CAD-Tester Interface. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:585-590 [Conf]
  74. Michael W. Salter, Kemon P. Taschioglou
    Mainstream ATE: To Reduce LSI and VLSI Test Cost. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:591-596 [Conf]
  75. Sheila O'Keefe
    Reconfigurable Resource Architecture Improves VLSI Tester Utilization. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:597-604 [Conf]
  76. J. Stephen Pabst
    Cost Impacts of Automatic Test Equipment Purchase Decisions. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:605-610 [Conf]
  77. William R. Mann
    R96MFX Test Strategy. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:611-614 [Conf]
  78. Wallace Harwood, Mark McDermott
    Testability Features of the MC68332 Modular Microcontroller. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:615-623 [Conf]
  79. Y. Nozuyama, A. Nishimura, J. Iwamura
    Implementation and Evaluation of Microinstruction-Controlled Self Test Using a Masked Microinstruction Scheme. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:624-632 [Conf]
  80. Marcel Jacomet
    FANTESTIC: Towards a Powerful Fault Analysis and Test Pattern Generator for Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:633-642 [Conf]
  81. F. Camerik, P. A. J. Dirks, Jochen A. G. Jess
    Qualification and Quantification of Process-Induced Product-Related Defects. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:643-652 [Conf]
  82. Scott F. Midkiff, Wern-Yan Koe
    Test Effectiveness Metrics and CMOS Faults. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:653-659 [Conf]
  83. Frans P. M. Beenker, Rob Dekker, Rudi Stans, Max Van der Star
    A Testability Strategy for Silicon Compilers. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:660-669 [Conf]
  84. Yinan N. Shen, Fabrizio Lombardi
    Location and Identification for Single and Multiple Faults in Testable Redundant PLAs for Yield Enhancement. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:670-678 [Conf]
  85. Chin-Long Wey
    Fault Location in Repairable Programmable Logic Arrays. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:679-685 [Conf]
  86. Frank J. Langley, Ronald R. Boatright, Laurence Crosby
    Composite Electro-Optical Testing of Surface-Mount Device Boards-One Manufacturer's Experience. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:686-691 [Conf]
  87. Michel Crastes de Paulet, M. Karam, Gabriele Saucier
    Testability Expertise and Test Planning from High-Level Specifications. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:692-699 [Conf]
  88. Abu S. M. Hassan, Vinod K. Agarwal, Janusz Rajski, Benoit Nadeau-Dostie
    Testing of Glue Logic Interconnects Using Boundary Scan Architecture. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:700-711 [Conf]
  89. Bill Underwood, Jack Ferguson
    The Parallel-Test-Detect Fault Simulation Algorithm. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:712-717 [Conf]
  90. Srinivas Patil, Prithviraj Banerjee
    Fault Partitioning Issues in an Integrated Parallel Test Generation/Fault Simulation Environment. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:718-726 [Conf]
  91. Prathima Agrawal, Vishwani D. Agrawal, Kwang-Ting Cheng, R. Tutundjian
    Fault Simulation in a Pipelined Multiprocessor System. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:727-734 [Conf]
  92. Richard Illman, Steve Clarke
    Built-In Self-Test of the Macrolan Chip. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:735-744 [Conf]
  93. Yvon Savaria, Bruno Laguë, Bozena Kaminska
    A Pragmatic Approach to the Design of Self-Testing Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:745-754 [Conf]
  94. Samuel H. Duncan
    A BIST Design Methodology Experiment. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:755-762 [Conf]
  95. Jay M. Stepleton
    A New System Architecture for a Combined In-Circuit/Functional Tester. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:763-772 [Conf]
  96. Barry A. Alcorn
    Writing Correct and Usable Specifications for Board Test: A Case Study. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:773-786 [Conf]
  97. Phillip N. King
    Flexible, High-Performance Pin Electronics Implementation. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:787-794 [Conf]
  98. Tracy Larrabee
    Efficient Generation of Test Patterns Using Boolean Difference. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:795-802 [Conf]
  99. Hyoung B. Min, William A. Rogers
    Search Strategy Switching: An Alternative to Increased Backtracking. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:803-811 [Conf]
  100. Charles E. Stroud, Ahmed E. Barbour
    Design for Testability and Test Generation for Static Redundancy System Level Fault-Tolerant Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:812-818 [Conf]
  101. Arif Samad, Martin Bell
    Automating ASIC Design-for-Testability: The VLSI Test Assistant. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:819-828 [Conf]
  102. Arthur E. Downey
    "ATG" Test Generation Software. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:829-837 [Conf]
  103. Jens Leenstra, Lambert Spaanenburg
    On the Design and Test of Asynchronous Macros Embedded in Synchronous Systems. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:838-845 [Conf]
  104. Christopher W. Branson
    A High Performance, 10-Volt Integrated Pin Electronics Driver. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:846-853 [Conf]
  105. Stephen W. Bryson
    Custom Pin Electronics for VLSI Automatic Test Equipment. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:854-859 [Conf]
  106. Steve Barton
    Characterization of High-Speed (Above 50 MHz) Devices Using Advance ATE-Techniques, Results and Device Problems. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:860-868 [Conf]
  107. Marc E. Levitt, Jacob A. Abraham
    The Economics of Scan Design. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:869-874 [Conf]
  108. Chryssa Dislis, I. D. Dear, J. R. Miles, S. C. Lau, Anthony P. Ambler
    Cost Analysis of Test Method Environments. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:875-883 [Conf]
  109. Bozena Kaminska, Yvon Savaria
    Design-for-Testability Using Test Design Yield and Decision Theory. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:884-892 [Conf]
  110. Don Allingham, Pat Bashford, Mike Peters, Dean Vendl
    DesignTest^TM: A Solution to the Problems of ASIC Verification. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:893-902 [Conf]
  111. George Swan, Yatin Trivedi, David J. Wharton
    CrossCheck: A Practical Solution for ASIC Testability. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:903-908 [Conf]
  112. Kazuhiro Sakashita, Takeshi Hashizume, Takashi Ohya, Isao Takimoto, Shuichi Kato
    Cell-Based Test Design Method. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:909-916 [Conf]
  113. Yasuo Tokunaga, Jürgen Frosien
    High Performance Electron Beam Tester for Voltage Measurement on Unpassivated and Passivated Devices. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:917-922 [Conf]
  114. Christopher G. Talbot, Suresh Rajan
    A Logic Analyzer Tool That Cuts E-Beam Prober Acquisition Times. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:923- [Conf]
  115. D. J. Hall, A. W. Sloman, G. S. Plows
    Rapid Data Acquisition for E-Beam Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:928- [Conf]
  116. Michele Favalli, Piero Olivo, Maurizio Damiani, Bruno Riccò
    CMOS Design for Improved IC Testability. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:934- [Conf]
  117. John C. Chan, Baxter F. Womack
    Diagnostics Based on Fault Signature. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:935- [Conf]
  118. Piero Olivo, Maurizio Damiani, Bruno Riccò
    On the Design of Multiple-Input Shift-Registers for Signature Analysis Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:936- [Conf]
  119. R. Ernst, S. Sutarwala, J.-Y. Jou
    TSG: A Test System Generator for Debugging and Regression Test of High-Level Behavioral Synthesis Tools. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:937- [Conf]
  120. David Haupert, Fu-Gin Chen, David Lee
    VLSI Package Reliability Risk Due to Accelerated Environmental Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:938- [Conf]
NOTICE1
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NOTICE2
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