Conferences in DBLP
Luis T. Burke Jr. Maintaing Quality, Poductivity and Profit in a Changing Bell System. [Citation Graph (0, 0)][DBLP ] Conf ] Melissa E. Broussard Higher Yields, Lower Costs. [Citation Graph (0, 0)][DBLP ] Conf ] Matthew V. Mahoney Closing the Loop: An Expanding Role for ATE in Semiconductor Manufacturing. [Citation Graph (0, 0)][DBLP ] Conf ] Pete S. Bottorff Fault Modeling and Test Effectiveness Evaluation for VLSI Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Chi-Chang Liaw , Stephen Y. H. Su A New Fault Model and Testing Technique for CMOS Devices. [Citation Graph (0, 0)][DBLP ] Conf ] C. C. Beh , K. H. Arya , Charles E. Radke , E. Kofi Vida-Torku Do Stuck Fault Models Reflect Manufacturing Defects? [Citation Graph (0, 0)][DBLP ] Conf ] Alexander Miczo Fault Modelling for Functional Primitives. [Citation Graph (0, 0)][DBLP ] Conf ] Mark G. Karpovsky Universal Tests Detecting Input/Output Faults in Almost All Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Erik DeBenedictis , Charles L. Seitz Testing and Structured Design. [Citation Graph (0, 0)][DBLP ] Conf ] Sumit DasGupta , Prabhakar Goel , Ron G. Walther , Tom W. Williams A Variation of LSSD and Its Implications on Design and Test Pattern Generation in VLSI. [Citation Graph (0, 0)][DBLP ] Conf ] K. S. Ramanatha , Nripendra N. Biswas A Design for Complete Testability of Programmable Logic Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] William C. Carter Signature Testing with Guaranteed Bounds for Fault Coverage. [Citation Graph (0, 0)][DBLP ] Conf ] Prabhakar Goel , M. T. McMahon Electronic Chip-In-Place Test. [Citation Graph (0, 0)][DBLP ] Conf ] Joel M. Schoen Test Equipment and Methods I. [Citation Graph (0, 0)][DBLP ] Conf ] William J. Bowhers Filtering Methods for Fast Ultra-Low Distortion Measurements. [Citation Graph (0, 0)][DBLP ] Conf ] Yasutoshi Otani , Eiji Ishiwa , Nobuo Arai , Yoshio Yamanaka A Pursuit of Superior Cost-Per-Performance in General-Purpose Linear IC Test System. [Citation Graph (0, 0)][DBLP ] Conf ] David C. Cheng , Alexander A. Grillo Test Considerations for Components with Redundant Elements. [Citation Graph (0, 0)][DBLP ] Conf ] Kennteth F. Coop Automated Test Instrumentation for Low-Current Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Bradford Robbins , David K. Oka Using Analog Signature Analysis in Speech Synthesis Device Testing. [Citation Graph (0, 0)][DBLP ] Conf ] K. S. Bhaskar Signature Analysis: Yet Another Perspective. [Citation Graph (0, 0)][DBLP ] Conf ] John Turino Professional Aspects of Test Engineering. [Citation Graph (0, 0)][DBLP ] Conf ] Douglas Greenwood Increasing Test Engineering Effectivness. [Citation Graph (0, 0)][DBLP ] Conf ] James L. Kroening Professional Aspects of Test Engineering. [Citation Graph (0, 0)][DBLP ] Conf ] Harold Levin ATPG and Simulation Systems : The State of the Art. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth R. Bowden Design Goals and Implementation Techniques for Time-Based Digital Simulation and Hazard Detection. [Citation Graph (0, 0)][DBLP ] Conf ] David Giles , Charles Berking , Kenneth Wacks Integrated Functional/Structural Timing for Digital Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Kyuhik Son , James Y. O. Fong Automatic Behavioral Test Generation. [Citation Graph (0, 0)][DBLP ] Conf ] John P. Barlow A New Software Tool for Detecting Problems Caused by Inductively-Generated Switching Noise. [Citation Graph (0, 0)][DBLP ] Conf ] James Y. O. Fong On Functional Controllability and Observability Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Charles Hinchcliff Simplified Microprocessor Test Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Richard M. Sedmak Self-Test Chip to System Level Approaches. [Citation Graph (0, 0)][DBLP ] Conf ] Edward J. McCluskey Built-In Verification Test. [Citation Graph (0, 0)][DBLP ] Conf ] Thirumalai Sridhar , Satish M. Thatte Concurrent Checking of Program Flow in VLSI Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Paul H. Bardell , William H. McAnney Self-Testing of Multichip Logic Modules. [Citation Graph (0, 0)][DBLP ] Conf ] J. Abadir , Yves Deswarte Run-Time Program for Self-Checking Single Board Computer. [Citation Graph (0, 0)][DBLP ] Conf ] Patrick P. Fasang A Fault Detection and Isolation Technique for Microcomputers. [Citation Graph (0, 0)][DBLP ] Conf ] D. J. Graham Memory Test : An International Art. [Citation Graph (0, 0)][DBLP ] Conf ] Eugene R. Hnatek , Beau R. Wilson Jr. An Evaluation of the 2816 EEPROM. [Citation Graph (0, 0)][DBLP ] Conf ] Marian Marinescu Simple and Efficient Algorithms for Functional RAM Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Y. Hayasaka , K. Shimotori , K. Okada Testing System for Redundant Memory. [Citation Graph (0, 0)][DBLP ] Conf ] T. Tada , T. Kobayashi , K. Okada , Y. Kuramitsu Testing of Sense Amplifier in Dynamic Memory. [Citation Graph (0, 0)][DBLP ] Conf ] Nik Kirschner An Interactive Descrambler Program for RAMs with Redundancy. [Citation Graph (0, 0)][DBLP ] Conf ] Charles E. Shalvoy Testing during Burn-In: Economical Alternative for Testing Memories. [Citation Graph (0, 0)][DBLP ] Conf ] Bill Hedrick Quality and Reliability. [Citation Graph (0, 0)][DBLP ] Conf ] Joel P. LeBlanc Jr. An STL Gate Array Reliability Test Bar. [Citation Graph (0, 0)][DBLP ] Conf ] Louis J. Sobotka The Effects of Backdriving Digital Integrated Circuits during In-Circuit Testing. [Citation Graph (0, 0)][DBLP ] Conf ] G. Eugene Gottlieb An Accelerated Testing Technique for Plastic Package Devices Using a Sequential Combination of Pressure Cooker and 85/85 (PCTH). [Citation Graph (0, 0)][DBLP ] Conf ] Willis J. Horth , Frederick G. Hall , Robert G. Hillman Microelectronic Device Electrical Test Implementation Problems on Automated Test Equipment. [Citation Graph (0, 0)][DBLP ] Conf ] F. G. Cockerill Quality Control for Production Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Kemon P. Taschioglou To Measure Quality in the Manufacturing of Printed Circuit Boards. [Citation Graph (0, 0)][DBLP ] Conf ] R. Burgess , E. Pignetti , J. Pitti MCM Data Analysis Tracking System. [Citation Graph (0, 0)][DBLP ] Conf ] Wayne Bryant , Charles Furry , Jim Hahn Benefits of ATE and Host Computer Networking. [Citation Graph (0, 0)][DBLP ] Conf ] Bruce G. MacAloney , Paul Littlejohn Manufacturing Productivity: Automated vs. Manual Test-Data-Management Systems. [Citation Graph (0, 0)][DBLP ] Conf ] David W. Malas , Stephen C. Hagan Test Data Automation: An ATE Distributed Processing Application in a Multi-Vendor Environment. [Citation Graph (0, 0)][DBLP ] Conf ] W. L. Goldie , P. F. Macready An Automatic Test Equipment Database System Used in the Generation and Analysis of Fault Statistics at the Printed Circuit Board Level. [Citation Graph (0, 0)][DBLP ] Conf ] William C. Berg , Robert D. Hess COMET: A Testability Analysis and Design Modification Package. [Citation Graph (0, 0)][DBLP ] Conf ] Eugen I. Muehldorf , Thomas W. Williams Analysis of the Switching Behavior of Combinatorial Logic Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Vishwani D. Agrawal , M. Ray Mercer Testability Measures : What Do They Tell Us ? [Citation Graph (0, 0)][DBLP ] Conf ] Ion M. Ratiu , Alberto L. Sangiovanni-Vincentelli , Donald O. Pederson VICTOR : A Fast VLSI Testability Analysis Program. [Citation Graph (0, 0)][DBLP ] Conf ] Richard A. Albright System Test. [Citation Graph (0, 0)][DBLP ] Conf ] John A. Masciola , Mark S. Lucas A Technique for Testing Large Distributed Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Ken Fedraw 9826A Computer Burn-In Program. [Citation Graph (0, 0)][DBLP ] Conf ] Donald Komonytsky LSI Self-Test Using Level Sensitive Scan Design and Signature Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth R. Willey Systems Testing Why ? [Citation Graph (0, 0)][DBLP ] Conf ] David C. Cheng A Precision Measurement Technique for High Frequency Repetitive Signals. [Citation Graph (0, 0)][DBLP ] Conf ] K. Uchida Testing the Dynamic Performance of High-Speed A/D Converters. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen W. Bryson Testing an Audio Spectrum Analyzer for Speech Recognition Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Tim Higgins Digital Signal Processing for Production Testing of Analog LSI Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Bell Liu Soft Failure Detection and Correction in Microprocessor Characterization. [Citation Graph (0, 0)][DBLP ] Conf ] Masood Namjoo Techniques for Concurrent Testing of VLSI Processor Operation. [Citation Graph (0, 0)][DBLP ] Conf ] Vijay S. Iyengar , Larry L. Kinney Concurrent Testing of Flow of Control in Simple Microprogrammed Control Units. [Citation Graph (0, 0)][DBLP ] Conf ] Sunil Nanda , Sudhakar M. Reddy Design of Easily Testable Microprocessors : A Case Study. [Citation Graph (0, 0)][DBLP ] Conf ] Satish M. Thatte , D. S. Ho , H.-T. Yuan , Thirumalai Sridhar , Theo J. Powell An Architecture for Testable VLSI Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Roger Simpson Test Software. [Citation Graph (0, 0)][DBLP ] Conf ] Antony K. Stevens Structured Programming and the I.C. Test Engineer. [Citation Graph (0, 0)][DBLP ] Conf ] I. M. Watson , John A. Newkirk , Robert G. Mathews , D. B. Boyle ICTEST : A Unified System for Functional Testing and Simulation of Digital ICs. [Citation Graph (0, 0)][DBLP ] Conf ] Jaques Couesnon , Michel Parot A Coherent and Efficient Approach to LSI Modeling and Testing for Integrated Circuit Users. [Citation Graph (0, 0)][DBLP ] Conf ] Richard C. Mahoney A Common Pascal Test Language: Reality or Pipedream. [Citation Graph (0, 0)][DBLP ] Conf ] Iqbal Syed , Nicole Rose Automated Generation of Device Test Software. [Citation Graph (0, 0)][DBLP ] Conf ] Mike Schell , Mike Sigler Automated Analysis of Static RAM Failures. [Citation Graph (0, 0)][DBLP ] Conf ] Reymon Oberly Board Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Eric H. Millham Board Test Session I. [Citation Graph (0, 0)][DBLP ] Conf ] Matthew L. Fichtenbaum Faults Which Challenge the In-Circuit Tester: Some Examples and Some Solutions. [Citation Graph (0, 0)][DBLP ] Conf ] T. Jackson , P. Vais , K. Schwerbrock A New Approach to On-Board Microprocessor-Based Self-Test. [Citation Graph (0, 0)][DBLP ] Conf ] Herold Levine , Charles Berking , Alan Blair , Kenneth R. Bowden , Peter deBruyn Kops , David Giles , David Ruhoff , Kenneth Wacks Design of a New Test Generation System for Performance Testing of LSI Digital Printed Circuit Boards. [Citation Graph (0, 0)][DBLP ] Conf ] Dennis Hebert , Jack H. Arabian Implications of the Technique for Dynamic High Speed Functional Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Gregory Illes Test System Remote Program Management. [Citation Graph (0, 0)][DBLP ] Conf ] Donald Stewart Improving the Effectiveness of Board Test Programmers. [Citation Graph (0, 0)][DBLP ] Conf ] William K. Jones Managing Your Test Cost for the 80's. [Citation Graph (0, 0)][DBLP ] Conf ] G. A. Perone , R. S. Maljatt , J. P. Kain , W. I. Goodheim A Closer Look at Testing Costs. [Citation Graph (0, 0)][DBLP ] Conf ] Ming-Guan Lin , Kenneth Rose Applying Test Theory to VLSI Testing. [Citation Graph (0, 0)][DBLP ] Conf ] William S. Richardson Test Pattern Portability for Microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Neal H. MacDonald , Gordon B. Neish An Algorithmic Approach to the Testing of a Wafer Scale Integrated (WSI) Circuit. [Citation Graph (0, 0)][DBLP ] Conf ] Roderick H. Macmillan , M. R. Bentley , An Efficient Test Vector Generation and Reduction Method for an LSI Digital Filter Circuit Using an Adaptive Search Technique. [Citation Graph (0, 0)][DBLP ] Conf ] Richard B. Craven Test Equipment and Methods II. [Citation Graph (0, 0)][DBLP ] Conf ] Brian C. Crosby ECL Board Testing: An In-Circuit Point of View. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas A. Senna Calculating VOH for LSI 10K ECL. [Citation Graph (0, 0)][DBLP ] Conf ] James Seaton , Jeffrey Axelbank Designing a High-Speed Vector Bust to Meet the Requirements of Analog LSI Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Junji Nishiura , Toshio Maruyama , Hiromi Maruyama , Shinpei Kamata Testing VLSI Microprocessor with New Functional Capability. [Citation Graph (0, 0)][DBLP ] Conf ] K. Thangamuthu , M. Macari , S. Cohen Automated Contactless Digital Test System for VLSI. [Citation Graph (0, 0)][DBLP ] Conf ] R. Oberly Board Testing II. [Citation Graph (0, 0)][DBLP ] Conf ] James J. Faran Jr. Methods of Assignment of Nodes to Pins for Multiplexed Testers. [Citation Graph (0, 0)][DBLP ] Conf ] Hookuong Wong , David Florcik A Tester-Independent Automated Test Preparation Process for Loaded Boards. [Citation Graph (0, 0)][DBLP ] Conf ] Thirumalai Sridhar , D. S. Ho , Theo J. Powell , Satish M. Thatte Analysis and Simulation of Parallel Signature Analyzers. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Solecky , Frank C. Hsu Board Diagnosis: A Current Assessment and Direction for Future Improvement. [Citation Graph (0, 0)][DBLP ] Conf ] 