Conferences in DBLP
Robert C. Kroeger Testability Emphasis in the General Electric A/VLSI Program. [Citation Graph (0, 0)][DBLP ] Conf ] Robert F. Miller , Kenneth W. Doversberger Testing Trends in Automotive Electronics. [Citation Graph (0, 0)][DBLP ] Conf ] J. A. G. Shearsmith The Effect of the Factory of the Future on Society. [Citation Graph (0, 0)][DBLP ] Conf ] Robert Albrow Test Pattern Compaction in VLSI Testers. [Citation Graph (0, 0)][DBLP ] Conf ] Steven Ladd Implementing a Self-Managed Test Vector Memory with One Million Elements. [Citation Graph (0, 0)][DBLP ] Conf ] Y. Kuramitsu , Y. Gamo A Suitable Test System for Gate Array. [Citation Graph (0, 0)][DBLP ] Conf ] David R. Emberson A Tightly Coupled Multiprocessor for VLSI Testing. [Citation Graph (0, 0)][DBLP ] Conf ] John R. Schinabeck System Architecture for Optimum DC Parameter Measurements. [Citation Graph (0, 0)][DBLP ] Conf ] Arthur L. Downey Test Program Optimization Techniques for a High Speed Performance VLSI Tester. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Hansen New Techniques for Manufacturing Test and Diagnosis of LSSD Boards. [Citation Graph (0, 0)][DBLP ] Conf ] John A. Masciola , Gary Roberts Testing Microprocessor Boards and Systems: A New Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Brian C. Crosby FAST Technology In-Circuit Testing Considerations. [Citation Graph (0, 0)][DBLP ] Conf ] Steven L. Bates High-Speed In-Circuit Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Matt Snook , Bob Illick A New Hardware Architecture for Digital In-Circuit Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Richard N. Barnes Fixturing for Surface-Mounted Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Edward J. McCluskey , David J. Lu Recurrent Test Patterns. [Citation Graph (0, 0)][DBLP ] Conf ] Kewal K. Saluja , Mark G. Karpovsky Testing Computer Hardware through Data Compression in Space and Time. [Citation Graph (0, 0)][DBLP ] Conf ] Zeev Barzilai , Barry K. Rosen Comparison of AC Self-Testing Procedures. [Citation Graph (0, 0)][DBLP ] Conf ] Jacob Savir , Paul H. Bardell On Random Pattern Test Length. [Citation Graph (0, 0)][DBLP ] Conf ] Glenn A. Kramer Employing Massive Parallelism in Digital ATPG Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] J. F. McDonald , C. Benmehrez Test Set Reduction Using the Subscripted D-Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] David Florcik , David Low Simulation Pattern Capturing System for Design Verification Using a Dynamic High Speed Functional Tester (DHSFT). [Citation Graph (0, 0)][DBLP ] Conf ] Michael G. Lamoureux , Vinod K. Agarwal Non-Stuck-At Fault Detection in nMOS Circuits by Region Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Miron Abramovici , Premachandran R. Menon A Practical Approach to Fault Simulation and Test Generation for Bridging Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Alexander Miczo The Sequential ATPG: A Theoretical Limit. [Citation Graph (0, 0)][DBLP ] Conf ] W. Boggs Integration into the CAD Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Steve Bisset The Develpment of a Tester-Per-Pin VLSI Test System Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] M. Ray Mercer Testing Issues at the University of Texas. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth Rose Test Technology in the University. [Citation Graph (0, 0)][DBLP ] Conf ] Jacob A. Abraham Incorporating Test Technology into an Undergraduate Curriculum. [Citation Graph (0, 0)][DBLP ] Conf ] Al A. Tuszynski Diversified Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Edward J. McCluskey Teaching Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Mark R. Barber Subnanosecond Timing Measurements on MOS Devices Using Modern VLSI Test Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Lisa Deerr Automatic Calibration for a VLSI Test System. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Catalano , Richard K. Feldman , Roberto Krutiansky , Richard Swan Individual Signal Path Calibration for Maximum Timing Accuracy in a High Pincount VLSI Test System. [Citation Graph (0, 0)][DBLP ] Conf ] Burnell G. West Attainable Accuracy of Autocalibrating VLSI Test Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Richard F. Herlein Optimizing the Timing Architecture of a Digital LSI Test System. [Citation Graph (0, 0)][DBLP ] Conf ] John C. Howland , Pat T. Harding Estimating the Required Size of an Automated Test and Repair System from Subassembly Volume and Failure Information. [Citation Graph (0, 0)][DBLP ] Conf ] R. Wade Williams Consideration While Introducing a Test Data Management System to the Factory Floor. [Citation Graph (0, 0)][DBLP ] Conf ] Jack H. Arabian User's Requirements for Automated Handling in Computer Manufacturing and Board Test. [Citation Graph (0, 0)][DBLP ] Conf ] Robert W. Atherton , David M. Campbell Use of In-Fab Parametric Testing for Process Control of Semiconductor Manufacturing. [Citation Graph (0, 0)][DBLP ] Conf ] Donald S. Cleverley The Role of Testing in Achieving Zero Defects. [Citation Graph (0, 0)][DBLP ] Conf ] Gerry Schmid Software Solutions Enhance ATE Networking Capabilities. [Citation Graph (0, 0)][DBLP ] Conf ] Alan F. Murray , Peter B. Denyer , David S. Renshaw Self-Testing in Bit Serial VLSI Parts: High Coverage at Low Cost. [Citation Graph (0, 0)][DBLP ] Conf ] Yacoub M. El-Ziq , Hamid H. Butt A Mixed-Mode Built-In Self-Test Technique Using Scan Path and Signature Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Michael A. Schuette , John Paul Shen On-Line Self-Monitoring Using Signatured Instruction Streams. [Citation Graph (0, 0)][DBLP ] Conf ] Franco Motika , John A. Waicukauski , Edward B. Eichelberger , Eric Lindbloom An LSSD Pseudo Random Pattern Test System. [Citation Graph (0, 0)][DBLP ] Conf ] W. S. Blackley , M. A. Jack , J. R. Jordan A Digital Polarity Correlator Featuring Built-In Self Test and Self Repair Mechanisms. [Citation Graph (0, 0)][DBLP ] Conf ] John R. Kuban , Bill Bruce The MC6804P2 Built-In Self-Test. [Citation Graph (0, 0)][DBLP ] Conf ] David J. Wharton The HITEST Test Generation System Overview. [Citation Graph (0, 0)][DBLP ] Conf ] Gordon D. Robinson HITEST : Intelligent Test Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Colin Maunder HITEST Test Generation System Interfaces. [Citation Graph (0, 0)][DBLP ] Conf ] Mats Johansson The GENESYS-Algorithm for ATPG without Fault Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Chantal Robach , Ch. Malecha , G. Michel Computer Aided Testability Evaluation and Test Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Masato Kawai , H. Shibano , S. Funatsu , S. Kato , T. Kurobe , K. Ookawa , T. Sasaki A High Level Test Pattern Generation Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Charles McMinn The Impact of a VLSI Test System on the Test Throughput Equation. [Citation Graph (0, 0)][DBLP ] Conf ] Takeshi Shigematsu , Takashi Sakamoto , Yoshio Yamanaka A New Approach to DC Parameter Measurement in the Day of VLSI. [Citation Graph (0, 0)][DBLP ] Conf ] R. Y. Li , S. C. Diehl , S. Harrison Power Supply Noise Testing of VLSI Chips. [Citation Graph (0, 0)][DBLP ] Conf ] Shigeru Sugamori , Kunio Takeuchi , Hiromi Maruyama , Shinpei Kamata High-Fidelity Device Tester Interface. [Citation Graph (0, 0)][DBLP ] Conf ] Phil Brothers New Directions for VLSI Test Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Mark A. Myers An Analysis of the Cost and Quality Impact of LSI/VLSI Technology on PCB Test Strategies. [Citation Graph (0, 0)][DBLP ] Conf ] Robert E. Huston An Analysis of ATE Testing Costs. [Citation Graph (0, 0)][DBLP ] Conf ] Paul N. Manikas , Stephen G. Eichenlaub Reducing the Cost of Quality through Test Data Management. [Citation Graph (0, 0)][DBLP ] Conf ] Robert W. Atherton , Alfred H. Miller Jr. , Judith E. Dayhoff Operations Management and Analysis in the Management of Electronic Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Andrea S. LaPaugh , Richard J. Lipton Total Fault Testing Using the Bipartite Transformation. [Citation Graph (0, 0)][DBLP ] Conf ] Jon G. Kuhl , Sudhakar M. Reddy On Testable Design for CMOS Logic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Bhargab B. Bhattacharya , Bidyut Gupta Syndrome Testable Design of Combinational Networks for Detecting Stuck-At and Bridging Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Teruhiko Yamada Syndrome-Testable Design of Programmable Logic Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Marc R. Faucher Pattern Recognition of Bit Fail Maps. [Citation Graph (0, 0)][DBLP ] Conf ] Masaaki Arao , Takao Tadokoro , Hiromi Maruyama , Shinpei Kamata Tester Correlation Problem in Memory Testers Used in Production Lines. [Citation Graph (0, 0)][DBLP ] Conf ] Donald M. Stewart Production Test and Repair of 256K Dynamic RAMS with Redundancy. [Citation Graph (0, 0)][DBLP ] Conf ] Robert L. Hickling Tester Independent Problem Representation and Tester Dependent Program Generation. [Citation Graph (0, 0)][DBLP ] Conf ] George F. Sprott An Adaptable Emulation Support Environment for Microprocessor Systems. [Citation Graph (0, 0)][DBLP ] Conf ] L. M. Zobniw Designing the VLSI Device-to-Board Test Ukraine Translator. [Citation Graph (0, 0)][DBLP ] Conf ] Mark P. Skrzynski , Neal Shea An ETHERNET Based Solution to ATE Networking. [Citation Graph (0, 0)][DBLP ] Conf ] Takuji Okamoto , Hiroyuki Shibata , Kozo Kinoshita Design of High-Level Test Language for Digital LSI. [Citation Graph (0, 0)][DBLP ] Conf ] David C. Snyder , Elaina S. Stokes , Richard C. Mahoney Inside a Modern Test Language Compiler. [Citation Graph (0, 0)][DBLP ] Conf ] Brian J. Sargent Implementation of a Memory-Emulation Diagnostic Technique. [Citation Graph (0, 0)][DBLP ] Conf ] Larry C. Sollman An Information-Rich ATE Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Robert S. Broughton Structured Logic Analysis for Manufacturing Testing. [Citation Graph (0, 0)][DBLP ] Conf ] C. Timoc , M. Buehler , T. Griswold , C. Pina , F. Stott , L. Hess Logical Models of Physical Failures. [Citation Graph (0, 0)][DBLP ] Conf ] Prithviraj Banerjee , Jacob A. Abraham Generating Tests for Physical Failures in MOS Logic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Yashwant K. Malaiya , Ramesh Narayanaswamy Testing for Timing Faults in Synchronous Sequential Integrated Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Max Khazam Predicting Test Accuracy for Analog In-Circuit Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Joel Halbert , Mike Koen A Waveform Digitizer for Dynamic Testing of High Speed Data Conversion Components. [Citation Graph (0, 0)][DBLP ] Conf ] Matthew V. Mahoney New Techniques for High Speed Analog Testing. [Citation Graph (0, 0)][DBLP ] Conf ] E. A. Sloane , P. W. Dodd A General Method for Increasing Converter Accuracy and Resolution. [Citation Graph (0, 0)][DBLP ] Conf ] Douglas A. Blakeslee Real-Time Automatic Calibration of Analog Test Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Phil Carrier A Microprocessor Based Method for Testing Transition Noise in Analog to Digital Converters. [Citation Graph (0, 0)][DBLP ] Conf ] Aamer Mahmood , Edward J. McCluskey , David J. Lu Concurrent Fault Detection Using a Watchdog Processor and Assertions. [Citation Graph (0, 0)][DBLP ] Conf ] Alexander Kheruze , Ken Caruso An Application of Statistical Methods for System Failure Prediction. [Citation Graph (0, 0)][DBLP ] Conf ] Frederick G. Danner System Test Visibility Or Why Can't You Test Your Electronics. [Citation Graph (0, 0)][DBLP ] Conf ] F. Scott Davidson System Test: Applications of Control Interface Testing. [Citation Graph (0, 0)][DBLP ] Conf ] M. Small , D. Murray Bayesian Models of Tests : Some Practical Results. [Citation Graph (0, 0)][DBLP ] Conf ] Pat T. Harding , John C. Howland Turning Test Data into Information. [Citation Graph (0, 0)][DBLP ] Conf ] Kewal K. Saluja , Li Shen , Stephen Y. H. Su A Simplified Algorithm for Testing Microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] G. F. Meravi , J. J. Bell , J. C. Bernier Analysis of Gate Array Failures Using Functional ATE. [Citation Graph (0, 0)][DBLP ] Conf ] Tom Middleton Functional Test Vector Generation for Digital LSI/VLSI Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Feng-Hsien Warren Shih Real-Time Product Characterization by Fault Modeling and Pattern Recognitions. [Citation Graph (0, 0)][DBLP ] Conf ] C. Timoc , F. Stott , K. Wickman , L. Hess Adaptive Self-Test for a Microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Paul W. Horstmann Design for Testability Using Logic Programming. [Citation Graph (0, 0)][DBLP ] Conf ] Syed Zahoor Hassan Signature Testing of Sequential Machines. [Citation Graph (0, 0)][DBLP ] Conf ] Nick Kanopoulos , G. T. Mitchell Testing of Bit-Serial Signal Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Marc A. Rich , Daniel E. Gentry The Economics of Parallel Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Garry Marks Parallel Testing of Non-Volatile Memories. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen W. Bryson Testing a High Performance Modem Filter. [Citation Graph (0, 0)][DBLP ] Conf ] Juerg Hofer , Bob Sigsby Digital Signal Processing Test Techniques for Telecommunications Integrated Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Mark Landry Production Testing of PCM (Digital) Audio Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Robert Craven , Joseph Schissler , Peter Konde Chroma Voltmeter Measurement Techniques for Analog LSI Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Roger Dunn IC Quality Control by the User. [Citation Graph (0, 0)][DBLP ] Conf ] Sushil K. Malik , Jeffrey E. Gunn , Robert E. Camenga Future of Temperature and Humidity Testing: Highly Accelerated Temperature and Humidity Stress Test (HAST). [Citation Graph (0, 0)][DBLP ] Conf ] Kemon P. Taschioglou A Convenient Algebra of Quality for Interpreting ATE Test Data. [Citation Graph (0, 0)][DBLP ] Conf ] G. Siva Bushanam , H. Story Safe Operating Zones for Digital In-Circuit Testing. [Citation Graph (0, 0)][DBLP ] Conf ] 