Conferences in DBLP
John R. Wallace Look Who's Refueling the Technology Race. [Citation Graph (0, 0)][DBLP ] Conf ] Willem D. Maris Testability, the Achilles Heel of Design. [Citation Graph (0, 0)][DBLP ] Conf ] Richard M. Sedmak On the Possible Limits of External Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Michael J. Roberts Challenges in AC Testability : Testing Gigahertz Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Arthur R. Braun Testing in the Data Communications Industries. [Citation Graph (0, 0)][DBLP ] Conf ] Syed Zahoor Hassan An Efficient Self-Test Structure for Sequential Machines. [Citation Graph (0, 0)][DBLP ] Conf ] Wilfried Daehn , Josef Gross A Test Generator IC for Testing Large CMOS-RAMs. [Citation Graph (0, 0)][DBLP ] Conf ] Laung-Terng Wang , Edward J. McCluskey Circuits for Pseudo-Exhaustive Test Pattern Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Laung-Terng Wang , Edward J. McCluskey A Hybrid Design of Maximum-Length Sequence Generators. [Citation Graph (0, 0)][DBLP ] Conf ] Sheldon B. Akers A Parity Bit Signature for Exhaustive Testing. [Citation Graph (0, 0)][DBLP ] Conf ] William H. McAnney , Jacob Savir Built-In Checking of the Correct Self-Test Signature. [Citation Graph (0, 0)][DBLP ] Conf ] Dennis Mancl , Mark J. Sullivan A Solution to Test Data Acquisition and Management. [Citation Graph (0, 0)][DBLP ] Conf ] William W. Bust , Charles R. Darst , Gregory G. Krysl ABNER : A Burn-In Monitor and Error Reporting System for PBX Systems Test. [Citation Graph (0, 0)][DBLP ] Conf ] Mark D. Winkel Using a Relational Database to Develop a Statistical Quality Control System for ATE. [Citation Graph (0, 0)][DBLP ] Conf ] Earl Dalton , Walter Ahern , Stephen Denker , Ken Sweitzer , Bill Cooper , Tom Kelly , Stan Smith Systematic Yield Improvement in Board Testing Practice. [Citation Graph (0, 0)][DBLP ] Conf ] David P. Cohoon , Jey Sheridan Case History of Networking a Wafer-Sort Area. [Citation Graph (0, 0)][DBLP ] Conf ] Ioannis Stamelos , M. Melgara , M. Paolini , S. Morpurgo , C. Segre A Multi-Level Test Pattern Generation and Validation Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Hongtao P. Chang , William A. Rogers , Jacob A. Abraham Structured Functional Level Test Generation Using Binary Decision Diagrams. [Citation Graph (0, 0)][DBLP ] Conf ] Noriyoshi Itazaki , Kozo Kinoshita Test Pattern Generation for Circuits with Three-state Modules by Improved Z-algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Ki Soo Hwang , M. Ray Mercer Informed Test Generation Guidance Using Partially Specified Fanout Constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Ruey-Sing Wei , Alberto L. Sangiovanni-Vincentelli New Front-End and Line Justification Algorithm for Automatic Test Generation. [Citation Graph (0, 0)][DBLP ] Conf ] André Ivanov , Vinod K. Agarwal Testability Measures : What Do They Do for ATPG ? [Citation Graph (0, 0)][DBLP ] Conf ] Gregory Freeman , Dick L. Liu , Bruce A. Wooley , Edward J. McCluskey Two CMOS Metastability Sensors. [Citation Graph (0, 0)][DBLP ] Conf ] W. C. Bruce , C. C. Hunter , L. A. Basto Testing Barrel Shifters in Microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] E. Kofi Vida-Torku , James A. Monzel , Charles E. Radke Performance Assurance of Memories Embedded in VLSI Chips. [Citation Graph (0, 0)][DBLP ] Conf ] Mark R. Barber , Walter I. Satre Timing Measurements on CMOS VLSI Devices Designed to Drive TTL Loads. [Citation Graph (0, 0)][DBLP ] Conf ] Jody Van Horn Accurate, Cost Effective Performance Screening of VLSI Circuit Designs. [Citation Graph (0, 0)][DBLP ] Conf ] George Chiu , Jean-Mark Halbout Requirements and Trends for High Speed Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Barry Baril ASIC Verification: Second Generation Systems and Solutions. [Citation Graph (0, 0)][DBLP ] Conf ] Al A. Tuszynski Memory Chip Test Economics. [Citation Graph (0, 0)][DBLP ] Conf ] Judith E. Dayhoff , Robert W. Atherton Financial Impact of Tester Reliability Improvements. [Citation Graph (0, 0)][DBLP ] Conf ] Jerry Perone Reducing Test Costs Through Strategic Changes in Maintenance and Service. [Citation Graph (0, 0)][DBLP ] Conf ] Ron Leckie A Model for Analyzing Test Capacity, Cost, and Productivity. [Citation Graph (0, 0)][DBLP ] Conf ] Wendell Damm , Pete Janowitz , Michael Hagen , YeeMay Shih , Glenn Widener Vernier Method for Calibration ot High-Speed Sampling System. [Citation Graph (0, 0)][DBLP ] Conf ] Joe Kirschling Quickly Developing Effective Codec Tests on an In-Circuit Board Test System. [Citation Graph (0, 0)][DBLP ] Conf ] Mark Rich A Method of Flexible Catch RAM Display for Memory Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Kemon P. Taschioglou Test to Eliminate Test. [Citation Graph (0, 0)][DBLP ] Conf ] Ronald J. Short The DASS Needs You ! : An Update on the Activities of the DASS. [Citation Graph (0, 0)][DBLP ] Conf ] Richard Nohelty Test System Architecture for Testing Advanced Mixed-Signal Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Eugene R. Hnatek IC Burn-In : The Changing Scene. [Citation Graph (0, 0)][DBLP ] Conf ] Mark Paraskeva , Anthony P. Ambler , D. F. Burrows , W. L. Knight , I. D. Dear Economically Viable Automatic Insertion of Self-Test Features for Custom VLSI. [Citation Graph (0, 0)][DBLP ] Conf ] Balakrishnan Krishnamurthy , Ioannis G. Tollis Improved Techniques for Estimating Signal Probabilities. [Citation Graph (0, 0)][DBLP ] Conf ] Sreejit Chakravarty , Harry B. Hunt III On the Computation of Detection Probability for Multiple Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Jacob Savir , William H. McAnney Random Pattern Testability of Delay Faults. [Citation Graph (0, 0)][DBLP ] Conf ] A. J. Briers , K. A. E. Totton Random Pattern Testability by Fast Fault Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Tom W. Williams , Wilfried Daehn , Matthias Gruetzner , Corot W. Starke Comparison of Aliasing Errors for Primitive and Non-Primitive Polynomials. [Citation Graph (0, 0)][DBLP ] Conf ] Joe Kirschling Testing GaAs Devices with a Digital In-Circuit Test System. [Citation Graph (0, 0)][DBLP ] Conf ] Richard L. Swent , Michael J. Ward Thermal Analysis of Backdriven Output Transistors. [Citation Graph (0, 0)][DBLP ] Conf ] Vin Ratford , Paul Keating Integrating Guided Probe and Fault Dictionary: An Enhanced Diagnostic Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Mike Fabish A Strategy for Enhancing Fault Coverage on VLSI Circuit Boards Using Performance In-Circuit Test Techniques. [Citation Graph (0, 0)][DBLP ] Conf ] H. Bleeker , D. van de Lagemaat Testing a Board Loaded with Leaded and Surface Mounted Components. [Citation Graph (0, 0)][DBLP ] Conf ] Robert J. Russell A Method of Improving In-Circuit Test Effectiveness. [Citation Graph (0, 0)][DBLP ] Conf ] Gabriel M. Silberman , Ilan Y. Spillinger The Difference Fault Model : Using Functional Fault Simulation to Obtain Implementation Fault Coverage. [Citation Graph (0, 0)][DBLP ] Conf ] Chantal Vivier , Georges Fournie Automatic Modelling of MOS Transistor Networks for Test Pattern Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Alberto L. Sangiovanni-Vincentelli , Ruey-Sing Wei PROTEUS : A Logic Verification System for Combinational Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] David O. Lahti , Grace C. Chen-Ellis PROSPECT : A Production System for Partitioning and Evaluating Chip Testability. [Citation Graph (0, 0)][DBLP ] Conf ] Joseph L. A. Hughes , Edward J. McCluskey Multiple Stuck-At Fault Coverage of Single Stuck-At Fault Test Sets. [Citation Graph (0, 0)][DBLP ] Conf ] Scott Davidson , James L. Lewandowski ESIM/AFS : A Concurrent Architectural Level Fault Simulator. [Citation Graph (0, 0)][DBLP ] Conf ] Boyd Henshaw An MC68020 Users Test Program. [Citation Graph (0, 0)][DBLP ] Conf ] P. Seetharamaiah , V. R. Murthy Tabular Mechanisation for Flexible Testing of Microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Grady Giles , Kenneth Scheuer Testability Features of the MC68851 PMMU. [Citation Graph (0, 0)][DBLP ] Conf ] F. Warren Shih , Hu H. Chao , Shauchi Ong , Andrew L. Diamond , Jeffrey Y. F. Tang , Cynthia A. Trempel Testability Design for Micro/370, a System/370 Single Chip Microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Jesse G. Crane Testing the Sperry 36/72 Bit CMOS Micromainframe Chip Set. [Citation Graph (0, 0)][DBLP ] Conf ] A. Dale Flowers , Kamlesh Mathur , John Isakson Statistical Process Control Using the Parametric Tester. [Citation Graph (0, 0)][DBLP ] Conf ] M. Aghazadeh , M. Kirschner Transient Thermal Characteristics of VLSI Devices : Evaluation and Application. [Citation Graph (0, 0)][DBLP ] Conf ] Mario L. Côrtes , Edward J. McCluskey An Experiment on Intermittent-Failure Mechanisms. [Citation Graph (0, 0)][DBLP ] Conf ] Jerry M. Soden , Charles F. Hawkins Reliability and Electrical Properties of Gate Oxide Shorts in CMOS ICs. [Citation Graph (0, 0)][DBLP ] Conf ] Birger Schneider , Gert Jørgensen , Mogens B. Christensen The Effects of Backdrive Stressing Fast IC Technologies. [Citation Graph (0, 0)][DBLP ] Conf ] J. Laurent , L. Bergher , Bernard Courtois , Jacques P. Collin Towards Automatic Failure Analysis of Complex ICs Through E-Beam Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Leendert M. Huisman , Larry Carter , Tom W. Williams TRIM : Testability Range by Ignoring the Memory. [Citation Graph (0, 0)][DBLP ] Conf ] Robert H. Fujii , Jacob A. Abraham Approaches to Circuit Level Design for Testability. [Citation Graph (0, 0)][DBLP ] Conf ] Rafic Z. Makki , C. Tiansheng Designing Testable Control Paths with Multiple and Feedback Scan-Paths. [Citation Graph (0, 0)][DBLP ] Conf ] M. Ray Mercer Logic Elements for Universally Testable Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Rhonda Kay Gaede , M. Ray Mercer , Bill Underwood Calculation of Greatest Lower Bounds Obtainable by the Cutting Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Wang Jian-Cao , Wei Dao-Zheng A New Testability Measure for Digital Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Niraj K. Jha Detecting Multiple Faults in CMOS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Zeev Barzilai , J. Lawrence Carter , Vijay S. Iyengar , Indira Nair , Barry K. Rosen , Joe D. Rutledge , Gabriel M. Silberman Efficient Fault Simulation of CMOS Circuits with Accurate Models. [Citation Graph (0, 0)][DBLP ] Conf ] S. Koeppe Modeling and Simulation of Delay Faults in CMOS Logic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] David M. Wu , Charles E. Radke , J. P. Roth Statistical AC Test Coverage. [Citation Graph (0, 0)][DBLP ] Conf ] John A. Waicukauski , Eric Lindbloom , Vijay S. Iyengar , Barry K. Rosen Transition Fault Simulation by Parallel Pattern Single Fault Propagation. [Citation Graph (0, 0)][DBLP ] Conf ] Shmuel Shalem Functional Testing of the NS32332 \muProcessor. [Citation Graph (0, 0)][DBLP ] Conf ] T. J. Mulrooney Inexpensive Microprocessor Testing of Custom Integrated Circuits on Wafers, Packages, and Boards. [Citation Graph (0, 0)][DBLP ] Conf ] James D. Bray ATE Test Head Requirements for Low-Cost VLSI Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Ben Wells A Prober/Handler Interface for High Pin-Count ASIC Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Hideo Todokoro , Shouzou Yoneda , Sigemitu Seitou , Sigeyuki Hosoki Electron Beam Tester with 10 ps Time Resolution. [Citation Graph (0, 0)][DBLP ] Conf ] Francois J. Henley Tests of Hermetically Sealed LSI/VLSI Devices by Laser Photoexcitation Logic Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Noah Morgan An Automated Menu Screen Generation Software Tool for VLSI ATE Programming and Operation. [Citation Graph (0, 0)][DBLP ] Conf ] Rihard S. Chomiczewski VIVED : A Visual Vector Editor. [Citation Graph (0, 0)][DBLP ] Conf ] Jim Teisher Improved Workstation/Tester Interface Is the Key to the Quality of Test-Program Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Fred Cox , Lloyd K. Konneker , Douglas Moreland Visual Programming for Analog/Hybrid ATE. [Citation Graph (0, 0)][DBLP ] Conf ] Maqsoodul Mannan Instability : A CAD Dilemma. [Citation Graph (0, 0)][DBLP ] Conf ] Stefano Concina , Gerald Liu , Len Lattanzi , Semyon Reyfman , Neil Richardson Software Integration in a Workstation-Based F-Beam Tester. [Citation Graph (0, 0)][DBLP ] Conf ] Toshio Tamamura Video DAC/ADC Dynamic Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Steven M. McIntyre Testing 10-Bit A/D Converter with a Digital VLSI Tester. [Citation Graph (0, 0)][DBLP ] Conf ] David P. Orecchio ISDN, Analog or Digital Test ? [Citation Graph (0, 0)][DBLP ] Conf ] Randall Kramer ISDN Device Testing Demands a New Level of Performance for Automatic Test Equipment. [Citation Graph (0, 0)][DBLP ] Conf ] T. Noguchi , Atsushi Murakami , Masato Kawai , Y. Hayasaka Testing for a Solid-State Color Image Sensor. [Citation Graph (0, 0)][DBLP ] Conf ] Dong Sam Ha , Sudhakar M. Reddy On the Design of Random Pattern Testable PLAs. [Citation Graph (0, 0)][DBLP ] Conf ] Magdy S. Abadir , Melvin A. Breuer Scan Path with Look Ahead Shifting (SPLASH). [Citation Graph (0, 0)][DBLP ] Conf ] D. L. Tao , Carlos R. P. Hartmann , Parag K. Lala A Concurrent Testing Strategy for PLAs. [Citation Graph (0, 0)][DBLP ] Conf ] Kohei Fukuoka , Ken Ohga , Atsushi Sugiyama , Satoshi Takemura DVTS: Design Verification Techniques for Functional Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Vishwani D. Agrawal , M. Ray Mercer Deterministic Versus Random Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Parag K. Lala On Built-In Testing of VLSI Chips. [Citation Graph (0, 0)][DBLP ] Conf ] Chi W. Yau Concurrent Test Generation Using AI Techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Nagendra C. E. Srinivas , Anthony S. Wojcik , Ytzhak H. Levendel An Artificial Intelligence Based Implementation of the P-Algorithm for Test Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Rik Fischer Smoody ARNOLD: Applying an AI Workstation to Production Test Code Generation. [Citation Graph (0, 0)][DBLP ] Conf ] N. A. Jones , K. Baker An Intelligent Knowledge-Based System Tool for High-Level BIST Design. [Citation Graph (0, 0)][DBLP ] Conf ] Steve D. Bedrosian The Role of Pattern Recognition in VLSI Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Keating Fundamental Limits to Timing Accuracy. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen A. Cohen A New Pin Electronics Architecture for High Performance Functional Module Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel R. Simpkins Testing FMAX in a Production Environment. [Citation Graph (0, 0)][DBLP ] Conf ] J. Stephen Pabst Timing Accuracy and Yield Estimation. [Citation Graph (0, 0)][DBLP ] Conf ] Eric Rosenfeld Accuracy and Repeatability with DSP Test Methods. [Citation Graph (0, 0)][DBLP ] Conf ] Al Tejeda , George Conner Innovative Video RAM Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Al Mostacciuolo Transmission Problems Encountered When Testing Memory Devices in Parallel on Memory ATE. [Citation Graph (0, 0)][DBLP ] Conf ] A. Kanadjian , D. Rodgers , M. Shepherd FIFO Test Program Development. [Citation Graph (0, 0)][DBLP ] Conf ] Y. Nishimura , M. Hamada , H. Hidaka , H. Ozaki , K. Fujishima , Y. Hayasaka Redundancy Test for 1 Mbit DRAM Using Multi-Bit-Test Mode. [Citation Graph (0, 0)][DBLP ] Conf ] Kim T. Le , Kewal K. Saluja A Novel Approach for Testing Memories Using a Built-In Self Testing Technique. [Citation Graph (0, 0)][DBLP ] Conf ] T. J. Knips , D. J. Malone Designing Characterization Tests for Bipolar Array Performance Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Masato Kawai , T. Shimono , S. Funatsu Test Data Quality Assurance. [Citation Graph (0, 0)][DBLP ] Conf ] Vladimir Cherkassky , Larry L. Kinney A Group Probing Strategy for Testing Large Number of Chips. [Citation Graph (0, 0)][DBLP ] Conf ] Norio Kuji , Teruo Tamama An Automated F-Beam Tester with CAD Interface, "Finder": A Powerful Tool for Fault Diagnosis of ASICs. [Citation Graph (0, 0)][DBLP ] Conf ] E. Sarkany , J. Feeney , J. Muhr A Functional Test Program Generator. [Citation Graph (0, 0)][DBLP ] Conf ] Takashi Hidai , Toshi Matsumoto , Fumiro Tsuruda Test Program Debugging Environment for Linear IC Testers. [Citation Graph (0, 0)][DBLP ] Conf ] Charles D. Havener Issues That Arise in Translating VLSI Test Programs Between Testers. [Citation Graph (0, 0)][DBLP ] Conf ] Hasan Elhuni , Larry L. Kinney Techniques for Testing Hexagonally Connected Systolic Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Cheng Hsien Tung , John P. Robinson On Concurrently Testable Microprogrammed Control Units. [Citation Graph (0, 0)][DBLP ] Conf ] Nagesh Vasanthavada , Peter N. Marinos , Gerald S. Mersten Testing of Fault-Tolerant Clock Systems. [Citation Graph (0, 0)][DBLP ] Conf ] P. Veronneau , Pierre N. Robillard Proposed Test Method to Prove Software Having a Vector Space Behavior. [Citation Graph (0, 0)][DBLP ] Conf ] Günhan Kildiran , Peter N. Marinos Functional Testing of Microprocessor-like Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Yehuda Baron Self Diagnostics on System Level by Design. [Citation Graph (0, 0)][DBLP ] Conf ] Bruce L. Havlicsek A Knowledge Based Diagnostic System for Automatic Test Equipment. [Citation Graph (0, 0)][DBLP ] Conf ] Mary C. Murphy Hoye Artificial Intelligence in Semiconductor Manufacturing for Process Development, Functional Diagnostics, and Yield Crash Prevention. [Citation Graph (0, 0)][DBLP ] Conf ] Larry Apfelbaum Improving In-Circuit Diagnosis of Analog Networks with Expert Systems Techniques. [Citation Graph (0, 0)][DBLP ] Conf ] M. Arif Samad , José A. B. Fortes Explanation Capabilities in DEFT : A Design-For-Testability Expert System. [Citation Graph (0, 0)][DBLP ] Conf ] A. Jesse Wilkinson Benchmarking an Expert System for Electronic Diagnosis. [Citation Graph (0, 0)][DBLP ] Conf ] Oliver Grillmeyer Making a Test System Diagnostic Usable. [Citation Graph (0, 0)][DBLP ] Conf ] Y. C. Jenq Automated Effective-Bit Characterization of Waveform Digitizers. [Citation Graph (0, 0)][DBLP ] Conf ] Eric Rosenfeld DSP Measurement of Frequency. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Keating An Improved Search Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] K. Moriwaki , S. Ishiyama , K. Takizawa , F. Kobayashi , S. Sekine , Y. Hinataze A Test System tor High Density and High Speed Digital Board. [Citation Graph (0, 0)][DBLP ] Conf ] J. S. R. Subrahmanyam , P. Pal Chaudhuri A Divide and Conquer Testing Strategy for Detection of Multiple Faults by SFDTS. [Citation Graph (0, 0)][DBLP ] Conf ] 