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International Test Conference (ITC) (itc)
2002 (conf/itc/2002)

  1. Alex d'Arbeloff
    Managing in the ATE Business - Postcards from the Past, Lessons for the Future. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:12- [Conf]
  2. Peter C. Maxwell
    The Heisenberg Uncertainty of Test. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:13- [Conf]
  3. Bozena Kaminska
    Homegrown Tools and Equipment versus EDA and ATE Vendors: The Future of Design to Test Product Lines. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:23- [Conf]
  4. Bill Bottoms
    Homegrown Tools and Equipment versus EDA and ATE Vendors: The Future of Design to Test Product Lines. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:24- [Conf]
  5. Greg Spirakis
    Homegrown Tools and Equipment versus EDA and ATE Vendors: The Future of Design to Test Product Lines. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:25- [Conf]
  6. Dale E. Hoffman
    Homegrown Tools and Equipment versus EDA and ATE Vendors: The Future of Design to Test Product Lines. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:26- [Conf]
  7. Rochit Rajsuman
    Testing The Tester. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:27- [Conf]
  8. Alfred L. Crouch
    Testing the Tester: What Broke? Where? When? Why? [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:28- [Conf]
  9. John C. Johnson
    Testing the Tester: Specification and Validation Approaches. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:29- [Conf]
  10. Rochit Rajsuman
    Testing The Tester. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:30- [Conf]
  11. Jean Michel Portal, L. Forli, H. Aziza, Didier Née
    An Automated Methodology to Diagnose Geometric Defect in the EEPROM Cell. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:31-36 [Conf]
  12. Sau-Kwo Chiu, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu
    Diagonal Test and Diagnostic Schemes for Flash Memorie. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:37-46 [Conf]
  13. A. T. Sivaram, Daniel Fan, A. Yiin
    Efficient Embedded Memory Testing with APG. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:47-54 [Conf]
  14. Bart Vermeulen, Tom Waayers, Sjaak Bakker
    EEE 1149.1-Compliant Access Architecture for Multiple Core Debug on Digital System Chips. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:55-63 [Conf]
  15. Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici
    Integrated Test Data Decompression and Core Wrapper Design for Low-Cost System-on-a-Chip Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:64-73 [Conf]
  16. Yu Huang, Sudhakar M. Reddy, Wu-Tung Cheng, Paul Reuter, Nilanjan Mukherjee, Chien-Chung Tsai, Omer Samman, Yahya Zaidan
    Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:74-82 [Conf]
  17. Sudhakar M. Reddy, Irith Pomeranz, Huaxing Tang, Seiji Kajihara, Kozo Kinoshita
    On Testing of Interconnect Open Defects in Combinational Logic Circuits with Stems of Large Fanout. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:83-89 [Conf]
  18. Jaume Segura, Ali Keshavarzi, Jerry M. Soden, Charles F. Hawkins
    Parametric Failures in CMOS ICs - A Defect-Based Analysis. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:90-99 [Conf]
  19. Cecilia Metra, Stefano Di Francescantonio, T. M. Mak
    Clock Faults? Impact on Manufacturing Testing and Their Possible Detection Through On-Line Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:100-109 [Conf]
  20. Hideo Okawara
    Frequency/Phase Movement Analy i by Orthogonal Demodulation. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:110-119 [Conf]
  21. Mani Soma, Welela Haileselassie, Jessica Yan, Rajesh Raina
    A Wavelet-Based Timing Parameter Extraction Method. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:120-128 [Conf]
  22. Sassan Tabatabaei, André Ivanov
    An Embedded Core for Sub-Picosecond Timing Measurements. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:129-137 [Conf]
  23. M. J. Geuzebroek, J. Th. van der Linden, A. J. van de Goor
    Test Point Insertion that Facilitates ATPG in Reducing Test Time and Data Volume. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:138-147 [Conf]
  24. Vishal Jain, John A. Waicukauski
    Scan Test Data Volume Reduction in Multi-Clocked Designs with Safe Capture Technique. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:148-153 [Conf]
  25. Erik H. Volkerink, Ajay Khoche, Subhasish Mitra
    Packet-Based Input Test Data Compression Techniques. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:154-163 [Conf]
  26. O. Hirabayashi, A. Suzuki, T. Yabe, A. Kawasumi, Y. Takeyama, K. Kushida, A. Tohata, N. Otsuka
    DFT Techniques for Wafer-Level At-Speed Testing of High-Speed SRAMs. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:164-169 [Conf]
  27. Shigeki Tomishima, Hiroaki Tanizaki, Mitsutaka Niiro, Masanao Maruta, Hideto Hidaka, T. Tada, Kenji Gamo
    A Variable Drivability (VD) Output Buffer for the System In a Package (SIP) and High Frequency Wafer Test. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:170-177 [Conf]
  28. Bruce Cowan, Owen Farnsworth, Peter Jakobsen, Steven F. Oakland, Michael Ouellette, Donald L. Wheater
    On-Chip Repair and an ATE Independent Fusing Methodology. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:178-186 [Conf]
  29. Jayasanker Jayabalan, Juraj Povazanec
    Integration of SRAM Redundancy into Production Test. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:187-193 [Conf]
  30. Jacob A. Abraham, Vivekananda M. Vedula, Daniel G. Saab
    Verifying Properties Using Sequential ATPG. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:194-202 [Conf]
  31. Ganapathy Parthasarathy, Madhu K. Iyer, Tao Feng, Li-C. Wang, Kwang-Ting Cheng, Magdy S. Abadir
    Combining ATPG and Symbolic Simulation for Efficient Validation of Embedded Array Systems. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:203-212 [Conf]
  32. Jayanta Bhadra, Narayanan Krishnamurthy
    Automatic Generation of Design Constraints in Verifying High Performance Embedded Dynamic Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:213-222 [Conf]
  33. Andreas G. Veneris, Magdy S. Abadir, Mandana Amiri
    Design Rewiring Using ATPG. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:223-232 [Conf]
  34. Ronald D. Blanton, John T. Chen, Rao Desineni, Kumar N. Dwarakanath, Wojciech Maly, Thomas J. Vogels
    Fault Tuples in Diagnosis of Deep-Submicron Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:233-241 [Conf]
  35. Yasuo Sato, Iwao Yamazaki, Hiroki Yamanaka, Toshio Ikeda, Masahiro Takakura
    A Persistent Diagnostic Technique for Unstable Defects. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:242-249 [Conf]
  36. David B. Lavo, Ismed Hartanto, Tracy Larrabee
    Multiplets, Models, and the Search for Meaning: Improving Per-Test Fault Diagnosis. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:250-259 [Conf]
  37. Camelia Hora, Rene Segers, Stefan Eichenberger, Maurice Lousberg
    An Effective Diagnosis Method to Support Yield Improvement. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:260-269 [Conf]
  38. Tom Austin, Charisma Canlas, Brady Morgan, Jorge Luis Rodriguez
    Across the Great Divide: Examination of Simulation Data with Actual Silicon Waveforms Improves Device Characterization and Production Test Development. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:270-279 [Conf]
  39. A. T. Sivaram, William Fritzsche, Toshitaka Koshi, Nam Lai
    DUT Capture Using Simultaneous Logic Acquisition. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:280-289 [Conf]
  40. Gregory A. Maston
    Considerations for STIL Data Application. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:290-296 [Conf]
  41. Guy Peterson
    Verification of Device Interface Hardware Interconnections Prior to the Start of Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:297-300 [Conf]
  42. Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee, Rob Thompson, Kun-Han Tsai, Andre Hertwig, Nagesh Tamarapalli, Grzegorz Mrugalski, Geir Eide, Jun Qian
    Embedded Deterministic Test for Low-Cost Manufacturing Test. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:301-310 [Conf]
  43. Subhasish Mitra, Kee Sup Kim
    X-Compact: An Efficient Response Compaction Technique for Test Cost Reduction. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:311-320 [Conf]
  44. C. V. Krishna, Nur A. Touba
    Reducing Test Dat Volume Using LFSR Reseeding with Seed Compression. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:321-330 [Conf]
  45. Francis G. Wolff, Christos A. Papachristou
    Multiscan-Based Test Compression and Hardware Decompression Using LZ77. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:331-339 [Conf]
  46. Yervant Zorian
    Embedded Memory Test and Repair: Infrastructure IP for SOC Yield. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:340-349 [Conf]
  47. Mark Craig, Alvin Jee, Prashant Maniar
    An Integrated Approach to Yield Loss Characterization. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:350-356 [Conf]
  48. Eric Dupont, Michael Nicolaidis
    Robustness IPs for Reliability and Security of SoCs. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:357-364 [Conf]
  49. Shahin Nazarian, Hang Huang, Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer
    XIDEN: Crosstalk Target Identification Framework. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:365-374 [Conf]
  50. Aditya D. Sathe, Michael L. Bushnell, Vishwani D. Agrawal
    Analog Macromodeling of Capacitive Coupling Faults in Digital Circuit Interconnects. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:375-383 [Conf]
  51. Bipul Chandra Paul, Kaushik Roy
    Testing CrossTalk Induced Delay Faults in Static CMOS Circuits Through Dynamic Timing Analysis. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:384-390 [Conf]
  52. A. V. S. S. Prasad, Vishwani D. Agrawal, Madhusudan V. Atre
    A New Algorithm for Global Fault Collapsing into Equivalence and Dominance Sets. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:391-397 [Conf]
  53. Li-C. Wang, Magdy S. Abadir, Juhong Zhu
    On Testing High-Performance Custom Circuits without Explicit Testing of the Internal Faults. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:398-406 [Conf]
  54. Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams
    Analysis of Delay Test Effectiveness with a Multiple-Clock Scheme. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:407-416 [Conf]
  55. D. Gessel, A. Slcoum, A. Sprunt, S. Ziegenhagen
    Realistic Spring Probe Testing Methods and Results. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:417-423 [Conf]
  56. Kenichi Kataoka, Toshihiro Itoh, Katsuya Okumura, Tadatomo Suga
    Low-Contact-Force Probing on Copper Electrodes. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:424-429 [Conf]
  57. Wolfram Humann
    Compensation of Transmission Line Loss for Gbit/s Test on ATEs. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:430-437 [Conf]
  58. J. S. Davis, David C. Keezer
    Multi-Purpose Digital Test Core Utilizing Programmable Logic. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:438-445 [Conf]
  59. Stephen K. Sunter, Benoit Nadeau-Dostie
    Complete, Contactless I/O Testing - Reaching the Boundary in Minimizing Digital IC Testing Cost. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:446-455 [Conf]
  60. Mike Mayberry, John Johnson, Navid Shahriari, Mike Tripp
    Realizing the Benefits of Structural Test for Intel Microprocessors. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:456-463 [Conf]
  61. David Turner, David Abercrombie, James McNames, W. Robert Daasch, Robert Madge
    Isolating and Removing Sources of Variation in Test Data. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:464-471 [Conf]
  62. Rajneesh Mahajan, Ramesh Govindarajulu, J. R. Armstrong, F. G. Gray
    A Multi-Language Goal-Tree Based Functional Test Planning System. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:472-481 [Conf]
  63. David Williams, Anthony P. Ambler
    System Manufacturing Test Cost Model. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:482-490 [Conf]
  64. Yi Zhao, Li Chen, Sujit Dey
    On-Line Testing of Multi-Source Noise-Induced Errors on the Interconnects and Buses of System-on-Chips. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:491-499 [Conf]
  65. Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto
    Static Analysis of SEU Effects on Software Applications. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:500-508 [Conf]
  66. Sreejit Chakravarty, Ankur Jain, Nandakumar Radhakrishnan, Eric W. Savage, Sujit T. Zachariah
    Experimental Evaluation of Scan Tests for Bridges. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:509-518 [Conf]
  67. Erik Jan Marinissen, Vikram Iyengar, Krishnendu Chakrabarty
    A Set of Benchmarks fo Modular Testing of SOCs. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:519-528 [Conf]
  68. Sandeep Kumar Goel, Erik Jan Marinissen
    Effective and Efficient Test Architecture Design for SOCs. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:529-538 [Conf]
  69. Sandeep Koranne, Vikram Iyengar
    On the Use of k-tuples for SoC Test Schedule Representation. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:539-548 [Conf]
  70. Todd Sargent
    Physical Principles of Interface Design. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:549-554 [Conf]
  71. Thomas P. Warwick
    What a Device Interface Board Really Costs: An Evaluation of Technical Considerations for Testing Products Operating in the Gigabit Region. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:555-564 [Conf]
  72. David E. McFeely
    The Process and Challenges of a High-Speed DUT Board Project. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:565-573 [Conf]
  73. B. Bailey, A. Metayer, B. Svrcek, Nandu Tendolkar, E. Wolf, Eric Fiene, Mike Alexander, Rick Woltenberg, Rajesh Raina
    Test Methodology for Motorola's High Performance e500 Core Based on PowerPC Instruction Set Architecture. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:574-583 [Conf]
  74. Timothe Litt
    Support for Debugging in the Alpha 21364 Microprocessor. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:584-589 [Conf]
  75. Praveen Parvathala, Kaila Maneparambil, William Lindsay
    FRITS - A Microprocessor Functional BIST Method. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:590-598 [Conf]
  76. Shahin Toutounchi, Andrew Lai
    FPGA Test and Coverage. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:599-607 [Conf]
  77. Mehdi Baradaran Tahoori, Subhasish Mitra, Shahin Toutounchi, Edward J. McCluskey
    Fault Grading FPGA Interconnect Test Configurations. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:608-617 [Conf]
  78. Charles E. Stroud, Jeremy Nall, Matthew Lashinsky, Miron Abramovici
    BIST-Based Diagnosis of FPGA Interconnect. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:618-627 [Conf]
  79. Hari Balachandran, Kenneth M. Butler, Neil Simpson
    Facilitating Rapid First Silicon Debug. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:628-637 [Conf]
  80. Bart Vermeulen, Tom Waayers, Sandeep Kumar Goel
    Core-Based Scan Architecture for Silicon Debug. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:638-647 [Conf]
  81. Xinli Gu, Weili Wang, Kevin Li, Heon C. Kim, Sung Soo Chung
    Re-Using DFT Logic for Functional and Silicon Debugging Test. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:648-656 [Conf]
  82. Don Douglas Josephson
    The Manic Depression of Microprocessor Debug. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:657-663 [Conf]
  83. Carol Pyron, Rekha Bangalore, Dawit Belete, Jason Goertz, Ashutosh Razdan, Denise Younger
    Silicon Symptoms to Solutions: Applying Design for Debug Techniques. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:664-672 [Conf]
  84. Robert Madge, B. H. Goh, V. Rajagopalan, C. Macchietto, W. Robert Daasch, Chris Schuermyer, C. Taylor, David Turner
    Screening MinVDD Outliers Using Feed-Forward Voltage Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:673-682 [Conf]
  85. Minh Quach, Tuan Pham, Tim Figal, Bob Kopitzke, Pete O'Neill
    Wafer-Level Defect-Based Testing Using Enhanced Voltage Stress and Statistical Test Data Evaluation. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:683-692 [Conf]
  86. Thomas S. Barnett, Matt Grady, Kathleen G. Purdy, Adit D. Singh
    Redundancy Implications for Early-Life Reliability: Experimental Verification of an Integrated Yield-Reliability Model. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:693-699 [Conf]
  87. Y. Cai, S. A. Werner, G. J. Zhang, M. J. Olsen, R. D. Brink
    Jitter Testing for Multi-Gigabit Backplane SerDes - Techniques to Decompose and Combine Various Types of Jitter. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:700-709 [Conf]
  88. Mike P. Li, Jan B. Wilstrup
    On the Accuracy of Jitter Separation from Bit Error Rate Function. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:710-716 [Conf]
  89. Takahiro J. Yamaguchi, Mani Soma, Masahiro Ishida, Hirobumi Musha, Louis Malarsie
    A New Method for Testing Jitter Tolerance of SerDes Devices Using Sinusoidal Jitter. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:717-725 [Conf]
  90. Ishwar Parulkar, Thomas A. Ziaja, Rajesh Pendurkar, Anand D'Souza, Amitava Majumdar
    A Scalable, Low Cost Design-for-Test Architecture for UltraSPARC? Chip Multi-Processors. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:726-735 [Conf]
  91. Sungbae Hwang, Jacob A. Abraham
    Optimal BIST Using an Embedded Microprocessor. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:736-745 [Conf]
  92. Dave Stang, Ramaswami Dandapani
    An Implementation of IEEE 1149.1 to Avoid Timing Violations and Other Practical In-Compliance Improvements. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:746-754 [Conf]
  93. Michael Cogswell, Shazia Mardhani, Kevin Melocco, Hina Arora
    A Structured Graphical Tool for Analyzing Boundary Scan Violations. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:755-762 [Conf]
  94. Adam Kristof
    Improved Digital I/O Ports Enhance Testability of Interconnections. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:763-772 [Conf]
  95. Sezer Gören, F. Joel Ferguson
    Testing Finite State Machines Based on a Structural Coverage Metric . [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:773-780 [Conf]
  96. David Berthelot, Samit Chaudhuri, Hamid Savoj
    An Efficient Linear Time Algorithm for Scan Chain Optimization and Repartitioning. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:781-787 [Conf]
  97. Loïs Guiller, Frederic Neuveux, S. Duggirala, R. Chandramouli, Rohit Kapur
    Integrating DFT in the Physical Synthesis Flow. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:788-795 [Conf]
  98. Yannick Bonhomme, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
    Power Driven Chaining of Flip-Flops in Scan Architectures. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:796-803 [Conf]
  99. Frank te Beest, Ad M. G. Peeters, Marc Verra, Kees van Berkel, Hans G. Kerkhoff
    Automatic Scan Insertion and Test Generation for Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:804-813 [Conf]
  100. Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira, Salvador Manich, Rosa Rodríguez-Montañés, Joan Figueras
    RTL Level Preparation of High-Quality/Low-Energy/Low-Power BIST. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:814-823 [Conf]
  101. Zhigang Jiang, Sandeep K. Gupta
    An ATPG for Threshold Testing: Obtaining Acceptable Yield in Future Processes. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:824-833 [Conf]
  102. Seongmoon Wang
    Generation of Low Power Dissipation and High Fault Coverage Patterns for Scan-Based BIST. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:834-843 [Conf]
  103. Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu
    Scan Power Reduction Through Test Data Transition Frequency Analysis. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:844-850 [Conf]
  104. Carsten Wegener, Michael Peter Kennedy
    Implementation of Model-Based Testing for Medium to High-Resolution Nyquist-Rate ADCs. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:851-860 [Conf]
  105. M. Stancic, L. Fang, M. H. H. Weusthof, R. M. W. Tijink, Hans G. Kerkhoff
    A New Test Generation Approach for Embedded Analogue Cores in SoC. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:861-869 [Conf]
  106. Gunter Krampl, Marco Rona, Hermann Tauber
    Test Setup Simulation - A High-Performance VHDL-Based Virtual Test Solution Meeting Industrial Requirements. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:870-878 [Conf]
  107. Maurizio Gavardoni
    Use of Pipeline Converters for ATE Applications. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:879-884 [Conf]
  108. Ahmed Rashid Syed
    R4X/D4X - Formatters for Flexible Test System Architecture. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:885-893 [Conf]
  109. Toshiyuki Okayasu, Masakatsu Suda, Kazuhiro Yamamoto
    CMOS Circuit Technology for Precise GHz Timing Generator. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:894-902 [Conf]
  110. Masashi Shimanouchi
    New Paradigm for Signal Paths in ATE Pin Electronics are Needed for Serialcom Device Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:903-912 [Conf]
  111. Jean-Pascal Mallet
    High Current DPS Architecture for Sort Test Challenge. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:913-922 [Conf]
  112. Tapan J. Chakraborty, Chen-Huan Chiang
    A Novel Fault Injection Method for System Verification Based on FPGA Boundary Scan Architectur. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:923-929 [Conf]
  113. Andrea Baldini, Alfredo Benso, Paolo Prinetto, Sergio Mo, Andrea Taddei
    Efficient Design of System Test: A Layered Architecture. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:930-939 [Conf]
  114. Liviu Miclea, Enyedi Szilárd, Alfredo Benso
    Itelligent Agents and BIST/BISR - Working Together in Distributed Systems. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:940-946 [Conf]
  115. B. Alorda, M. Rosales, Jerry M. Soden, Charles F. Hawkins, Jaume Segura
    Charge Based Transient Current Testing (CBT) for Submicron CMOS SRAMs. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:947-953 [Conf]
  116. David I. Bergman, Hans Engler
    Improved IDDQ Testing with Empirical Linear Prediction. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:954-963 [Conf]
  117. Bram Kruseman, Stefan van den Oetelaar, Josep Rius
    Comparison of IDDQ Testing and Very-Low Voltage Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:964-973 [Conf]
  118. Manish Sharma, Janak H. Patel
    Finding a Small Set of Longest Testable Paths that Cover Every Gate. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:974-982 [Conf]
  119. Xiao Liu, Michael S. Hsiao, Sreejit Chakravarty, Paul J. Thadikaran
    Techniques to Reduce Data Volume and Application Time for Transition Test. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:983-992 [Conf]
  120. Ramesh C. Tekumalla, Scott Davidson
    On Identifying Indistinguishable Path Delay Faults and Improving Diagnosis. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:993-1002 [Conf]
  121. Kazumi Hatayama, Michinobu Nakao, Yoshikazu Kiyoshige, Koichiro Natsume, Yasuo Sato, Takaharu Nagumo
    Application of High-Quality Built-In Test to Industrial Designs. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1003-1012 [Conf]
  122. Nadir Z. Basturkmen, Sudhakar M. Reddy, Irith Pomeranz
    Pseudo Random Patterns Using Markov Sources for Scan BIST. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1013-1021 [Conf]
  123. Mohamed Hafed, Gordon W. Roberts
    Test and Evaluation of Multiple Embedded Mixed-Signal Test Cores. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1022-1030 [Conf]
  124. Aubin Roy, Stephen K. Sunter, Alessandra Fudoli, Davide Appello
    High Accuracy Stimulus Generation for A/D Converter BIST. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1031-1039 [Conf]
  125. John Gatej, Lee Song, Carol Pyron, Rajesh Raina, Tom Munns
    valuating ATE Features in Terms of Test Escape Rates and Other Cost of Test Culprits. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1040-1049 [Conf]
  126. Peter C. Maxwell
    Wafer/Package Test Mix for Optimal Defect Detection. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1050-1055 [Conf]
  127. Bill Eklow, Carl Barnhart, Kenneth P. Parker
    IEEE P1149.6: A Boundary-Scan Standard for Advanced Digital Networks. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1056-1065 [Conf]
  128. Kathy Hird, Kenneth P. Parker, Bill Follis
    Test Coverage: What Does It Mean When a Board Test Passes?. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1066-1074 [Conf]
  129. Nilmoni Deb, R. D. (Shawn) Blanton
    Built-In Self Test of CMOS-MEMS Accelerometers. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1075-1084 [Conf]
  130. Jiang Brandon Liu, Andreas G. Veneris, Hiroshi Takahashi
    Incremental Diagnosis of Multiple Open-Interconnects. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1085-1092 [Conf]
  131. Mohammad H. Tehranipour, Mehrdad Nourani
    Signal Integrity Loss in SoC's Interconnects: A Diagnosis Approach Using Embedded Microprocessor. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1093-1102 [Conf]
  132. Sandeep Kumar Goel, Bart Vermeulen
    Hierarchical Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1103-1110 [Conf]
  133. Dawit Belete, Ashutosh Razdan, William Schwarz, Rajesh Raina, Christopher Hawkins, Jeff Morehead
    Use of DFT Techniques In Speed Grading a 1GHz+ Microprocessor . [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1111-1119 [Conf]
  134. Jayashree Saxena, Kenneth M. Butler, John Gatt, R. Raghuraman, Sudheendra Phani Kumar, Supatra Basu, David J. Campbell, John Berech
    Scan-Based Transition Fault Testing - Implementation and Low Cost Test Challenges . [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1120-1129 [Conf]
  135. Bhaskar Chatterjee, Manoj Sachdev, Ali Keshavarzi
    A DFT Technique for Low Frequency Delay Fault Testing in High Performance Digital Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1130-1139 [Conf]
  136. Koji Asami, Yasuo Furukawa, Michael Purtell, Motoo Ueda, Karl Watanabe, Toshifumi Watanabe
    WCDMA Testing with a Baseband/IF Range AWG. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1140-1145 [Conf]
  137. Kevin M. MacKay
    Testing Wireless Local Area Network Transceiver ICs at 5 GHz. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1146-1150 [Conf]
  138. John Ferrario, Randy Wolf, Steve Moss
    Architecting Millisecond Test Solutions for Wireless Phone RFIC's. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1151-1158 [Conf]
  139. Vikram Iyengar, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty
    Test Resource Optimization for Multi-Site Testing of SOCs Under ATE Memory Depth Constraints. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1159-1168 [Conf]
  140. Rainer Dorsch, Ramón Huerta Rivera, Hans-Joachim Wunderlich, Martin Fischer
    Adapting an SoC to ATE Concurrent Test Capabilities. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1169-1175 [Conf]
  141. Mohsen Nahvi, André Ivanov, Resve A. Saleh
    Dedicated Autonomous Scan-Based Testing (DAST) for Embedded Cores. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1176-1184 [Conf]
  142. David Williams
    Test Coverage Models for System Test? [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1185- [Conf]
  143. Rochit Rajsuman
    Can IC Test Learn from How a Tester is Tested. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1186- [Conf]
  144. Scott Davidson
    What Can IC Test Teach System Test? [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1187- [Conf]
  145. Anthony P. Ambler
    Is It Rocket Science? [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1188-1189 [Conf]
  146. Bart Vermeulen
    TAPS All Over My Chips! So Now What Do I Do? [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1190- [Conf]
  147. Lee Whetsel
    Inevitable Use of TAP Domains in SOCs. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1191- [Conf]
  148. Steven F. Oakland
    TAPs All Over My Chips. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1192- [Conf]
  149. Teresa L. McLaurin
    TAPS All Over My Chips. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1193-1194 [Conf]
  150. Anjali Kinra Vij
    Good Scan = Good Quality Level? Well, It Depends ? [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1195- [Conf]
  151. Carol Pyron
    Scan and BIST Can Almost Achieve Test Quality Levels. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1196- [Conf]
  152. Grady Giles
    Is Scan (Alone) Sufficient to Test Today?s Microprocessors? Not Quite, but We Can?t Get the Job Done Without It. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1197- [Conf]
  153. Phil Nigh
    Scan-Based Testing: The Only Practical Solution for Testing ASIC/Consumer Products. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1198- [Conf]
  154. David M. Wu
    Trouble With Scan. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1199-1200 [Conf]
  155. Arnold Frisch
    A/MS BISTs: The FACTS, Just the Facts. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1201- [Conf]
  156. Karim Arabi
    Mixed-Signal BIST: Fact or Fiction. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1202- [Conf]
  157. Lee Y. Song
    Mixed Signal BIST: Fact or Fiction. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1203- [Conf]
  158. Gordon W. Roberts
    Mixed-Signal BIST: Fact or Fiction. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1204- [Conf]
  159. Stephen K. Sunter
    IC Mixed-Signal BIST: Separating Facts from Fiction. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1205- [Conf]
  160. Dennis R. Conti
    Mission Impossible? Open Architecture ATE. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1207- [Conf]
  161. Paul F. Scrivens
    Mission Possible? Open Architecture ATE. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1208- [Conf]
  162. Paul D. Roddy
    Is an Open Architecture Tester Really Achievable? [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1209- [Conf]
  163. Sergio M. Perez
    The Consequences of an Open ATE Architecture. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1210- [Conf]
  164. Mark Jagiela
    An Open Architecture for Semiconductor Test: Enablers and Challenges. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1211- [Conf]
  165. Burnell G. West
    Open ATE Architecture: Key Challenges. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1212-1213 [Conf]
  166. Bill Price
    The Role of Test in a Highly Outsourced Business Model. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1214- [Conf]
  167. Davide Appello
    The Yield of Test Outsourcing. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1215- [Conf]
  168. Fidel Muradali
    The Impact of Outsourcing on Test. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1216- [Conf]
  169. Peter Muhmenthaler
    Outsourcing Test without Standards?. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1217-1218 [Conf]
  170. Jean Michel Daga
    Test and Repair of Embedded Flash Memories. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1219- [Conf]
  171. Paul Okino
    Test Time Impact of Redundancy Repair in Embedded Flash Memory. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1220- [Conf]
  172. Riichiro Shirota
    Test and Repair of Non-Volatile Commodity and Embedded Memories (NAND Flash Memory). [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1221- [Conf]
  173. Roger Barth
    Selective Optimization of Test for Embedded Flash Memory. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1222- [Conf]
  174. Shigeo Tsuchida
    Test and Repair of Nonvolatile Commodity and Embedded Memories. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1223-1224 [Conf]
  175. Mustapha Slamani
    Testing Highly Integrated Wireless Circuits and Systems with Low Cost Tester: How to Overcome the Challenge? [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1225- [Conf]
  176. Alan Kafton
    Wireless SOC Testing: Can RF Testing Costs Be Reduced? [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1226-1227 [Conf]
  177. C. Hawkins, J. Segura
    Testing Highly Integrated Wireless Circuits and Systems with Low Cost Tester: How to Overcome the Challenge? [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1228- [Conf]
  178. Takahiro J. Yamaguchi
    Wireless SOC Testing: Can RF Testing Costs Be Reduced? [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1229- [Conf]
  179. David C. Keezer
    GHz Testing and Its Fuzzy Targets. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1230- [Conf]
  180. Manoj Sachdev
    Multi-GHz Interface Devices Should Be Tested Using External Test Resources. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1231- [Conf]
  181. Mike Tripp
    Challenges and Solutions for Multi-Gigahertz Testing . [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1232- [Conf]
  182. Ulrich Schoettmer
    Multi-Gigahertz Digital Test Challenges and Techniques. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1233-1234 [Conf]
  183. Bill Eklow
    Is Board Test Worth Talking About? [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1235- [Conf]
  184. Gordon D. Robinson
    Board Test: Wanted Dead or Alive. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1236- [Conf]
  185. Kenneth M. Butler
    Is ITC Bored with Board Test? [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1237- [Conf]
  186. Kenneth P. Parker
    Board Test Is NOT Mature. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1238- [Conf]
  187. Monica Lobetti Bodoni
    Panel: "Board Test and ITC: What Does the Future Hold?". [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1239- [Conf]
  188. W. Robert Daasch, Kevin Cota, James McNames, Robert Madge
    Neighbor Selection for Variance Reduction in IDDQ and Other Parametric Data. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1240- [Conf]
NOTICE1
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NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002