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International Test Conference (ITC) (itc)
1988 (conf/itc/1988)

  1. A. Blanton Godfrey
    Managing Quality : Today's Opportunities, Tomorrow's Challenges. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:1- [Conf]
  2. Lutz P. Henckels
    Scan Path and Beyond : The Road to Improved ASIC Testability. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:2- [Conf]
  3. Alberto L. Sangiovanni-Vincentelli
    Optimal Logic Synthesis and Testability : Two Sides of the Same Coin. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:3-12 [Conf]
  4. Sheng-Jen Tsai, Charles D. Hechtman
    GaAs Driver and Sensor for a High-Speed Test System. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:13-22 [Conf]
  5. Christopher W. Branson, Don Murray, Steve Sullivan
    Integrated Pin Electronics for a VLSI Test System. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:23-27 [Conf]
  6. J. R. Birchak, H. K. Haill
    Characteristic Impedance and Coupling Coefficients for Multilayer PC Boards. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:28-38 [Conf]
  7. Robert E. McAuliffe
    Practical Production Testing of ISDN Circuit Boards. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:39-46 [Conf]
  8. Mark G. Karpovsky, Prawat Nagvajara
    Board-Level Diagnosis by Signature Analysis. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:47-53 [Conf]
  9. Stephen Y. H. Su, Hede Ma
    Fault Isolation in Grey Systems. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:54-63 [Conf]
  10. C. Bellon, Raoul Velazco, Haissam Ziade
    Analysis of Experimental Results on Functional Testing and Diagnosis of Complex Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:64-72 [Conf]
  11. Hans Peter Klug
    Microprocessor Testing by Instruction Sequences Derived from Random Patterns. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:73-80 [Conf]
  12. Janusz Sosnowski
    Detection of Control Flow Errors Using Signature and Checking Instructions. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:81-88 [Conf]
  13. Vinod Narayanan, Vijay Pitchumani
    : A Parallel Algorithm for Fault Simulation on the Connection Machine. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:89-93 [Conf]
  14. Jean Paul Caisso, Bernard Courtois
    Fault Simulation and Test Pattern Generation at the Multiple-Valued Switch Level. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:94-101 [Conf]
  15. Fumiyasu Hirose, Koichiro Takayama, Nobuaki Kawato
    A Method to Generate Tests for Combinational Logic Circuits Using an Ultra-High-Speed Logic Simulator. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:102-107 [Conf]
  16. Teruo Tamama, Naoaki Narumi, Taiichi Otsuji, Masao Suzuki, Tsuneta Sudo
    Key Technologies for 500 MHz VLSI Test System "ULTIMATE". [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:108-113 [Conf]
  17. T. Adachi, M. Tanno, Tsuneta Sudo
    Software Environment for 500 MHz VLSI Test System "ULTIMATE". [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:114-119 [Conf]
  18. Yoshimitsu Sakagawa, Yusio Akazawa, Naoaki Narumi, Akira Yoshii, Tsuneta Sudo
    Packaging Technologies for the 500 MHz VLSI Test System "ULTIMATE". [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:120-125 [Conf]
  19. Abu S. M. Hassan, Vinod K. Agarwal, Janusz Rajski
    Testing and Diagnosis of Interconnects Using Boundary Scan Architecture. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:126-137 [Conf]
  20. Clay Gloster, Franc Brglez
    Boundary Scan with Cellular-Based Built-In Self-Test. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:138-145 [Conf]
  21. Matthias Gruetzner
    Design for Testability for Wafer-Scale Integration Interconnect Systems Design and Test Methodology. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:146-152 [Conf]
  22. Theo J. Powell, Fred Hwang, Bill Johnson
    Testability Features in the TMS370 Family of Microcomputers. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:153-160 [Conf]
  23. Luis A. Bonet
    Testability Features of a 32 Kbps ADPCM Transcoder. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:161-171 [Conf]
  24. Y. Nozuyama, A. Nishimura, J. Iwamura
    Design for Testability of a 32-Bit Microprocessor, the TX1. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:172-182 [Conf]
  25. Miron Abramovici, B. Krishnamurthy, A. Mathews, B. Rogers, M. Schulz, S. Seth, John A. Waicukauski
    What is the Path to Fast Fault Simulation? [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:183-192 [Conf]
  26. Marc Mydill
    Standardization of ATE Timing Accuracy Specifications. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:193-194 [Conf]
  27. Phil Collins
    Boundary Scan: The ATE Vendors' View. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:195-196 [Conf]
  28. Pete Fleming
    Semiconductor Perspective on Test Standards. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:197-198 [Conf]
  29. Charles R. Kime
    Impact of Testability Standards on University Research and Instruction. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:199-200 [Conf]
  30. David J. Richards
    Value of Testability Standards in Testing Commercial Products. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:201-202 [Conf]
  31. Edward J. McCluskey
    Practice and Theory. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:203-204 [Conf]
  32. Samiha Mourad
    Digital Testing, Theory and Practice. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:205-206 [Conf]
  33. Kenneth Rose
    Do the Designs Work ? [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:207-208 [Conf]
  34. Stephen M. Lea, Nigel Brown, Tim Katz, Phil Collins
    Expert System for the Functional Test Program Generation of Digital Electronic Circuit Boards. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:209-220 [Conf]
  35. Brian T. Murray, John P. Hayes
    Hierarchical Test Generation Using Precomputed Tests for Modules. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:221-229 [Conf]
  36. Gerold Affs, Reiner W. Hartenstein, Andrea Wodtko
    The KARL/KARATE System: Automatic Test Pattern Generation Based on RT Level Descriptions. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:230-235 [Conf]
  37. Hans-Joachim Wunderlich
    Multiple Distributions for Biased Random Test Patterns. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:236-244 [Conf]
  38. John A. Waicukauski, Eric Lindbloom
    Fault Detection Effectiveness of Weighted Random Patterns. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:245-255 [Conf]
  39. Fardad Siavoshi
    WTPGA : A Novel Weighted Test Pattern Generation Approach for VLSI Built-In Self-Test. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:256-262 [Conf]
  40. Dhiraj K. Pradhan, Nirmala R. Kamath
    RTRAM: Reconfigurable and Testable Multi-Bit RAM Design. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:263-278 [Conf]
  41. Pinaki Mazumder
    An On-Chip Double-Bit Error-Correcting Code for Three-Dimensional Dynamic Random-Access Memory. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:279-288 [Conf]
  42. Steve Grennan
    Application of a Commercial Data Base Management System to Memory Device Test Program Generation and Debugging. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:289-294 [Conf]
  43. Edward J. McCluskey, Fred Buelow
    IC Quality and Test Transparency. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:295-301 [Conf]
  44. Chris Salzmann, Martin Funcell, Richard Taylor
    Design for Test and the Cost of Quality. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:302-307 [Conf]
  45. W. David Ballew, Lauren M. Streb
    Elimination of Incoming Test Based Upon In-Process Failure and Repair Costs. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:308-313 [Conf]
  46. Henry Cox, André Ivanov, Vinod K. Agarwal, Janusz Rajski
    On Multiple Fault Coverage and Aliasing Probability Measures. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:314-321 [Conf]
  47. Jacob Savir, William H. McAnney
    Identification of Failing Tests with Cycling Registers. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:322-328 [Conf]
  48. Sandeep K. Gupta, Dhiraj K. Pradhan
    A New Framework for Designing and Analyzing BIST Techniques: Computation of Exact Aliasing Probability. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:329-342 [Conf]
  49. Frans P. M. Beenker, Rob Dekker, Loek Thijssen
    Fault Modeling and Test Algorithm Development. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:343-352 [Conf]
  50. Frans P. M. Beenker, Rob Dekker, Loek Thijssen
    A Realistic Self-Test Machine for Static Random Access Memories. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:353-361 [Conf]
  51. Manuel J. Raposa
    Dual Port Static RAM Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:362-368 [Conf]
  52. A. P. Dorey, B. K. Jones, Andrew M. D. Richardson, P. C. Russell, Y. Z. Xu
    Reliability Testing by Precise Electrical Measurement. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:369-373 [Conf]
  53. Masaki Hashizume, Takeomi Tamesada, Kazuhiro Yamada, Masaaki Kawakami
    Fault Detection of Combinational Circuits Based on Supply Current. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:374-380 [Conf]
  54. Birger Schneider, Peter Oestergaard
    An Advanced Data Compaction Approach for Test During Burn-In. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:381-390 [Conf]
  55. Charles D. Hechtman
    In-Circuit Test Fixture. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:391-400 [Conf]
  56. Luis Balme, Anne Mignotte, Jean-Yves Monari, Patrick Pondaven, Christophe Vaucher
    New Testing Equipment for SMT PC Boards. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:401-410 [Conf]
  57. John Arena
    Evaluating the Limitations of High-Speed Board Testers. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:411-420 [Conf]
  58. John Y. Sayah, Charles R. Kime
    : Test Scheduling for High Performance VLSI System Implementations. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:421-430 [Conf]
  59. Sandeep K. Gupta, Melvin A. Breuer, Jung-Cheun Lien
    Concurrent Control of Multiple BIT Structures. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:431-442 [Conf]
  60. C. Mani Krishna, Yann-Hang Lee
    Optimal Scheduling of Signature Analysis for VLSI Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:443-451 [Conf]
  61. John Ivie
    A High Level Approach to Integrating Design and Test. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:452-459 [Conf]
  62. Ji-en Morris Chang, William T. Krakow
    Optimal Use of Timing Resources: A Crucial Step in Test Program Generation. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:460-465 [Conf]
  63. Cristopher Merritt
    A Strategy for Generating Functional Tests from Device Simulations. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:466-474 [Conf]
  64. John Paul Shen, F. Joel Ferguson
    Extraction and Simulation of Realistic CMOS Faults Using Inductive Fault Analysis. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:475-484 [Conf]
  65. Michael Demjanenko, Shambhu J. Upadhyaya
    Dynamic Techniques for Yield Enhancement of Field Programmable Logic Arrays. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:485-491 [Conf]
  66. Eun Sei Park, Thomas W. Williams, M. Ray Mercer
    Statistical Delay Fault Coverage and Defect Level for Delay Faults. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:492-499 [Conf]
  67. Bernd Reichelmann
    Contactors for Testing at High Frequencies. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:500-501 [Conf]
  68. Melvin A. Breuer, Jung-Cheun Lien
    A Test and Maintenance Controller for a Module Containing Testable Chips. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:502-513 [Conf]
  69. Mehdi Katoozi, Mani Soma
    A BIST Design of Structured Arrays with Fault-Tolerant Layout. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:514-521 [Conf]
  70. Jon G. Udeli Jr.
    Reconfigurable Hardware for Pseudo-Exhaustive Test. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:522-530 [Conf]
  71. David L. Landis, Daniel C. Muha
    Evaluation of System BIST Using Computational Performance Measures. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:531-536 [Conf]
  72. Arthur E. Downey, Kazuhiko Matsuda
    Some New Techniques in Waveshape Capture and Analysis. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:537-546 [Conf]
  73. Patrick M. Powers
    A High-Resolution Waveform Analysis Tool. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:547-550 [Conf]
  74. Cihan Tinaztepe, Bülent Özgüç
    Functional Test Program Generation Through interactive Graphics. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:551-558 [Conf]
  75. Yuichi Kawabata, Masami Maruyama, Al Tejeda
    PGTOOL: An Automatic Interactive Program Generation Tool for Testing New-Generation Memory Devices. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:559-568 [Conf]
  76. William H. Nicholls, Mani Soma
    Fault Bundling: Reducing Machine Evaluation Activity in Hierarchical Concurrent Fault Simulation. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:569-573 [Conf]
  77. Deborah Machlin, David Gross, Sudhir Kadkade, Ernst Ulrich
    Switch-Level Concurrent Fault Simulation Based on a General Purpose List Traversal Mechanism. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:574-581 [Conf]
  78. Steven P. Smith, Bill Underwood, M. Ray Mercer
    D^3FS: A Demand Driven Deductive Fault Simulator. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:582-592 [Conf]
  79. Tapan J. Chakraborty, Sumit Ghosh
    On Behavior Fault Modeling for Combinational Digital Designs. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:593-600 [Conf]
  80. Brian Leslie, Farid Matta
    Membrane Probe Card Technology (the Future for High Performance Wafer Test). [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:601-607 [Conf]
  81. C. Barsotti, S. Tremaine, M. Bonham
    Very High Density Probing. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:608-614 [Conf]
  82. T. Roland Fredriksen, David Grano
    New Automated Prober Support for High Pincount Test Heads. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:615-620 [Conf]
  83. Srinivas Devadas, Hi-Keung Tony Ma, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli
    Synthesis and Optimization Procedures for Fully and Easily Testable Sequential Machines. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:621-630 [Conf]
  84. Desmond F. D'Souza
    A Knowledge Representation Scheme for DFT. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:631-641 [Conf]
  85. Hideo Fujiwara, Osamu Fujisawa, Kazunori Hikone
    Enhancing Random-Pattern Coverage of Programmable Logic Arrays via Masking Technique. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:642-648 [Conf]
  86. Gary D. Culbertson
    Managing the ASIC Design to Test Process. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:649-656 [Conf]
  87. Eric Archambeau, Ken Van Egmond
    Built-In Test Compiler in an ASIC Environment. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:657-664 [Conf]
  88. A. Walter, Y. Kleinman, L. Edelshteyn, J. Gartner
    An Expert Test Program Generation System for Per-Pin Testers. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:665-668 [Conf]
  89. Samy Makar, Edward J. McCluskey
    On the Testing of Multiplexers. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:669-679 [Conf]
  90. Sandip Kundu, Sudhakar M. Reddy
    Robust Tests for Parity Trees. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:680-687 [Conf]
  91. Henry Cox, Janusz Rajski
    Stuck-Open and Transition Fault Testing in CMOS Complex Gates. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:688-694 [Conf]
  92. G. Tremblay, P. Meyrueix, J. C. Peuzin
    Optical Testing of Printed Circuit Boards. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:695-699 [Conf]
  93. Francois J. Henley, Hee-June Choi
    Test Head Design Using Electro-Optic Receivers and GaAs Pin Electronics for a Gigahertz Production Test System. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:700-709 [Conf]
  94. Dean J. Kratzer, Steve Barton, Francois J. Henley, David A. Plomgrem
    High-Speed Pattern Generator and GaAs Pin : Electronics for a Gigahertz Production Test System. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:710-718 [Conf]
  95. M. M. Pradhan, E. J. O'Brien, S. L. Lam, James Beausang
    Circular BIST with Partial Scan. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:719-729 [Conf]
  96. Hi-Keung Tony Ma, A. Richard Newton, Srinivas Devadas, Alberto L. Sangiovanni-Vincentelli
    An Incomplete Scan Design Approach to Test Generation for Sequential Machines. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:730-734 [Conf]
  97. S. Bhawmick, M. S. Khaira, P. P. Mishra, A. Das, A. Dasgupta, P. Palchaudhury
    Threading of Multiple Scan Paths in a VLSI Circuit. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:735-743 [Conf]
  98. John Beck, James Pappas, Robert Rose, Larry Seiler
    Integrated Test Logic for Video ICs. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:744-751 [Conf]
  99. John L. Russo
    Flexible Deep Memory Architecture Aids Program Development. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:752-754 [Conf]
  100. Eric Rosenfeld
    Timing Generation for DSP Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:755-763 [Conf]
  101. Gabriel M. Silberman, Ilan Y. Spillinger
    G-RIDDLE : A Formal Analysis of Logic Designs Condiucive to the Acceleration of Backtracing. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:764-772 [Conf]
  102. Steven D. Millman, Edward J. McCluskey
    Detecting Bridging Faults with Stuck-at Test Sets. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:773-783 [Conf]
  103. Markus Robinson, Janusz Rajski
    An Algorithmic Branch and Bound Method for PLA Test Pattern Generation. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:784-795 [Conf]
  104. Chi W. Yau, Song-Lin Chang, Bruce F. Jordan, Joe J. Schwermann, Joan A. Wellman
    Trouble-Shooting: A Key to Process Improvement. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:796-803 [Conf]
  105. Raymond J. Balzer, Greg A. Larsen
    Predicting and Obtaining High Final Test Yields. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:804-815 [Conf]
  106. Neil Hutchinson
    CIM , Electronics Manufacturing and ATE. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:816-822 [Conf]
  107. Kenneth D. Wagner, Thomas W. Williams
    Design for Testability of Mixed Signal Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:823-828 [Conf]
  108. Gertjan J. Hemink, Berend W. Meijer, Hans G. Kerkhoff
    TASTE: A Tool for Analog System Testability Evaluation. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:829-838 [Conf]
  109. M. J. Marlett, Jacob A. Abraham
    DC_IATP : An Iterative Analog Circuit Test Generation Program for Generating DC Single Pattern Tests. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:839-844 [Conf]
  110. Ankan K. Pramanick, Sudhakar M. Reddy
    On the Detection of Delay Faults. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:845-856 [Conf]
  111. Vijay S. Iyengar, Barry K. Rosen, Ilan Y. Spillinger
    Delay Test Generation 1: Concepts and Coverage Metrics. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:857-866 [Conf]
  112. Vijay S. Iyengar, Barry K. Rosen, Ilan Y. Spillinger
    Delay Test Generation 2: Algebra and Algorithms. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:867-876 [Conf]
  113. Stephen R. Demba, Ernst Ulrich, Karen Panetta, David Giramma
    Experiences with Concurrent Fault Simulation of Diagnostic Programs. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:877-883 [Conf]
  114. Hidetoshi Tanaka, Masato Kawai, Izumi Sugasaki, Tadanobu Hakuba
    System Level Fault Dictionary Generation. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:884-887 [Conf]
  115. Stephen Y. H. Su, Hede Ma
    Designs for Diagnosability and Reliability in VLSI Systems. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:888-897 [Conf]
  116. M. Melgara, M. Battu, P. Garino, J. Dowe, Y. J. Vernay, M. Marzouki, F. Boland
    Automatic Location of IC Design Errors Using Beam System. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:898-907 [Conf]
  117. Hironobu Niijima, Yasuo Tokunaga, Shouichi Koshizuka, Kazuo Yakuwa, Péter Fazekas, Mathias Sturm, Hans-Peter Feuerbaum
    Electron Beam Tester Integrated into a VLSI Tester. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:908-913 [Conf]
  118. Kent D. Wilken, John Paul Shen
    Continuous Signature Monitoring: Efficient Concurrent-Detection of Processor Control Errors. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:914-925 [Conf]
  119. Lawrence P. Holmquist, Larry L. Kinney
    Error Detection with Latency in Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:926-933 [Conf]
  120. Leon J. Sigal, Charles R. Kime
    Concurrent Off-Phase Built-in Self-Test of Dormant Logic. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:934-941 [Conf]
  121. Mark Marshall
    Techniques for User Testing of the 68882. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:942-947 [Conf]
  122. Kenneth R. Stuchlik
    Simultaneous Switching Noise Evaluation of Advanced CMOS Logic (ACL). [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:948-957 [Conf]
  123. Douglas B. Arnett, K. S. Bhaskar
    Emulative Testing at the Bus Speed Limit. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:958-968 [Conf]
  124. Donald H. Merliho, John Hadjilogiou
    Built-In Test Strategy for Next Generation Military Avionic Hardware. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:969-975 [Conf]
  125. Bulent I. Dervisoglu
    Using Scan Technology for Debug and Diagnostics in a Workstation Environment. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:976-986 [Conf]
  126. Mike Ricchetti, John Hoglund
    Scan Diagnostic Strategy for the Series 10000 Prism Workstation. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:987-992 [Conf]
  127. Jill J. Hallenbeck, Nick Kanopoulos, Nagesh Vasanthavada, James W. Watterson
    CAD Tools for Supporting System Design for Testability. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:993- [Conf]
  128. Cuong Bui
    Testability Using Random Access Test Register. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:994-995 [Conf]
  129. Michael Treseler
    Designing State Machines for Testability. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:996- [Conf]
  130. Samiha Mourad, Edward J. McCluskey
    On Benchmarking Digital Testing Systems. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:997- [Conf]
  131. Peter N. Marinos
    The Non-Linear Feedback Shift-Register as a Built-In Self-Test (BIST) Resource. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:998- [Conf]
  132. David Stannard, Bozena Kaminska
    Detection of Hard Faults in a Combinational Circuit Using Budget Constraints. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:999- [Conf]
  133. Jon G. Udeli Jr., Edward J. McCluskey
    Partial Hardware Partitioning: A New Pseudo-Exhaustive Test Implementation. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:1000- [Conf]
  134. Sami A. Al-Arian, Kevin A. Kwiat
    Defining a Standard for Fault Simulator Evaluation. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:1001- [Conf]
  135. G. J. Hill, B. C. Roberts, C. P. Strudwick
    Determination of Safe Back-Driving Currents in Bond Wires and Dice. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:1002- [Conf]
NOTICE1
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NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
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