Conferences in DBLP
A. Blanton Godfrey Managing Quality : Today's Opportunities, Tomorrow's Challenges. [Citation Graph (0, 0)][DBLP ] Conf ] Lutz P. Henckels Scan Path and Beyond : The Road to Improved ASIC Testability. [Citation Graph (0, 0)][DBLP ] Conf ] Alberto L. Sangiovanni-Vincentelli Optimal Logic Synthesis and Testability : Two Sides of the Same Coin. [Citation Graph (0, 0)][DBLP ] Conf ] Sheng-Jen Tsai , Charles D. Hechtman GaAs Driver and Sensor for a High-Speed Test System. [Citation Graph (0, 0)][DBLP ] Conf ] Christopher W. Branson , Don Murray , Steve Sullivan Integrated Pin Electronics for a VLSI Test System. [Citation Graph (0, 0)][DBLP ] Conf ] J. R. Birchak , H. K. Haill Characteristic Impedance and Coupling Coefficients for Multilayer PC Boards. [Citation Graph (0, 0)][DBLP ] Conf ] Robert E. McAuliffe Practical Production Testing of ISDN Circuit Boards. [Citation Graph (0, 0)][DBLP ] Conf ] Mark G. Karpovsky , Prawat Nagvajara Board-Level Diagnosis by Signature Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen Y. H. Su , Hede Ma Fault Isolation in Grey Systems. [Citation Graph (0, 0)][DBLP ] Conf ] C. Bellon , Raoul Velazco , Haissam Ziade Analysis of Experimental Results on Functional Testing and Diagnosis of Complex Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Hans Peter Klug Microprocessor Testing by Instruction Sequences Derived from Random Patterns. [Citation Graph (0, 0)][DBLP ] Conf ] Janusz Sosnowski Detection of Control Flow Errors Using Signature and Checking Instructions. [Citation Graph (0, 0)][DBLP ] Conf ] Vinod Narayanan , Vijay Pitchumani : A Parallel Algorithm for Fault Simulation on the Connection Machine. [Citation Graph (0, 0)][DBLP ] Conf ] Jean Paul Caisso , Bernard Courtois Fault Simulation and Test Pattern Generation at the Multiple-Valued Switch Level. [Citation Graph (0, 0)][DBLP ] Conf ] Fumiyasu Hirose , Koichiro Takayama , Nobuaki Kawato A Method to Generate Tests for Combinational Logic Circuits Using an Ultra-High-Speed Logic Simulator. [Citation Graph (0, 0)][DBLP ] Conf ] Teruo Tamama , Naoaki Narumi , Taiichi Otsuji , Masao Suzuki , Tsuneta Sudo Key Technologies for 500 MHz VLSI Test System "ULTIMATE". [Citation Graph (0, 0)][DBLP ] Conf ] T. Adachi , M. Tanno , Tsuneta Sudo Software Environment for 500 MHz VLSI Test System "ULTIMATE". [Citation Graph (0, 0)][DBLP ] Conf ] Yoshimitsu Sakagawa , Yusio Akazawa , Naoaki Narumi , Akira Yoshii , Tsuneta Sudo Packaging Technologies for the 500 MHz VLSI Test System "ULTIMATE". [Citation Graph (0, 0)][DBLP ] Conf ] Abu S. M. Hassan , Vinod K. Agarwal , Janusz Rajski Testing and Diagnosis of Interconnects Using Boundary Scan Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Clay Gloster , Franc Brglez Boundary Scan with Cellular-Based Built-In Self-Test. [Citation Graph (0, 0)][DBLP ] Conf ] Matthias Gruetzner Design for Testability for Wafer-Scale Integration Interconnect Systems Design and Test Methodology. [Citation Graph (0, 0)][DBLP ] Conf ] Theo J. Powell , Fred Hwang , Bill Johnson Testability Features in the TMS370 Family of Microcomputers. [Citation Graph (0, 0)][DBLP ] Conf ] Luis A. Bonet Testability Features of a 32 Kbps ADPCM Transcoder. [Citation Graph (0, 0)][DBLP ] Conf ] Y. Nozuyama , A. Nishimura , J. Iwamura Design for Testability of a 32-Bit Microprocessor, the TX1. [Citation Graph (0, 0)][DBLP ] Conf ] Miron Abramovici , B. Krishnamurthy , A. Mathews , B. Rogers , M. Schulz , S. Seth , John A. Waicukauski What is the Path to Fast Fault Simulation? [Citation Graph (0, 0)][DBLP ] Conf ] Marc Mydill Standardization of ATE Timing Accuracy Specifications. [Citation Graph (0, 0)][DBLP ] Conf ] Phil Collins Boundary Scan: The ATE Vendors' View. [Citation Graph (0, 0)][DBLP ] Conf ] Pete Fleming Semiconductor Perspective on Test Standards. [Citation Graph (0, 0)][DBLP ] Conf ] Charles R. Kime Impact of Testability Standards on University Research and Instruction. [Citation Graph (0, 0)][DBLP ] Conf ] David J. Richards Value of Testability Standards in Testing Commercial Products. [Citation Graph (0, 0)][DBLP ] Conf ] Edward J. McCluskey Practice and Theory. [Citation Graph (0, 0)][DBLP ] Conf ] Samiha Mourad Digital Testing, Theory and Practice. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth Rose Do the Designs Work ? [Citation Graph (0, 0)][DBLP ] Conf ] Stephen M. Lea , Nigel Brown , Tim Katz , Phil Collins Expert System for the Functional Test Program Generation of Digital Electronic Circuit Boards. [Citation Graph (0, 0)][DBLP ] Conf ] Brian T. Murray , John P. Hayes Hierarchical Test Generation Using Precomputed Tests for Modules. [Citation Graph (0, 0)][DBLP ] Conf ] Gerold Affs , Reiner W. Hartenstein , Andrea Wodtko The KARL/KARATE System: Automatic Test Pattern Generation Based on RT Level Descriptions. [Citation Graph (0, 0)][DBLP ] Conf ] Hans-Joachim Wunderlich Multiple Distributions for Biased Random Test Patterns. [Citation Graph (0, 0)][DBLP ] Conf ] John A. Waicukauski , Eric Lindbloom Fault Detection Effectiveness of Weighted Random Patterns. [Citation Graph (0, 0)][DBLP ] Conf ] Fardad Siavoshi WTPGA : A Novel Weighted Test Pattern Generation Approach for VLSI Built-In Self-Test. [Citation Graph (0, 0)][DBLP ] Conf ] Dhiraj K. Pradhan , Nirmala R. Kamath RTRAM: Reconfigurable and Testable Multi-Bit RAM Design. [Citation Graph (0, 0)][DBLP ] Conf ] Pinaki Mazumder An On-Chip Double-Bit Error-Correcting Code for Three-Dimensional Dynamic Random-Access Memory. [Citation Graph (0, 0)][DBLP ] Conf ] Steve Grennan Application of a Commercial Data Base Management System to Memory Device Test Program Generation and Debugging. [Citation Graph (0, 0)][DBLP ] Conf ] Edward J. McCluskey , Fred Buelow IC Quality and Test Transparency. [Citation Graph (0, 0)][DBLP ] Conf ] Chris Salzmann , Martin Funcell , Richard Taylor Design for Test and the Cost of Quality. [Citation Graph (0, 0)][DBLP ] Conf ] W. David Ballew , Lauren M. Streb Elimination of Incoming Test Based Upon In-Process Failure and Repair Costs. [Citation Graph (0, 0)][DBLP ] Conf ] Henry Cox , André Ivanov , Vinod K. Agarwal , Janusz Rajski On Multiple Fault Coverage and Aliasing Probability Measures. [Citation Graph (0, 0)][DBLP ] Conf ] Jacob Savir , William H. McAnney Identification of Failing Tests with Cycling Registers. [Citation Graph (0, 0)][DBLP ] Conf ] Sandeep K. Gupta , Dhiraj K. Pradhan A New Framework for Designing and Analyzing BIST Techniques: Computation of Exact Aliasing Probability. [Citation Graph (0, 0)][DBLP ] Conf ] Frans P. M. Beenker , Rob Dekker , Loek Thijssen Fault Modeling and Test Algorithm Development. [Citation Graph (0, 0)][DBLP ] Conf ] Frans P. M. Beenker , Rob Dekker , Loek Thijssen A Realistic Self-Test Machine for Static Random Access Memories. [Citation Graph (0, 0)][DBLP ] Conf ] Manuel J. Raposa Dual Port Static RAM Testing. [Citation Graph (0, 0)][DBLP ] Conf ] A. P. Dorey , B. K. Jones , Andrew M. D. Richardson , P. C. Russell , Y. Z. Xu Reliability Testing by Precise Electrical Measurement. [Citation Graph (0, 0)][DBLP ] Conf ] Masaki Hashizume , Takeomi Tamesada , Kazuhiro Yamada , Masaaki Kawakami Fault Detection of Combinational Circuits Based on Supply Current. [Citation Graph (0, 0)][DBLP ] Conf ] Birger Schneider , Peter Oestergaard An Advanced Data Compaction Approach for Test During Burn-In. [Citation Graph (0, 0)][DBLP ] Conf ] Charles D. Hechtman In-Circuit Test Fixture. [Citation Graph (0, 0)][DBLP ] Conf ] Luis Balme , Anne Mignotte , Jean-Yves Monari , Patrick Pondaven , Christophe Vaucher New Testing Equipment for SMT PC Boards. [Citation Graph (0, 0)][DBLP ] Conf ] John Arena Evaluating the Limitations of High-Speed Board Testers. [Citation Graph (0, 0)][DBLP ] Conf ] John Y. Sayah , Charles R. Kime : Test Scheduling for High Performance VLSI System Implementations. [Citation Graph (0, 0)][DBLP ] Conf ] Sandeep K. Gupta , Melvin A. Breuer , Jung-Cheun Lien Concurrent Control of Multiple BIT Structures. [Citation Graph (0, 0)][DBLP ] Conf ] C. Mani Krishna , Yann-Hang Lee Optimal Scheduling of Signature Analysis for VLSI Testing. [Citation Graph (0, 0)][DBLP ] Conf ] John Ivie A High Level Approach to Integrating Design and Test. [Citation Graph (0, 0)][DBLP ] Conf ] Ji-en Morris Chang , William T. Krakow Optimal Use of Timing Resources: A Crucial Step in Test Program Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Cristopher Merritt A Strategy for Generating Functional Tests from Device Simulations. [Citation Graph (0, 0)][DBLP ] Conf ] John Paul Shen , F. Joel Ferguson Extraction and Simulation of Realistic CMOS Faults Using Inductive Fault Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Demjanenko , Shambhu J. Upadhyaya Dynamic Techniques for Yield Enhancement of Field Programmable Logic Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Eun Sei Park , Thomas W. Williams , M. Ray Mercer Statistical Delay Fault Coverage and Defect Level for Delay Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Bernd Reichelmann Contactors for Testing at High Frequencies. [Citation Graph (0, 0)][DBLP ] Conf ] Melvin A. Breuer , Jung-Cheun Lien A Test and Maintenance Controller for a Module Containing Testable Chips. [Citation Graph (0, 0)][DBLP ] Conf ] Mehdi Katoozi , Mani Soma A BIST Design of Structured Arrays with Fault-Tolerant Layout. [Citation Graph (0, 0)][DBLP ] Conf ] Jon G. Udeli Jr. Reconfigurable Hardware for Pseudo-Exhaustive Test. [Citation Graph (0, 0)][DBLP ] Conf ] David L. Landis , Daniel C. Muha Evaluation of System BIST Using Computational Performance Measures. [Citation Graph (0, 0)][DBLP ] Conf ] Arthur E. Downey , Kazuhiko Matsuda Some New Techniques in Waveshape Capture and Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Patrick M. Powers A High-Resolution Waveform Analysis Tool. [Citation Graph (0, 0)][DBLP ] Conf ] Cihan Tinaztepe , Bülent Özgüç Functional Test Program Generation Through interactive Graphics. [Citation Graph (0, 0)][DBLP ] Conf ] Yuichi Kawabata , Masami Maruyama , Al Tejeda PGTOOL: An Automatic Interactive Program Generation Tool for Testing New-Generation Memory Devices. [Citation Graph (0, 0)][DBLP ] Conf ] William H. Nicholls , Mani Soma Fault Bundling: Reducing Machine Evaluation Activity in Hierarchical Concurrent Fault Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Deborah Machlin , David Gross , Sudhir Kadkade , Ernst Ulrich Switch-Level Concurrent Fault Simulation Based on a General Purpose List Traversal Mechanism. [Citation Graph (0, 0)][DBLP ] Conf ] Steven P. Smith , Bill Underwood , M. Ray Mercer D^3FS: A Demand Driven Deductive Fault Simulator. [Citation Graph (0, 0)][DBLP ] Conf ] Tapan J. Chakraborty , Sumit Ghosh On Behavior Fault Modeling for Combinational Digital Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Brian Leslie , Farid Matta Membrane Probe Card Technology (the Future for High Performance Wafer Test). [Citation Graph (0, 0)][DBLP ] Conf ] C. Barsotti , S. Tremaine , M. Bonham Very High Density Probing. [Citation Graph (0, 0)][DBLP ] Conf ] T. Roland Fredriksen , David Grano New Automated Prober Support for High Pincount Test Heads. [Citation Graph (0, 0)][DBLP ] Conf ] Srinivas Devadas , Hi-Keung Tony Ma , A. Richard Newton , Alberto L. Sangiovanni-Vincentelli Synthesis and Optimization Procedures for Fully and Easily Testable Sequential Machines. [Citation Graph (0, 0)][DBLP ] Conf ] Desmond F. D'Souza A Knowledge Representation Scheme for DFT. [Citation Graph (0, 0)][DBLP ] Conf ] Hideo Fujiwara , Osamu Fujisawa , Kazunori Hikone Enhancing Random-Pattern Coverage of Programmable Logic Arrays via Masking Technique. [Citation Graph (0, 0)][DBLP ] Conf ] Gary D. Culbertson Managing the ASIC Design to Test Process. [Citation Graph (0, 0)][DBLP ] Conf ] Eric Archambeau , Ken Van Egmond Built-In Test Compiler in an ASIC Environment. [Citation Graph (0, 0)][DBLP ] Conf ] A. Walter , Y. Kleinman , L. Edelshteyn , J. Gartner An Expert Test Program Generation System for Per-Pin Testers. [Citation Graph (0, 0)][DBLP ] Conf ] Samy Makar , Edward J. McCluskey On the Testing of Multiplexers. [Citation Graph (0, 0)][DBLP ] Conf ] Sandip Kundu , Sudhakar M. Reddy Robust Tests for Parity Trees. [Citation Graph (0, 0)][DBLP ] Conf ] Henry Cox , Janusz Rajski Stuck-Open and Transition Fault Testing in CMOS Complex Gates. [Citation Graph (0, 0)][DBLP ] Conf ] G. Tremblay , P. Meyrueix , J. C. Peuzin Optical Testing of Printed Circuit Boards. [Citation Graph (0, 0)][DBLP ] Conf ] Francois J. Henley , Hee-June Choi Test Head Design Using Electro-Optic Receivers and GaAs Pin Electronics for a Gigahertz Production Test System. [Citation Graph (0, 0)][DBLP ] Conf ] Dean J. Kratzer , Steve Barton , Francois J. Henley , David A. Plomgrem High-Speed Pattern Generator and GaAs Pin : Electronics for a Gigahertz Production Test System. [Citation Graph (0, 0)][DBLP ] Conf ] M. M. Pradhan , E. J. O'Brien , S. L. Lam , James Beausang Circular BIST with Partial Scan. [Citation Graph (0, 0)][DBLP ] Conf ] Hi-Keung Tony Ma , A. Richard Newton , Srinivas Devadas , Alberto L. Sangiovanni-Vincentelli An Incomplete Scan Design Approach to Test Generation for Sequential Machines. [Citation Graph (0, 0)][DBLP ] Conf ] S. Bhawmick , M. S. Khaira , P. P. Mishra , A. Das , A. Dasgupta , P. Palchaudhury Threading of Multiple Scan Paths in a VLSI Circuit. [Citation Graph (0, 0)][DBLP ] Conf ] John Beck , James Pappas , Robert Rose , Larry Seiler Integrated Test Logic for Video ICs. [Citation Graph (0, 0)][DBLP ] Conf ] John L. Russo Flexible Deep Memory Architecture Aids Program Development. [Citation Graph (0, 0)][DBLP ] Conf ] Eric Rosenfeld Timing Generation for DSP Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Gabriel M. Silberman , Ilan Y. Spillinger G-RIDDLE : A Formal Analysis of Logic Designs Condiucive to the Acceleration of Backtracing. [Citation Graph (0, 0)][DBLP ] Conf ] Steven D. Millman , Edward J. McCluskey Detecting Bridging Faults with Stuck-at Test Sets. [Citation Graph (0, 0)][DBLP ] Conf ] Markus Robinson , Janusz Rajski An Algorithmic Branch and Bound Method for PLA Test Pattern Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Chi W. Yau , Song-Lin Chang , Bruce F. Jordan , Joe J. Schwermann , Joan A. Wellman Trouble-Shooting: A Key to Process Improvement. [Citation Graph (0, 0)][DBLP ] Conf ] Raymond J. Balzer , Greg A. Larsen Predicting and Obtaining High Final Test Yields. [Citation Graph (0, 0)][DBLP ] Conf ] Neil Hutchinson CIM , Electronics Manufacturing and ATE. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth D. Wagner , Thomas W. Williams Design for Testability of Mixed Signal Integrated Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Gertjan J. Hemink , Berend W. Meijer , Hans G. Kerkhoff TASTE: A Tool for Analog System Testability Evaluation. [Citation Graph (0, 0)][DBLP ] Conf ] M. J. Marlett , Jacob A. Abraham DC_IATP : An Iterative Analog Circuit Test Generation Program for Generating DC Single Pattern Tests. [Citation Graph (0, 0)][DBLP ] Conf ] Ankan K. Pramanick , Sudhakar M. Reddy On the Detection of Delay Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Vijay S. Iyengar , Barry K. Rosen , Ilan Y. Spillinger Delay Test Generation 1: Concepts and Coverage Metrics. [Citation Graph (0, 0)][DBLP ] Conf ] Vijay S. Iyengar , Barry K. Rosen , Ilan Y. Spillinger Delay Test Generation 2: Algebra and Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen R. Demba , Ernst Ulrich , Karen Panetta , David Giramma Experiences with Concurrent Fault Simulation of Diagnostic Programs. [Citation Graph (0, 0)][DBLP ] Conf ] Hidetoshi Tanaka , Masato Kawai , Izumi Sugasaki , Tadanobu Hakuba System Level Fault Dictionary Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen Y. H. Su , Hede Ma Designs for Diagnosability and Reliability in VLSI Systems. [Citation Graph (0, 0)][DBLP ] Conf ] M. Melgara , M. Battu , P. Garino , J. Dowe , Y. J. Vernay , M. Marzouki , F. Boland Automatic Location of IC Design Errors Using Beam System. [Citation Graph (0, 0)][DBLP ] Conf ] Hironobu Niijima , Yasuo Tokunaga , Shouichi Koshizuka , Kazuo Yakuwa , Péter Fazekas , Mathias Sturm , Hans-Peter Feuerbaum Electron Beam Tester Integrated into a VLSI Tester. [Citation Graph (0, 0)][DBLP ] Conf ] Kent D. Wilken , John Paul Shen Continuous Signature Monitoring: Efficient Concurrent-Detection of Processor Control Errors. [Citation Graph (0, 0)][DBLP ] Conf ] Lawrence P. Holmquist , Larry L. Kinney Error Detection with Latency in Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Leon J. Sigal , Charles R. Kime Concurrent Off-Phase Built-in Self-Test of Dormant Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Mark Marshall Techniques for User Testing of the 68882. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth R. Stuchlik Simultaneous Switching Noise Evaluation of Advanced CMOS Logic (ACL). [Citation Graph (0, 0)][DBLP ] Conf ] Douglas B. Arnett , K. S. Bhaskar Emulative Testing at the Bus Speed Limit. [Citation Graph (0, 0)][DBLP ] Conf ] Donald H. Merliho , John Hadjilogiou Built-In Test Strategy for Next Generation Military Avionic Hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Bulent I. Dervisoglu Using Scan Technology for Debug and Diagnostics in a Workstation Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Mike Ricchetti , John Hoglund Scan Diagnostic Strategy for the Series 10000 Prism Workstation. [Citation Graph (0, 0)][DBLP ] Conf ] Jill J. Hallenbeck , Nick Kanopoulos , Nagesh Vasanthavada , James W. Watterson CAD Tools for Supporting System Design for Testability. [Citation Graph (0, 0)][DBLP ] Conf ] Cuong Bui Testability Using Random Access Test Register. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Treseler Designing State Machines for Testability. [Citation Graph (0, 0)][DBLP ] Conf ] Samiha Mourad , Edward J. McCluskey On Benchmarking Digital Testing Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Peter N. Marinos The Non-Linear Feedback Shift-Register as a Built-In Self-Test (BIST) Resource. [Citation Graph (0, 0)][DBLP ] Conf ] David Stannard , Bozena Kaminska Detection of Hard Faults in a Combinational Circuit Using Budget Constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Jon G. Udeli Jr. , Edward J. McCluskey Partial Hardware Partitioning: A New Pseudo-Exhaustive Test Implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Sami A. Al-Arian , Kevin A. Kwiat Defining a Standard for Fault Simulator Evaluation. [Citation Graph (0, 0)][DBLP ] Conf ] G. J. Hill , B. C. Roberts , C. P. Strudwick Determination of Safe Back-Driving Currents in Bond Wires and Dice. [Citation Graph (0, 0)][DBLP ] Conf ] 