Conferences in DBLP
Andrew Rappaport The Great ATE Robbery. [Citation Graph (0, 0)][DBLP ] Conf ] Ben Bennetts Progress in DFT: A Personal View. [Citation Graph (0, 0)][DBLP ] Conf ] Uwe Gläser , Uwe Hübner , Heinrich Theodor Vierhaus Mixed Level Hierarchical Test Generation for Transition Faults and Overcurrent Related Defects. [Citation Graph (0, 0)][DBLP ] Conf ] Sandip Kundu , Leendert M. Huisman , Indira Nair , Vijay S. Iyengar , Lakshmi N. Reddy A Small Test Generator for Large Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Kazumi Hatayama , Kazunori Hikone , Mitsuji Ikeda , Terumine Hayashi Sequential Test Generation Based on Real-Value Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Jaushin Lee , Janak H. Patel An Instruction Sequence Assembling Methodology for Testing Microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Jim Chapman High-Performance CMOS-Based VLSI Testers: Timing Control and Compensation. [Citation Graph (0, 0)][DBLP ] Conf ] Akinori Maeda The Advanced Test System Architecture Provides Fast and Accurate Test for a High Resolution ADC. [Citation Graph (0, 0)][DBLP ] Conf ] Matthew L. Fichtenbaum , Robert J. Muller A VXI Driver-Sensor Instrument with Large Tester Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Wayne T. Daniel Design Verification of a High Density Computer Using IEEE 1149.1. [Citation Graph (0, 0)][DBLP ] Conf ] John Andrews IEEE 1149.1 Applied to Mixed TTL-ECL and Differential Logic. [Citation Graph (0, 0)][DBLP ] Conf ] E. Kofi Vida-Torku Impact of Boundary Scan Design on Delay Test. [Citation Graph (0, 0)][DBLP ] Conf ] Barry Caldwell , Tom Langford Is IEEE 1149.1 Boundary Scan Cost Effective: A Simple Case Study. [Citation Graph (0, 0)][DBLP ] Conf ] Jos van Sas , Francky Catthoor , Hugo De Man Optimized BIST Strategies for Programmable Data Paths Based on Cellular Automata. [Citation Graph (0, 0)][DBLP ] Conf ] Sybille Hellebrand , Steffen Tarnick , Bernard Courtois , Janusz Rajski Generation of Vector Patterns Through Reseeding of Multipe-Polynominal Linear Feedback Shift Registers. [Citation Graph (0, 0)][DBLP ] Conf ] Albrecht P. Stroele Self-Test Scheduling with Bounded Test Execution. [Citation Graph (0, 0)][DBLP ] Conf ] Sandeep K. Gupta , Dhiraj K. Pradhan Can Concurrent Checkers Help BIST? [Citation Graph (0, 0)][DBLP ] Conf ] Roger Perry IDDQ Testing in CMOS Digital ASIC's - Putting it All Together. [Citation Graph (0, 0)][DBLP ] Conf ] K. Sawada , S. Kayano An Evaluation of IDDQ Versus Conventional Testing for CMOS Sea-of-Gate IC's. [Citation Graph (0, 0)][DBLP ] Conf ] Peter C. Maxwell , Robert C. Aitken , Vic Johansen , Inshen Chiang The Effectiveness of IDDQ , Functional and Scan Tests: How Many Fault Coverages Do We Need? [Citation Graph (0, 0)][DBLP ] Conf ] Elizabeth M. Rudnick , W. Kent Fuchs , Janak H. Patel Diagnostic Fault Simulation of Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Gianpiero Cabodi , Paolo Camurati , Fulvio Corno , Paolo Prinetto , Matteo Sonza Reorda Sequential Circuit Diagnosis Based on Formal Verification Techniques. [Citation Graph (0, 0)][DBLP ] Conf ] John Moondanos , Jacob A. Abraham Sequential Redundancy Identification Using Verification Techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Lee Whetsel A Proposed Method of Accessing 1149.1 in a Backplane Environment. [Citation Graph (0, 0)][DBLP ] Conf ] José M. M. Ferreira , Filipe S. Pinto , José Silva Matos A Boundary Scan Test Controller for Hierarchical BIST. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen C. Hilla Boundary Scan Testing for Multichip Modules. [Citation Graph (0, 0)][DBLP ] Conf ] Frank Bouwman , Steven Oostdijk , Rudi Stans , Ben Bennetts , Frans P. M. Beenker Macro Testability: The Results of Production Device Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Haruo Kato CCD Image Sensor Test Using Cellular Automation-Type Pattern Recognition System. [Citation Graph (0, 0)][DBLP ] Conf ] Ran Edeleman , Ishai Kreiser Correlation of Capacitive Load Delay. [Citation Graph (0, 0)][DBLP ] Conf ] David C. Keezer MCM Test Using Available Technology. [Citation Graph (0, 0)][DBLP ] Conf ] Keith Baker Time-to-Market: An Issue in Mixed-signal vs. Analogue. [Citation Graph (0, 0)][DBLP ] Conf ] Richard S. Levy Does Object-Oriented Programming Fit in the Real World of ATE? [Citation Graph (0, 0)][DBLP ] Conf ] James R. Ward The Reality of Object Oriented Solutions for ATE. [Citation Graph (0, 0)][DBLP ] Conf ] T. Yamada , Akihiro Fujiwara , Michiko Inoue COM (Cost Oriented Memory) Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Robert Trahan , Rex Kiang An Analysis of the Die Testing Process Using Taguchi Techniques and Circuit Diagnostics. [Citation Graph (0, 0)][DBLP ] Conf ] Robert James Montoya Using Tester Repeatability to Improve Yields. [Citation Graph (0, 0)][DBLP ] Conf ] Sarkis Ourfalian Successful Implementation of SPC in Semiconductor Final Test. [Citation Graph (0, 0)][DBLP ] Conf ] Hideo Fujiwara , Akihiro Yamamoto Parity-Scan Design to Reduce the Cost of Test Application. [Citation Graph (0, 0)][DBLP ] Conf ] Sridhar Narayanan , Charles Njinda , Melvin A. Breuer Optimal Sequencing of Scan Registers. [Citation Graph (0, 0)][DBLP ] Conf ] Sungju Park , Sheldon B. Akers A Graph Theoretic Approach to Partial Scan Design by K-Cycle Elimination. [Citation Graph (0, 0)][DBLP ] Conf ] Shoba Krishnan , Sondes Sahli , Chin-Long Wey Test Generation and Concurrent Error Detection in Current-Mode A/D Converters. [Citation Graph (0, 0)][DBLP ] Conf ] Masao Sugai , Takayuki Nakatani AC Dynamic Testing of 20Bit Sigma-Delta Over-Sampling D/A Converter on a Mixed Signal Test System. [Citation Graph (0, 0)][DBLP ] Conf ] Frans de Jong , Adriaan J. de Lind van Wijngaarden Memory Interconnection Test at Board Level. [Citation Graph (0, 0)][DBLP ] Conf ] Shuichi Kameyama , Hideyuki Ohara , Chihiro Endo , Naoki Takayama Interconnect and Delay Testing with a 4800-Pin Board Tester. [Citation Graph (0, 0)][DBLP ] Conf ] Gaspare Pantano , Dave Rolince VECTOR (Virtual Edge Connector Test): A Strategy to Increase TPS Fault Coverage Without Adding Test Vectors. [Citation Graph (0, 0)][DBLP ] Conf ] Richard H. Williams , R. Glenn Wagner , Charles F. Hawkins Testing Errors: Data and Calculations in an IC Manufacturing Process. [Citation Graph (0, 0)][DBLP ] Conf ] Babur Mustafa Pulat , Lauren M. Streb Position of Component Testing in Total Quality Management (TQM). [Citation Graph (0, 0)][DBLP ] Conf ] Mick Tegethoff , T. E. Figal , S. W. Hird Board Test DFT Model for Computer Products. [Citation Graph (0, 0)][DBLP ] Conf ] Marcelo Lubaszewski , Bernard Courtois On the Design of Self-Checking Boundary Scannable Boards. [Citation Graph (0, 0)][DBLP ] Conf ] Wei-Cheng Her , Lin-Ming Jin , Yacoub M. El-Ziq An ATPG Driver Selection Algorithm for Interconnect Test with Boundary Scan. [Citation Graph (0, 0)][DBLP ] Conf ] Matthew Melton , Franc Brglez Automatic Pattern Generation for Diagnosis of Wiring Interconnect Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Timothy Daniel Lyons The Production Implementation of a Linear Error Modeling Technique. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen C. Bateman , William H. Kao Simulation of an Integrated Design and Test Environment for Mixed-Signal Integrated Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Alaa F. Alani , Gerry Musgrave , Anthony P. Ambler A Steady-State Response Test Generation for Mixed-Signal Integrated Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] R. Warren Necoechea High Performance Monolithic Verniers for VLSI Automatic Test Equipment. [Citation Graph (0, 0)][DBLP ] Conf ] Gary Fehr Timing-Per-Pin Flexibility at Shared-Resource Cost. [Citation Graph (0, 0)][DBLP ] Conf ] Timothy Alton TGEN: Flexible Timing Generator Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Christopher L. Henderson , Richard H. Williams , Charles F. Hawkins Economic Impact of Type I Test Errors at System and Board Levels. [Citation Graph (0, 0)][DBLP ] Conf ] Michael G. Wahl , Carol Pyron EDIF Test - The Upcoming Standard for Test Data Transfers. [Citation Graph (0, 0)][DBLP ] Conf ] Bas Verhelst , Richard Morren , Keith Baker Using EDIF for Transfer of Test Data: Practical Experience. [Citation Graph (0, 0)][DBLP ] Conf ] Michele Favalli , Marcello Dalpasso , Piero Olivo , Bruno Riccò Analysis of Steady State Detection of Resistive Bridging Faults in BiCMOS Digital ICs. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Lidén , Peter Dahlgren , Jan Torin Transistor Fault Coverage for Self-Testing CMOS Checkers. [Citation Graph (0, 0)][DBLP ] Conf ] Marcello Dalpasso , Michele Favalli , Piero Olivo , Bruno Riccò Parametric Bridging Fault Characterization for the Fault Simulation of Library-Based ICs. [Citation Graph (0, 0)][DBLP ] Conf ] Gordon R. Mc Leod BIST Techniques for ASIC Design. [Citation Graph (0, 0)][DBLP ] Conf ] Benoit Nadeau-Dostie , Dwayne Burek , Abu S. M. Hassan ScanBIST: A Multi-frequency Scan-based BIST Method. [Citation Graph (0, 0)][DBLP ] Conf ] Wei-Lun Wang , Jhing-Fa Wang , Kuen-Jong Lee A Fast Testing Method for Sequential Circuits at the State Trasition Level. [Citation Graph (0, 0)][DBLP ] Conf ] Herbert Thaler , Lee Holt A Suite of Novel Digital ATE Timing Calibration Methods. [Citation Graph (0, 0)][DBLP ] Conf ] David C. Keezer , R. J. Wenzel Calibration Techniques for a Gigahertz Test System. [Citation Graph (0, 0)][DBLP ] Conf ] Ulrich Schoettmer , Holger Engelhard High Performance Pin Electronics with GaAs, A Contradiction in Terms? [Citation Graph (0, 0)][DBLP ] Conf ] Maury A. Smeyne System Test: What is it? Why Bother Defining It? [Citation Graph (0, 0)][DBLP ] Conf ] William R. Simpson , John W. Sheppard System Perspective on Diagnostic Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Charles F. Hawkins System Testing: The Future for All of Us. [Citation Graph (0, 0)][DBLP ] Conf ] Noel E. Donlin Is Burn-In Burned-Out - Part 2. [Citation Graph (0, 0)][DBLP ] Conf ] Anneliese von Mayrhauser Software Testing: Opportunity and Nightmare. [Citation Graph (0, 0)][DBLP ] Conf ] Simeon C. Ntafos Software Testing: Theory and Practice. [Citation Graph (0, 0)][DBLP ] Conf ] Richard Hulse A Mixed Signal Analog Test Bus Framework. [Citation Graph (0, 0)][DBLP ] Conf ] Madhuri Jarwala Design for Test Approaches to Mixed-Signal Testing. [Citation Graph (0, 0)][DBLP ] Conf ] B. R. Wilkins A Structure for Board-Level Mixed-Signal Testability. [Citation Graph (0, 0)][DBLP ] Conf ] Bejoy G. Oomman , Prasad Kongara , Chittaranjan Mallipeddi Amdahl Corporation Board Delay Test System. [Citation Graph (0, 0)][DBLP ] Conf ] Yaron Aizenbud , Paul Chang , Moshe Leibowitz , Dave Smith , Bernd Könemann , Vijay S. Iyengar , Barry K. Rosen AC Test Quality: Beyond Transition Fault Coverage. [Citation Graph (0, 0)][DBLP ] Conf ] Bernd Könemann , J. Barlow , Paul Chang , R. Gabrielson , C. Goertz , Brion L. Keller , Kevin McCauley , J. Tischer , Vijay S. Iyengar , Barry K. Rosen , T. Williams Delay Test: The Next Frontier for LSSD Test Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Weiwei Mao , Michael D. Ciletti Robustness Enhancement and Detection Threshold Reduction in ATPG for Gate Delay Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Nicolaidis Transparent BIST for RAMs. [Citation Graph (0, 0)][DBLP ] Conf ] H. Maeno , K. Nii , S. Sakayanagi , S. Kato LSSD Compatible and Concurrently Testable Ram. [Citation Graph (0, 0)][DBLP ] Conf ] Masaki Tsukude , Kazutami Arimoto , Hideto Hidaka , Yasuhiro Konishi , Masanori Hayashikishi , Katsunori Suma , Kazuyasu Fujishima A Testing Technique for ULSI Memory with On-Chip Voltage Down Converter. [Citation Graph (0, 0)][DBLP ] Conf ] Tom Chen , Glen Sunada A Self-Testing and Self-Repairing Structure for Ultra-Large Capacity Memories. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaoqing Wen , Kozo Kinoshita Testable Designs of Sequential Circuits Under Highly Observable Condition. [Citation Graph (0, 0)][DBLP ] Conf ] M. Saraiva , P. Casimiro , Marcelino B. Santos , José T. de Sousa , Fernando M. Gonçalves , Isabel C. Teixeira , João Paulo Teixeira Physical DFT for High Coverage of Realistic Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Andrzej Krasniewski , Slawomir Pilarski High Quality Testing of Embedded RAMs Using Circular Self-Test Path. [Citation Graph (0, 0)][DBLP ] Conf ] Miron Abramovici , Prashant S. Parikh Warning: 100% Fault Coverage May Be Misleading!! [Citation Graph (0, 0)][DBLP ] Conf ] Paul Astrachan , Todd Brooks , Jody Everett , Wai-on Law , Kenneth McIntyre , Chuong Nguyen , Charles Weng Testing a DSP-Based Mixed-Signal Telecommunications Chip. [Citation Graph (0, 0)][DBLP ] Conf ] J. Preißner , G.-H. Huaman-Bollo , G. Mahlich , Johannes Schuck , Hans Sahm , P. Weingart , D. Weinsziehr , J. Yeandel , R. Evans An Open Modular Test Concept for the DSP KISS-16Vs. [Citation Graph (0, 0)][DBLP ] Conf ] A. J. van de Goor , Th. J. W. Verhallen Functional Testing of Current Microprocessors (applied to the Intel i860TM ). [Citation Graph (0, 0)][DBLP ] Conf ] Marcus Rimén , Joakim Ohlsson A Study of the Error Behavior of a 32-bit RISC Subjected to Simulated Transient Fault Injection. [Citation Graph (0, 0)][DBLP ] Conf ] Jacob Savir Skewed-Load Transition Test: Part 1, Calculus. [Citation Graph (0, 0)][DBLP ] Conf ] Srinivas Patil , Jacob Savir Skewed-Load Transition Test: Part 2, Coverage. [Citation Graph (0, 0)][DBLP ] Conf ] Kwang-Ting Cheng Transition Fault Simulation for Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Oliver F. Haberl , Thomas Kropf HIST: A Methodology for the Automatic Insertion of a Hierarchical Self Test. [Citation Graph (0, 0)][DBLP ] Conf ] Pi-Yu Chung , Ibrahim N. Hajj ACCORD: Automatic Catching and CORrection of Logic Design Errors in Combinatorial Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Vivek Chickermane , Jaushin Lee , Janak H. Patel Design for Testability Using Architectural Descriptions. [Citation Graph (0, 0)][DBLP ] Conf ] Rohit Kapur , Jaehong Park , M. Ray Mercer All Tests for a Fault Are Not Equally Valuable for Defect Detection. [Citation Graph (0, 0)][DBLP ] Conf ] Ravi K. Gulati , Weiwei Mao , Deepak K. Goel Detection of "Undetectable" Faults Using IDDQ Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Robert C. Aitken A Comparison of Defect Models for Fault Location with IDDQ Measurements. [Citation Graph (0, 0)][DBLP ] Conf ] Eric Rosenfeld A Method of Jitter Measurement. [Citation Graph (0, 0)][DBLP ] Conf ] Takashi Kido In-Process Inspection Technique for Active-Matrix LCD Panels. [Citation Graph (0, 0)][DBLP ] Conf ] Paul Kelley Testing Video Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Miron Abramovici , Mahesh A. Iyer One-Pass Redundancy Identification and Removal. [Citation Graph (0, 0)][DBLP ] Conf ] Wolfgang Kunz , Dhiraj K. Pradhan Recursive Learning: An Attractive Alternative to the Decision Tree for Test Genration in Digital Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Bernd Könemann , Phil Noto A Test Generation Methodology for High-Performance Computer Chips and Modules. [Citation Graph (0, 0)][DBLP ] Conf ] Mitsuru Shinagawa , Tadao Nagatsuma An Automated Optical On-Wager Probing System for Ultra-High-Speed ICs. [Citation Graph (0, 0)][DBLP ] Conf ] R. Scharf , C. Kuntzsch , Klaus Helmreich , Werner Wolz , Klaus D. Müller-Glaser DRC-based Selection of Optimal Probing Points for Chip-Internal Measurements. [Citation Graph (0, 0)][DBLP ] Conf ] Alan C. Noble IDA: A Tool for Computer-Aided Failure Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] R. Arnold , M. Chowanetz , Werner Wolz , Klaus D. Müller-Glaser Test/Agent: CAD-integrated Automatic Generation of Test Programs. [Citation Graph (0, 0)][DBLP ] Conf ] William Kao , Jean Xia , Tom Boydston Automatic Test Program Generation for Mixed Signal ICs via Design to Test Link. [Citation Graph (0, 0)][DBLP ] Conf ] R. Mehtani , M. De Jonghe , Richard Morren , Keith Baker Improving Total IC Design Quality Using Application Mode Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Yukiya Miura , Kozo Kinoshita Circuit Design for Built-in Current Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Siyad C. Ma , Edward J. McCluskey Non-Conventional Faults in BiCMOS Digital Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Rosa Rodríguez-Montañés , Joan Figueras , Eric Bruls Bridging Defects Resistance Measurements in a CMOS Process. [Citation Graph (0, 0)][DBLP ] Conf ] James M. Bieman , Hwei Yin Designing for Software Testability Using Automated Oracles. [Citation Graph (0, 0)][DBLP ] Conf ] Anneliese von Mayrhauser , James Keables A Simulation Environment for Early Lifecycle Software Reliability Research and Prediction. [Citation Graph (0, 0)][DBLP ] Conf ] Ilene Burnstein , Nitya Jani , Steve Mannina , Joe Tamsevicius , Michael Goldshteyn , Louis Lendi Intelligent Fault Localization in Software. [Citation Graph (0, 0)][DBLP ] Conf ] January Kister , Robert L. Franch Advances in Membrane Probe Technology. [Citation Graph (0, 0)][DBLP ] Conf ] Eswar Subramanian , Randy Nelson Enhanced Probe Card Facilities At-Speed Wafer Probing in Very High Density Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel T. Hamling A 3GHz, 144 Point Probe Fixture for Automatic IC Wafer Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Cecilia Metra , Michele Favalli , Piero Olivo , Bruno Riccò CMOS Checkers with Testable Bridging and Transistor Stuck-on Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaoling Sun , Micaela Serra Merging Concurrent Checking and Off-line BIST. [Citation Graph (0, 0)][DBLP ] Conf ] Pinaki Mazumder An Integrated Built-In Self-Testing and Self-Repair of VLSI/WSI Hexagonal Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Kevin T. Kornegay , Robert W. Brodersen An Architecture for a Reconfigurable IEEE 1149.n Master Controller Board. [Citation Graph (0, 0)][DBLP ] Conf ] David L. Landis , Chuck Hudson , Patrick F. McHugh Applications of the IEEE P1149.5 Module Test and Maintenance Bus. [Citation Graph (0, 0)][DBLP ] Conf ] Najmi T. Jarwala , Paul Stiling , Enn Tammaru , Chi W. Yau A Framework for Boundary-Scan Based System Test Diagnosis. [Citation Graph (0, 0)][DBLP ] Conf ] W. C. Bruce , Michael G. Gallup , Grady Giles , Tom Munns Implementing 1149.1 on CMOS Microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] 