Conferences in DBLP
Joseph B. Costello Design and Test: What Will It Take to Tie the Knot?. [Citation Graph (0, 0)][DBLP ] Conf ] Michael S. Ledford Automotive Industry: The Next DFT Challenge. [Citation Graph (0, 0)][DBLP ] Conf ] Colin Maunder A Universal Framework for Managed Built-in Test. [Citation Graph (0, 0)][DBLP ] Conf ] William R. Simpson , John W. Sheppard The Impact of Commercial Off-The-Shelf (COTS) Equipment on System Test and Diagnosis. [Citation Graph (0, 0)][DBLP ] Conf ] Israel Beniaminy , Moshe Ben-Bassat , M. Bodenheimer , M. Eshel Experience in Diagnosing a Remote, Tele-Controlled Unit Using the AITEST Expert System. [Citation Graph (0, 0)][DBLP ] Conf ] Frank W. Angelotti , Wayne A. Britson , Kerry T. Kaliszewski , Steve M. Douskey System Level Interconnect Test in a Tristate Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Jeff Rearick , Janak H. Patel Fast and Accurate CMOS Bridging Fault Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Peter C. Maxwell , Robert C. Aitken Biased Voting: A Method for Simulating CMOS Bridging Faults in the Presence of Variable Gate Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Eugeni Isern , Joan Figueras Test Generation with High Coverages for Quiescent Current Test of Bridging Faults in Combinational Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Heinrich Theodor Vierhaus , Wolfgang Meyer , Uwe Gläser CMOS Bridges and Resistive Transistor Faults: IDDQ versus Delay Effects. [Citation Graph (0, 0)][DBLP ] Conf ] Kurt A. Milne Automated Wafer Lot Approval: A Statistically Based Implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Brian Beck Practical Application of Statistical Process Control in Semiconductor Manufacturing. [Citation Graph (0, 0)][DBLP ] Conf ] Rick Boyle , Jack Donovan , Eugene R. Hnatek , Alex M. Ijaz Application of Statistical Techniques to Critical System Parameters. [Citation Graph (0, 0)][DBLP ] Conf ] M. M. A. van Rosmalen , Keith Baker , Eric Bruls , Jochen A. G. Jess Parameter Monitoring: Advantages and Pitfalls. [Citation Graph (0, 0)][DBLP ] Conf ] Tom Austin Creating A Mixed-Signal Simulation Capability for Concurrent IC Design and Test Program Development. [Citation Graph (0, 0)][DBLP ] Conf ] Tony Taylor Tools and Techniques for Converting Simulation Models into Test Patterns. [Citation Graph (0, 0)][DBLP ] Conf ] Ravindranath Naiknaware , G. N. Nandakumar , Srinivasa Rao Kasa Automatic Test Plan Generation for Analog and Mixed Signal Integrated Circuits using Partial Activation and High Level Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Jan Moorman , Steven D. Millman Visualizing Test Information: A Novel Approach for Improving Testability. [Citation Graph (0, 0)][DBLP ] Conf ] Markus Robinson , Frederic Mailhot , Jim Konsevich Technology Independent Boundary Scan Synthesis (Technology and Physical Issues). [Citation Graph (0, 0)][DBLP ] Conf ] Tom Langford Utilizing Boundary Scan to Implement BIST. [Citation Graph (0, 0)][DBLP ] Conf ] Math Muris , Alex S. Biewenga Using Boundary Scan Test to Test Random Access Memory Clusters. [Citation Graph (0, 0)][DBLP ] Conf ] Jarir K. Chaar , Michael J. Halliday , Inderpal S. Bhandari , Ram Chillarege On the Evaluation of Software Inspections and Tests. [Citation Graph (0, 0)][DBLP ] Conf ] Samuel T. Chanson , Antonio Alfredo Ferreira Loureiro , Son T. Vuong On the Design for Testability of Communication Software. [Citation Graph (0, 0)][DBLP ] Conf ] Gregory F. Sullivan , Dwight S. Wilson , Gerald M. Masson Certification Trails and Software Design for Testability. [Citation Graph (0, 0)][DBLP ] Conf ] Chryssa Dislis , J. H. Dick , I. D. Dear , I. N. Azu , Anthony P. Ambler Economics Modelling for the Determination of Test Strategies for Complex VLSI Boards. [Citation Graph (0, 0)][DBLP ] Conf ] Richard H. Williams , Charles F. Hawkins The Economics of Guardband Placement. [Citation Graph (0, 0)][DBLP ] Conf ] Douglas J. Mirizzi , Willie Jerrels , Dale Ohmart Implementation of Parallelsite Test on an 8Bit Configurable Microcontroller. [Citation Graph (0, 0)][DBLP ] Conf ] Slawomir Pilarski , Alicja Pierzynska BIST and Delay Fault Detection. [Citation Graph (0, 0)][DBLP ] Conf ] Prab Varma , Tushar Gheewala Delay Testing Using a Matrix of Accessible Storage. [Citation Graph (0, 0)][DBLP ] Conf ] Harold N. Scholz , Duane R. Aadsen , Yervant Zorian A Method for Delay Fault Self-Testing of Macrocells. [Citation Graph (0, 0)][DBLP ] Conf ] Colin Maunder Position Statement: ITC93 Boundary-Scan Panel. [Citation Graph (0, 0)][DBLP ] Conf ] David A. Greene Benefits of Boundary-Scan to In-Circuit Test. [Citation Graph (0, 0)][DBLP ] Conf ] Wayne T. Daniel IEEE 1149.1 Growing Pains. [Citation Graph (0, 0)][DBLP ] Conf ] Mick Tegethoff IEEE 1149.1: How to Justify Implementation. [Citation Graph (0, 0)][DBLP ] Conf ] David C. Keezer Known Godd Die for MCMs: Enabling Technologies. [Citation Graph (0, 0)][DBLP ] Conf ] Prab Varma Scan DFT: Why More Can Cost Less. [Citation Graph (0, 0)][DBLP ] Conf ] John W. Sheppard Testing Fully Testable Systems: A Case Study. [Citation Graph (0, 0)][DBLP ] Conf ] Jon Turino DFT: Profit or Loss -- A Position Paper. [Citation Graph (0, 0)][DBLP ] Conf ] Alex Elentukh Cultural Evolution in Software Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Michael A. Long Software Regression Testing Success Story. [Citation Graph (0, 0)][DBLP ] Conf ] James F. Leathrum , K. A. Liburdy The Evolving Role of Testing in Open Systems Standards. [Citation Graph (0, 0)][DBLP ] Conf ] Hong Hao , Edward J. McCluskey Very-Low-Voltage Testing for Weak CMOS Logic ICs. [Citation Graph (0, 0)][DBLP ] Conf ] Rick Gayle The Cost of Quality: Reducing ASIC Defects with IDDQ At-Speed Testing and Increased Fault Coverage. [Citation Graph (0, 0)][DBLP ] Conf ] Paul C. Wiscombe A Comparison of Stuck-At Fault Coverage and IDDQ Testing on Defect Levels. [Citation Graph (0, 0)][DBLP ] Conf ] Carl W. Thatcher , Rodham E. Tulloss Towards a Test Standard for Board and System Level Mixed-Signal Interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth P. Parker , John E. McDermid , Stig Oresjo Structure and Metrology for an Analog Testability Bus. [Citation Graph (0, 0)][DBLP ] Conf ] José Silva Matos , Ana C. Leão , João Canas Ferreira Control and Observation of Analog Nodes in Mixed-Signal Boards. [Citation Graph (0, 0)][DBLP ] Conf ] Robert Gage Structured CBIST in ASICs. [Citation Graph (0, 0)][DBLP ] Conf ] Jos van Sas , Geert van Wauwe , Erik Huyskens , Dirk Rabaey BIST for Embedded Static RAMs with Coverage Calculation. [Citation Graph (0, 0)][DBLP ] Conf ] James Broseghini , Donald H. Lenhert An ALU-Based Programmable MISR/Pseudorandom Generator for a MC68HC11 Family Self-Test. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas M. Storey A Test Methodology for VLSI Chips on Silicon. [Citation Graph (0, 0)][DBLP ] Conf ] Lynn Roszel MCM Foundry Test Methodology and Implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Russell J. Wagner , Joel A. Jorgenson Design-For-Test Techniques Utilized in an Avionics Computer MCM. [Citation Graph (0, 0)][DBLP ] Conf ] Chryssa Dislis , J. H. Dick , Anthony P. Ambler Algorithms for Cost Optimised Test Strategy Selection. [Citation Graph (0, 0)][DBLP ] Conf ] Cary Champlin IRIDIUMtm Satellite: A Large System Application of Design for Testability. [Citation Graph (0, 0)][DBLP ] Conf ] Rodham E. Tulloss IEEE 1149 Standards - Changing Testing, Silicon to Systems. [Citation Graph (0, 0)][DBLP ] Conf ] M. J. Aguado , E. de la Torre , Miguel Miranda , C. López-Barrio Distributed Implementation of an ATPG System Using Dynamic Fault Allocation. [Citation Graph (0, 0)][DBLP ] Conf ] Robert H. Klenke , Lori M. Kaufman , James H. Aylor , Ronald Waxman , Padmini Narayan Workstation Based Parallel Test Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Mitsuo Teramoto A Method for Reducing the Search Space in Test Pattern Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Scott Diamond , Bo Janko Extraction of Coupled SPICE Models for Packages and Interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Rudy Garcia Keep Alive - A New Requirement for High Performance uProcessor Test. [Citation Graph (0, 0)][DBLP ] Conf ] Hans Bouwmeester , Steven Oostdijk , Frank Bouwman , Rudi Stans , Loek Thijssen , Frans P. M. Beenker Minimizing Test Time by Exploiting Parallelism in Macro Test. [Citation Graph (0, 0)][DBLP ] Conf ] Jim Mosley III A Flexible Approach to Data Collection for Component Test Systems. [Citation Graph (0, 0)][DBLP ] Conf ] John O'Donnell Generated in Real-time Instant Process Statistics ("GRIPS"): Immediate, Tester-computed Test Statistics, Eliminating the Post-processing of Datalogs. [Citation Graph (0, 0)][DBLP ] Conf ] Paresh Gondalia , Allan Gutjahr , Wen-Ben Jone Realizing a High Measure of Confidence for Defect Level Analysis of Random Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Johannes Steensma , Francky Catthoor , Hugo De Man Partial Scan at the Register-Transfer Level. [Citation Graph (0, 0)][DBLP ] Conf ] Kee Sup Kim , Charles R. Kime Partial Scan Using Reverse Direction Empirical Testability. [Citation Graph (0, 0)][DBLP ] Conf ] Chih-Jen Lin , Yervant Zorian , Sudipta Bhawmik PSBIST: A Partial-Scan Based Built-In Self-Test Scheme. [Citation Graph (0, 0)][DBLP ] Conf ] Lee Whetsel Hierarchically Accessing 1149.1 Applications in a System Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Christopher Poirier IEEE P1149.5 to 1149.1 Data and Protocol Conversion. [Citation Graph (0, 0)][DBLP ] Conf ] José M. M. Ferreira , Manuel G. Gericota , José L. Ramalho , Gustavo R. Alves BIST for 1149.1-Compatible Boards: A Low-Cost and Maximum-Flexibility Solution. [Citation Graph (0, 0)][DBLP ] Conf ] Richard K. Feldman A Novel Instrument for Accurate Time Measurement in Automatic Calibration of Test Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Arnold Frisch , Thomas Almy Timing Analyzer for Embedded Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Will Creek Characterization of Edge Placement Accuracy in High-Speed Digital Pin Electronics. [Citation Graph (0, 0)][DBLP ] Conf ] Mani Soma Fault Coverage of DC Parametric Tests for Embedded Analog Amplifiers. [Citation Graph (0, 0)][DBLP ] Conf ] E. Kurzweil , M. Lallement , R. Blanc , R. Pasquinelli Catch the Ground Bounce Before It Hits your System. [Citation Graph (0, 0)][DBLP ] Conf ] Hugh Littlebury , Roger Brueckner Integrating Electrical Test into Final Assembly. [Citation Graph (0, 0)][DBLP ] Conf ] Carl W. Thatcher Design-For-Testability Economics. [Citation Graph (0, 0)][DBLP ] Conf ] Nai-Chi Lee Practical Considerations for Mixed-Signal Test Bus. [Citation Graph (0, 0)][DBLP ] Conf ] Gunnar Carlsson Test Synthesis from a User Perspective. [Citation Graph (0, 0)][DBLP ] Conf ] Miron Abramovici DOs and DON'Ts in Computing Fault Coverage. [Citation Graph (0, 0)][DBLP ] Conf ] Peter C. Maxwell Let's Grade ALL the Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Jerry M. Soden , Charles F. Hawkins Quality Testing Requires Quality Thinking. [Citation Graph (0, 0)][DBLP ] Conf ] Edward J. McCluskey Quality and Single-Stuck Faults. [Citation Graph (0, 0)][DBLP ] Conf ] M. H. Konijnenburg , J. Th. van der Linden , A. J. van de Goor Test Pattern Generation with Restrictors. [Citation Graph (0, 0)][DBLP ] Conf ] Praveen Vishakantaiah , Jacob A. Abraham , Daniel G. Saab CHEETA: Composition of Hierarchical Sequential Tests Using ATKET. [Citation Graph (0, 0)][DBLP ] Conf ] Eun Sei Park , M. Ray Mercer Switch-Level ATPG Using Constraint-Guided Line Justification. [Citation Graph (0, 0)][DBLP ] Conf ] J. S. Beasley , H. Ramamurthy , Jaime Ramírez-Angulo , Mark DeYong iDD Pulse Response Testing of Analog and Digital CMOS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Ching-Wen Hsue , Chih-Jen Lin Built-In Current Sensor for IDDQ Test in CMOS. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth M. Wallquist , Alan W. Righter , Charles F. Hawkins A General Purpose IDDQ Measurement Circuit. [Citation Graph (0, 0)][DBLP ] Conf ] Naim Ben Hamida , Bozena Kaminska Analog Circuit Testing Based on Sensitivity Computation and New Circuit Modeling. [Citation Graph (0, 0)][DBLP ] Conf ] S. J. Barnfield , W. R. Moore Multiple Fault Diagnosis in Printed Circuit Boards. [Citation Graph (0, 0)][DBLP ] Conf ] Christophe Vaucher , Louis Balme The Standard Mirror Boards (SMBs) Concept. [Citation Graph (0, 0)][DBLP ] Conf ] Anchada Charoenrook , Mani Soma Fault Diagnosis of Flash ADC using DNL Test. [Citation Graph (0, 0)][DBLP ] Conf ] David Ownby , Harold Bogard FFT Based Troubleshooting of 120dB Dynamic Range ADC Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Shinichi Kimura , Makoto Kimura , Takayuki Nakatani , Masao Sugai A New Approach for PLL Characterization on Mixed Signal ATE. [Citation Graph (0, 0)][DBLP ] Conf ] D. Dumas , Patrick Girard , Christian Landrault , Serge Pravossoudovitch An Implicit Delay-Fault Simulation Method with Approximate Detection Threshold Calculation. [Citation Graph (0, 0)][DBLP ] Conf ] Soumitra Bose , Prathima Agrawal , Vishwani D. Agrawal Generation of Compact Delay Tests by Multiple-Path Activation. [Citation Graph (0, 0)][DBLP ] Conf ] Jayashree Saxena , Dhiraj K. Pradhan A Method to Derive Compact Test Sets for Path Delay Faults in Combinational Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] LaNae J. Avra , Edward J. McCluskey Synthesizing for Scan Dependence in Built-In Self-Testable Desings. [Citation Graph (0, 0)][DBLP ] Conf ] Tien-Chien Lee , Niraj K. Jha , Wayne Wolf A Conditional Resource-Sharing Method for Behavior Synthesis of Highly- Testable Data Paths. [Citation Graph (0, 0)][DBLP ] Conf ] Suman Kanjilal , Srimat T. Chakradhar , Vishwani D. Agrawal A Synthesis Approach to Design for Testability. [Citation Graph (0, 0)][DBLP ] Conf ] Don Douglas Josephson , Daniel J. Dixon , Barry J. Arnold Test Features of the HP PA7100LC Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Rajiv Patel , Krishna Yarlagadda Testability Features of the SuperSPARCtm . [Citation Graph (0, 0)][DBLP ] Conf ] H. Bonnenberg , Andreas Curiger , Norbert Felber , Hubert Kaeslin , R. Zimmermann , Wolfgang Fichtner VINCI: Secure Test of a VLSI High-Speed Encryption System. [Citation Graph (0, 0)][DBLP ] Conf ] Eiichi Teraoka , Toru Kengaku , Ikuo Yasui , Kazuyuki Ishikawa , Takahiro Matsuo , Hideyuki Wakada , Narumi Sakashita , Yukihiko Shimazu , Takeshi Tokuda A Built-in Self- Test for ADC and DAC in a Single-Chip Speech CODEC. [Citation Graph (0, 0)][DBLP ] Conf ] Ed Flaherty , Andrew Allen , John Morris Design for Testability of a Modular, Mixed Signal Family of VLSI Devices. [Citation Graph (0, 0)][DBLP ] Conf ] M. F. Toner , Gordon W. Roberts A BIST Scheme for an SNR Test of a Sigma-Delta ADC. [Citation Graph (0, 0)][DBLP ] Conf ] Manoj Sachdev , Math Verstraelen Development of Fault Model and Test Algorithms for Embedded DRAMs. [Citation Graph (0, 0)][DBLP ] Conf ] Robert P. Treuer , Vinod K. Agarwal Fault Location Algorithms for Repairable Embedded. [Citation Graph (0, 0)][DBLP ] Conf ] Janusz Sosnowski "In System" Transparent Autodiagnostics of Rams. [Citation Graph (0, 0)][DBLP ] Conf ] Richard H. Carver Mutation-Based Testing of Concurrent Programs. [Citation Graph (0, 0)][DBLP ] Conf ] James F. Leathrum , K. A. Liburdy Automated Testing of Open Software Standards. [Citation Graph (0, 0)][DBLP ] Conf ] Anneliese von Mayrhauser , Kurt M. Olender Efficient Testing of Software Modifications. [Citation Graph (0, 0)][DBLP ] Conf ] Michele Favalli , Marcello Dalpasso , Piero Olivo , Bruno Riccò Analyss of Dynamic Effects of Resistive Bridging Faults in CMOS and BiCMOS Digital ICs. [Citation Graph (0, 0)][DBLP ] Conf ] Chennian Di , Jochen A. G. Jess On Accurate Modeling and Efficient Simulation of CMOS Opens. [Citation Graph (0, 0)][DBLP ] Conf ] Udo Mahlstedt , Jürgen Alt Simulation of non-classical Faults on the Gate Level - The Fault Simulator COMISM -. [Citation Graph (0, 0)][DBLP ] Conf ] Bryan J. Dinteman , Paul Botsford Differential Virtual Instrumentation with Continuously. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth D. Wagner , Bernd Könemann Testable Programmable Digital Clock Pulse Control Elements. [Citation Graph (0, 0)][DBLP ] Conf ] Himanshu Kumar , Scott A. Erjavic Knowledge-Based Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Paul Sakamoto , Tom Chiu High-Speed Sampling Capability for a VLSI Mixed-Signal Tester. [Citation Graph (0, 0)][DBLP ] Conf ] Kent Kwang , Hsin Wang , Arthur Hu , Mitsuyuki Asaki , Hironobu Niijima CAD-Driven High-Precision E-Beam Positioning. [Citation Graph (0, 0)][DBLP ] Conf ] Richard F. Herlein Terminating Transmission lines in the Test Environment. [Citation Graph (0, 0)][DBLP ] Conf ] R. Mehtani , B. Atzema , M. De Jonghe , Richard Morren , Geert Seuren , Taco Zwemstra Mix Test: A Mixed-Signal Extension to a Digital Test System. [Citation Graph (0, 0)][DBLP ] Conf ] Kwang-Ting Cheng , Hsi-Chuan Chen Delay Testing for Non-Robust Untestable Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Ankan K. Pramanick , Sandip Kundu Design of Scan-Based Path-Delay-Testable Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Udo Mahlstedt DELTEST: Deterministic Test Generation for Gate-Delay Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Chauchin Su , Kychin Hwang A Serial-Scan Test-Vector-Compression Methodology. [Citation Graph (0, 0)][DBLP ] Conf ] Yves Bertrand , Frédéric Bancel , Michel Renovell Multiconfiguration Technique to Reduce Test Duration for Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy A Learning-Based Method to Match a Test Pattern Generator to a Circuit-Under-Test. [Citation Graph (0, 0)][DBLP ] Conf ] Miron Abramovici , Prashant S. Parikh , Ben Mathew , Daniel G. Saab On Selecting Flip-Flops for Partial Reset. [Citation Graph (0, 0)][DBLP ] Conf ] Danial J. Neebel , Charles R. Kime Inhomogeneous Cellular Automata for Weighted-Random-Pattern Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Miguel Miranda , Carlos A. López-Barrio Generation of Optimized Single Distributions of Weights for Random Built-in Self-Test. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Bershteyn Calculatoin of Multiple Sets of Weights for Weighted-Random Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Rajagopalan Srinivasan , Sandeep K. Gupta , Melvin A. Breuer Novel Test Pattern Generators for Pseudo-Exhaustive Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Robert C. Aitken BP-1992 A Comparison of Defect Models for Fault Location with IDDQ Measurements. [Citation Graph (0, 0)][DBLP ] Conf ] 