Conferences in DBLP
Robert E. Anderson A Test Retrospection and a Quest for Direction. [Citation Graph (0, 0)][DBLP ] Conf ] Aart J. de Geus Test: The New Value-Added Field. [Citation Graph (0, 0)][DBLP ] Conf ] Walt Wilson Faster, Better, Cheaper: What Does This Mean For The Test Industry? [Citation Graph (0, 0)][DBLP ] Conf ] Lina Prokopchak Development of a Solution for Achieving Known-Good-Die. [Citation Graph (0, 0)][DBLP ] Conf ] Toshiaki Ueno , You Kondoh Membrane Prove Technology for MCM Known-Good-Die. [Citation Graph (0, 0)][DBLP ] Conf ] William E. Burdick Jr. , Wolfgang Daum High-Yield Multichip Modules Based on Minimal IC Pretest. [Citation Graph (0, 0)][DBLP ] Conf ] Anne E. Gattiker , Wojciech Maly Feasibility Study of Smart Substrate Multichip Modules. [Citation Graph (0, 0)][DBLP ] Conf ] Dilip K. Bhavsar , John H. Edmondson Testability Strategy of the ALPHA AXP 21164 Microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Alfred L. Crouch , Matthew Pressly , Joe Circello Testabilty Features of the MC 68060 Microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Kalon Holdbrook , Sunil Joshi , Samir Mitra , Joe Petolino , Renu Raman , Michelle Wong microSPARCTM : A Case Study of Scan-Based Debug. [Citation Graph (0, 0)][DBLP ] Conf ] Craig Hunter , E. Kofi Vida-Torku , Johnny LeBlanc Balancing Structured and Ad-hoc Design for Test: Testing of the PowerPC 603TM Microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Des Farren , Anthony P. Ambler System Test Cost Modelling Based on Event Rate Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Donald L. Wheater , Phil Nigh , Jeanne Trinko Mechler , Luke Lacroix ASIC Test Cost/Strategy Trade-offs. [Citation Graph (0, 0)][DBLP ] Conf ] Timothy J. Moore A Test Process Optimization and Cost Modeling Tool. [Citation Graph (0, 0)][DBLP ] Conf ] David A. Greene When Does It Make cents to Give Up Physical Test Access? [Citation Graph (0, 0)][DBLP ] Conf ] Edward C. Behnke 3B21D BIST/Boundary-Scan System Diagnostic Test Story. [Citation Graph (0, 0)][DBLP ] Conf ] Frank W. Angelotti Modeling for Structured System Interconnect Test. [Citation Graph (0, 0)][DBLP ] Conf ] Harald P. E. Vranken , M. P. J. Stevens , M. T. M. Segers , J. H. M. M. van Rhee System-Level Testability of Hardware/Software Systems. [Citation Graph (0, 0)][DBLP ] Conf ] John D. Lofgren A Generic Test and Maintenance Node for Embedded System Test. [Citation Graph (0, 0)][DBLP ] Conf ] Bill Underwood , Wai-on Law , Sungho Kang , Haluk Konuk Fastpath: A Path-Delay Test Generator for Standard Scan Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Prab Varma On Path-Delay Testing in a Standard Scan Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Nur A. Touba , Edward J. McCluskey Automated Logic Synthesis of Random-Pattern-Testable Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Sujit Dey , Miodrag Potkonjak Transforming Behavioral Specifications to Facilitate Synthesis of Testable Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Keith Baker QTAG: A Standard for Test Fixture Based IDDQ /ISSQ Monitors. [Citation Graph (0, 0)][DBLP ] Conf ] Hans A. R. Manhaeve , Paul L. Wrighton , Jos van Sas , Urbain Swerts An Off-chip IDDQ Current Measurement Unit for Telecommunication ASICs. [Citation Graph (0, 0)][DBLP ] Conf ] Keith Baker , A. Bratt , Andrew M. D. Richardson , A. Welbers Development of a CLASS 1 QTAG Monitor. [Citation Graph (0, 0)][DBLP ] Conf ] Alan Hales A Serially Addressable, Flexible Current Monitor for Test Fixture Based IDDQ /ISSQ Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Jalal A. Wehbeh , Daniel G. Saab On the Initialization of Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Paolo Prinetto , Maurizio Rebaudengo , Matteo Sonza Reorda An Automatic Test Pattern Generator for Large Sequential Circuits Based on Genetic Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Seongmoon Wang , Sandeep K. Gupta ATPG for Heat Dissipation Minimization During Test Application. [Citation Graph (0, 0)][DBLP ] Conf ] Mahesh A. Iyer , Miron Abramovici Sequentially Untestable Faults Identified Without Search ("Simple Implications Beat Exhaustive Search!"). [Citation Graph (0, 0)][DBLP ] Conf ] Michael G. Davis Implementation of a Dual-Segment Architecture for a High-Pin-Count VLSI Test System. [Citation Graph (0, 0)][DBLP ] Conf ] Didier Wimmers , Kris Sakaitani , Burnell G. West 500-MHz Testing on a 100-MHz Tester. [Citation Graph (0, 0)][DBLP ] Conf ] Mary Sue Haydt , Robert Michael Owens , Samiha Mourad Modeling the Effect of Ground Bounce on Noise Margin. [Citation Graph (0, 0)][DBLP ] Conf ] Eric Kushnick Modular Mixed Signal Testing: High Speed or High Resolution. [Citation Graph (0, 0)][DBLP ] Conf ] Gordon R. McLeod Built-in System Test and Fault Location. [Citation Graph (0, 0)][DBLP ] Conf ] John Andrews Roadmap for Extending IEEE 1149.1 for Hierarchical Control of Locally-Stored, Standardized-Command-Set Test Programs. [Citation Graph (0, 0)][DBLP ] Conf ] Duy Le , Ivan Karolik , Ronald Smith , A. J. Mcgovern , Chyral Curette , Joseph Ulbin , Michael Zarubaiko , Charles Henry , Lewis Stevens Environmental Stress Testing with Boundary-Scan. [Citation Graph (0, 0)][DBLP ] Conf ] Lee Whetsel An Approach to Accelerate Scan Testing in IEEE 1149.1 Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Kee Sup Kim , Len Schultz Multi-Frequency, Multi-Phase Scan Chain. [Citation Graph (0, 0)][DBLP ] Conf ] Jau-Shien Chang , Chen-Shang Lin A Test-Clock Reduction Method for Scan-Designed Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Sanghyeon Baeg , William A. Rogers Hybrid Design for Testability Combining Scan and Clock Line Control and Method for Test Generation. [Citation Graph (0, 0)][DBLP ] Conf ] André DeHon In-System Timing Extraction and Control Through Scan-Based, Test-Access Ports. [Citation Graph (0, 0)][DBLP ] Conf ] Yasuhiro Konishi , T. Ogawa , M. Kumanoya Testing 256k Word x 16 Bit Cache DRAM (CDRAM). [Citation Graph (0, 0)][DBLP ] Conf ] James A. Gasbarro Testing High Speed Drams. [Citation Graph (0, 0)][DBLP ] Conf ] Kent Stalnaker Practical Test Methods for Verification of the EDRAM. [Citation Graph (0, 0)][DBLP ] Conf ] Wha-Joon Lee Testing Issues on High Speed Synchronous DRAMs. [Citation Graph (0, 0)][DBLP ] Conf ] Kamalesh N. Ruparel Benchmarking. [Citation Graph (0, 0)][DBLP ] Conf ] Don Sterba Potential Solutions for Benchmarking Issues. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth E. Posse Multichip Module Testing Methodologies: What's In; What's Not. [Citation Graph (0, 0)][DBLP ] Conf ] Jed Eastman MCM Test Trade-Offs. [Citation Graph (0, 0)][DBLP ] Conf ] Vyacheslav N. Yarmolik , Michael Nicolaidis , O. Kebichi Aliasing-free Signature Analysis for RAM BIST. [Citation Graph (0, 0)][DBLP ] Conf ] Yervant Zorian , A. J. van de Goor , Ivo Schanstra An Effective BIST Scheme for Ring-Address Type FIFOs. [Citation Graph (0, 0)][DBLP ] Conf ] Craig Hunter , Jeff Slaton , Jim Eno , Romesh M. Jessani , Carl Dietz The PowerPC 603TM Microprocessor: An Array Built-In Self-Test Mechanism. [Citation Graph (0, 0)][DBLP ] Conf ] Brian Chess , Anthony Freitas , F. Joel Ferguson , Tracy Larrabee Testing CMOS Logic Gates for Realistic Shorts. [Citation Graph (0, 0)][DBLP ] Conf ] Sreejit Chakravarty , Paul J. Thadikaran A Study of IDDQ Subset Selection Algorithms for Bridging Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Charles F. Hawkins , Jerry M. Soden , Alan W. Righter , F. Joel Ferguson Defect Classes - An Overdue Paradigm for CMOS IC. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas M. Storey , C. Lapihuska , E. Atwood , L. Su A Test Methodology to Support an ASEM MCM Foundry. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew Flint Test Strategies for a Family of Complex MCMs. [Citation Graph (0, 0)][DBLP ] Conf ] Najmi T. Jarwala Designing "Dual-Personality" IEEE 1149.1-Compliant Multi-Chip Modules. [Citation Graph (0, 0)][DBLP ] Conf ] Jerry Katz A Case Study in the Use of Scan in microSparcTM Testing and Debug. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas Burch , J. Hartmann , Günter Hotz , M. Krallmann , U. Nikolaus , Sudhakar M. Reddy , Uwe Sparmann A Hierarchical Environment for Interactive Test Engineering. [Citation Graph (0, 0)][DBLP ] Conf ] Solomon Max Ensuring System Traceability to International Standards. [Citation Graph (0, 0)][DBLP ] Conf ] Dhiraj K. Pradhan , Mitrajit Chatterjee GLFSR - A New Test Pattern Generator for Built-In Self-Test. [Citation Graph (0, 0)][DBLP ] Conf ] Rohit Kapur , Srinivas Patil , Thomas J. Snethen , Thomas W. Williams Design of an Efficient Weighted-Random-Pattern Generation System. [Citation Graph (0, 0)][DBLP ] Conf ] Krishnendu Chakrabarty , John P. Hayes Efficient Test-Response Compression for Multiple-Output Cicuits. [Citation Graph (0, 0)][DBLP ] Conf ] Timothy J. Dell ECC-On-SIMM Test Challenges. [Citation Graph (0, 0)][DBLP ] Conf ] James A. Gasbarro , Mark Horowitz Techniques for Characterizing DRAMs With a 500-MHz Interface. [Citation Graph (0, 0)][DBLP ] Conf ] Sang-Chul Oh , Jae-Ho Kim , Ho-Jeong Choi , Si-Don Choi , Ki Tae Park , Jong-Woo Park , Wha-Joon Lee Automatic Failure-Analysis System for High-Density DRAM. [Citation Graph (0, 0)][DBLP ] Conf ] William R. Kosar Detection and Correction of Systematic Type 1 Test Errors Through Concurrent Engineering. [Citation Graph (0, 0)][DBLP ] Conf ] Mick Tegethoff , Tom Chen Defects, Fault Coverage, Yield and Cost in Board Manufacturing. [Citation Graph (0, 0)][DBLP ] Conf ] Cheryl Ascarrunz HALT: Bridging the Gap Between Theory and Practice. [Citation Graph (0, 0)][DBLP ] Conf ] Simon Johnson Residual Charge on the Faulty Floating Gate MOS Transistor. [Citation Graph (0, 0)][DBLP ] Conf ] Eric Bruls Variable Supply Voltage Testing for Analogue CMOS and Bipolar Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Scott Davidson Is IDDQ Yield Loss Inevitable? [Citation Graph (0, 0)][DBLP ] Conf ] John A. Masciola , Gerald K. Morgan , Geoffrey L. Templeton A Software Architecture for Mixed-Signal Functional Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Gregory A. Maston A Procedural Interface to Test. [Citation Graph (0, 0)][DBLP ] Conf ] Yuning Sun , Xiaoming Wang , Wanchun Shi An Intelligent Software-Integrated Environment of IC Testing. [Citation Graph (0, 0)][DBLP ] Conf ] J. Th. van der Linden , M. H. Konijnenburg , A. J. van de Goor Parallel Pattern Fast Fault Simulation for Three-State Circuits and Bidirectional I/O. [Citation Graph (0, 0)][DBLP ] Conf ] Rolf Krieger , Bernd Becker , Martin Keim A Hybrid Fault Simulator for Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Yoshinobu Higami , Seiji Kajihara , Kozo Kinoshita Reduced Scan Shift: A New Testing Method for Sequential Circuit. [Citation Graph (0, 0)][DBLP ] Conf ] Mustapha Slamani , Bozena Kaminska , Guy Quesnel An Integrated Approach for Analog Ciruit Testing with a Minmum Number of Detected Parameters. [Citation Graph (0, 0)][DBLP ] Conf ] R. J. A. Harvey , Andrew M. D. Richardson , Eric Bruls , Keith Baker Analogue Fault Simulation Based on Layout-Dependent Fault Models. [Citation Graph (0, 0)][DBLP ] Conf ] A. K. Lu , Gordon W. Roberts An Analog Multi-Tone Signal Generator for Built-In Self-Test Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Alfred L. Crouch , Rick Ramus , Colin Maunder Low-Power Mode and IEEE 1149.1 Compliance - A Low-Power Solution. [Citation Graph (0, 0)][DBLP ] Conf ] Chauchin Su , Kychin Hwang , Shyh-Jye Jou An IDDQ Based Built-in Concurrent Test Technique for Interconnects in a Boundary-Scan Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Savio N. Chau Fault Injection Boundary-Scan Design for Verification of Fault-Tolerant Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Takashi Sekino , Toshiyuki Okayasu Ultra Hi-Speed Pin-Electronics and Test Station Using GaAs IC. [Citation Graph (0, 0)][DBLP ] Conf ] Dennis Petrich Achieving +/-30ps Accuracy in the ATE Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Marc Mydill A Test-System Architecture to Reduce Transmission Line Effects During High-Speed Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Ewa Sokolowska , Bozena Kaminska Application of Optoelectronic Techniques to High Speed Testing. [Citation Graph (0, 0)][DBLP ] Conf ] M. Calha , Marcelino B. Santos , Fernando M. Gonçalves , Isabel C. Teixeira , João Paulo Teixeira Back Annotation of Physical Defects into Gate-Level, Realistic Faults in Digital ICs. [Citation Graph (0, 0)][DBLP ] Conf ] Olaf Stern , Hans-Joachim Wunderlich Simulation Results of an Efficient Defect-Analysis Procedure. [Citation Graph (0, 0)][DBLP ] Conf ] Peter C. Maxwell , Robert C. Aitken , Leendert M. Huisman The Effect on Quality of Non-Uniform Fault Coverage and Fault Probability. [Citation Graph (0, 0)][DBLP ] Conf ] Frank Bouwman , Taco Zwemstra , Sonny Hartanto , Keith Baker , Jan Koopmans Application of Joint Time-Frequency Analysis in Mixed-Signal Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Luke S. L. Hsieh , Sandeep P. Kumar Digitizer Error Extraction in the Nonlinearity Test. [Citation Graph (0, 0)][DBLP ] Conf ] Yves Langard , Jean-Luc Balat , Jacques Durand An Improved Method of ADC Jitter Measurement. [Citation Graph (0, 0)][DBLP ] Conf ] Gregory W. Papadeas , David Gauthier An On-Line Data Collection and Analysis System for VLSI Devices at Wafer Probe and Final Test. [Citation Graph (0, 0)][DBLP ] Conf ] Scott A. Erjavic Test Station Workcell Controller and Resource Relationship Design. [Citation Graph (0, 0)][DBLP ] Conf ] Tamorah Comard , Madhukar Joshi , Donald A. Morin , Kimberley Sprague Calculating Error of Measurement on High-Speed Microprocessor Test. [Citation Graph (0, 0)][DBLP ] Conf ] Douglas W. Raymond , Philip J. Stringer , Harold W. Ng , Michael Mitsumata , Robert Burk Goal-Directed Vector Generation Using Sample ICs. [Citation Graph (0, 0)][DBLP ] Conf ] Gordon D. Robinson NAND Trees Accurately Diagnose Board-Level Pin Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Douglas W. Raymond , Dominic F. Haigh , Ray Bodick , Barbara Ryan , Dale McCombs Non-Volatile Programmable Devices and In-Circuit Test. [Citation Graph (0, 0)][DBLP ] Conf ] A. Jefferson Offutt A Practical System for Mutation Testing: Help for the Common Programmer. [Citation Graph (0, 0)][DBLP ] Conf ] Hwei Yin , James M. Bieman Improving Software Testability with Assertion Insertion. [Citation Graph (0, 0)][DBLP ] Conf ] Anneliese von Mayrhauser , Jeff Walls , Richard T. Mraz Sleuth: A Domain-Based Testing Tool. [Citation Graph (0, 0)][DBLP ] Conf ] Alaaeldin A. Amin , Mohamed Y. Osman , Radwan E. Abdel-Aal , Husni Al-Muhtaseb Efficient O(sqrt(n)) BIST Algorithms for DDNPS Faults in Dual-Port Memories. [Citation Graph (0, 0)][DBLP ] Conf ] Mark G. Karpovsky , Vyacheslav N. Yarmolik Transparent Memory Testing for Pattern-Sensitive Faults. [Citation Graph (0, 0)][DBLP ] Conf ] A. J. van de Goor , B. Smit Generating March Tests Automatically. [Citation Graph (0, 0)][DBLP ] Conf ] Ralph Sanchez Concurrent Engineering with DFT in the Digital System: A Parallel Process. [Citation Graph (0, 0)][DBLP ] Conf ] Cecil A. Dean , Yervant Zorian Do You Practice Safe Tests? What We Found Out About Your Habits. [Citation Graph (0, 0)][DBLP ] Conf ] Debaditya Mukherjee , Massoud Pedram , Melvin A. Breuer Control Strategies for Chip-Based DFT/BIST Hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Mick Tegethoff , Tom Chen Manufacturing-Test Simulator: A Concurrent-Engineering Tool for Boards and MCMs. [Citation Graph (0, 0)][DBLP ] Conf ] Lars Eerenstein Testing Two Generations of HDTV Decoders - The Impact of Boundary-Scan. [Citation Graph (0, 0)][DBLP ] Conf ] Yunsheng Lu , Weiwei Mao , Ramaswami Dandapani , Ravi K. Gulati Structure and Metrology for a Single-wire Analog. [Citation Graph (0, 0)][DBLP ] Conf ] Mohammed F. AlShaibi , Charles R. Kime Fixed-Biased Pseudorandom Built-In Self-Test for Random-Pattern-Resistant Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Albrecht P. Stroele , Hans-Joachim Wunderlich Configuring Flip-Flops to BIST Registers. [Citation Graph (0, 0)][DBLP ] Conf ] Fulvio Corno , Paolo Prinetto , Matteo Sonza Reorda Making the Circular Self-Test Path Technique Effective for Real Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] R. S. Ramchandani , Donald E. Thomas Behavioral-Test Generation using Mixed-Integer Non-linear Programming. [Citation Graph (0, 0)][DBLP ] Conf ] Chang Hyun Cho , James R. Armstrong B-algorithm: A Behavioral-Test Generation Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Gianpiero Cabodi , Paolo Camurati , Stefano Quer Full-Symbolic ATPG for Large Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Henry Cox On Synthesizing Circuits With Implicit Testability Constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Edward B. Pitty , Denis Martin , Hi-Kyeung Tony Ma A Simulation-Based Protocol-Driven Scan-Test-Design Rule Checker. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy On Achieving Complete Testability of Synchronous Sequential Circuits with Synchronizing Sequences. [Citation Graph (0, 0)][DBLP ] Conf ] Wojciech Maly Integration of Design, Manufacturing and Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Lee Whetsel Navigating Test Access in Systems. [Citation Graph (0, 0)][DBLP ] Conf ] John Andrews Using SCANTM Bridge as an IEEE 1149.1 Protocol Addressable, Multi-Drop, Backplane Test Bus. [Citation Graph (0, 0)][DBLP ] Conf ] Patrick F. McHugh The IEEE P1149.5 MTM-Bus, A Backplane Test and Initialization Interface. [Citation Graph (0, 0)][DBLP ] Conf ] Cary Champlin Backplane Test Bus Selection Criteria. [Citation Graph (0, 0)][DBLP ] Conf ] Robert Gage 1149.1 Scan Control Transport Levels. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth P. Parker Observations on the 1149.x Family of Standards. [Citation Graph (0, 0)][DBLP ] Conf ] William Eklow Optimizing Boundary Scan in a Proprietary Environment. [Citation Graph (0, 0)][DBLP ] Conf ] 