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Conferences in DBLP

International Test Conference (ITC) (itc)
1995 (conf/itc/1995)

  1. Kenneth M. Thompson
    Intel and the Myths of Test. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:10- [Conf]
  2. Philippe Chauveau
    Design and Testing of the On-Ramps to the Information Superhighway. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:11- [Conf]
  3. O. Kebichi, Michael Nicolaidis, Vyacheslav N. Yarmolik
    Exact Aliasing Computation for RAM BIST. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:13-22 [Conf]
  4. Bruce F. Cockburn, Y.-F. Nicole Sat
    Synthesized Transparent BIST for Detecting Scrambled Pattern-Sensitive Faults in RAMs. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:23-32 [Conf]
  5. Luigi Ternullo Jr., R. Dean Adams, John Connor, Garret S. Koch
    Deterministic Self-Test of a High-Speed Embedded Memory and Logic Processor Subsystem. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:33-44 [Conf]
  6. Th. Calin, F. L. Vargas, Michael Nicolaidis
    Upset-Tolerant CMOS SRAM Using Current Monitoring: Prototype and Test Experiments. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:45-53 [Conf]
  7. Peter D. Capofreddi, Bruce A. Wooley
    The Use of Linear Models for the Efficient and Accurate Testing of A/D Converters. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:54-60 [Conf]
  8. Manoj Sachdev, Bert Atzema
    Industrial Relevance of Analog IFA: A Fact or a Fiction. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:61-70 [Conf]
  9. Yukiya Miura
    A Comparative Analysis of Input Stimuli for Testing Mixed-Signal LSIs Based on Curent Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:71-77 [Conf]
  10. Xavier Haurie, Gordon W. Roberts
    Arbitrary-Precision Signal Generation for Bandlimited Mixed-Signal Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:78-86 [Conf]
  11. Solomon Max
    Visualizing Quality. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:87-96 [Conf]
  12. Gerald H. Johnson, Jan B. Wilstrup
    A General Purpose ATE Based IDDQ Measurement Circuit. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:97-105 [Conf]
  13. Karl F. Zimmermann
    SiPROBE - A New Technology for Wafer Probing. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:106-112 [Conf]
  14. Ira Pramanick, Ankan K. Pramanick
    Parallel Delay Fault Coverage and Test Quality Evaluation. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:113-122 [Conf]
  15. Alicja Pierzynska, Slawomir Pilarski
    Non-Robust versus Robust. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:123-131 [Conf]
  16. Mukund Sivaraman, Andrzej J. Strojwas
    Test Vector Generation for Parametric Path Delay Faults. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:132-138 [Conf]
  17. Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal
    Classification and Test Generation for Path-Delay Faults Using Single Stuck-Fault Tests. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:139-148 [Conf]
  18. Graham Hetherington, Greg Sutton, Kenneth M. Butler, Theo J. Powell
    Test Generation and Design for Test for a Large Multiprocessing DSP. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:149-156 [Conf]
  19. Marc E. Levitt, Srinivas Nori, Sridhar Narayanan, G. P. Grewal, Lynn Youngs, Anjali Jones, Greg Billus, Siva Paramanandam
    Testability, Debuggability, and Manufacturability Features of the UltraSPARCTM-I Microprocessor. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:157-166 [Conf]
  20. Jen-Tien Yen, Marie Sullivan, Carlos Montemayor, Pete Wilson, Richard Evers
    Overview of PowerPCTM 620 Multiprocessor Verification Strategy. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:167-174 [Conf]
  21. Hong Hao, Rick Avra
    Structured Design-for-Debug - The SuperSPARCTM II Methodology and Implementation. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:175-183 [Conf]
  22. Bruce C. Kim, Abhijit Chatterjee, Madhavan Swaminathan, David E. Schimmel
    A Novel Low-Cost Approach to MCM Interconnect Test. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:184-192 [Conf]
  23. Kevin T. Kornegay, Kaushik Roy
    Integrated Test Solutions and Test Economics for MCMs. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:193-201 [Conf]
  24. Andrew Flint
    A Comparison of Test Requirements, Methods, and Results for Seven MCM Products. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:202-207 [Conf]
  25. Koppolu Sasidhar, Abhijit Chatterjee, Vinod K. Agarwal, Joseph L. A. Hughes
    Distributed Probabilistic Diagnosis of MCMs on Large Area. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:208-216 [Conf]
  26. James A. Tuttle, Thomas W. Collins, Mary Stone Tuttle
    Matching Models to Real Life for Defect Reduction. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:217-223 [Conf]
  27. Willie Benitez, Deo Marrero, Douglas J. Mirizzi, Dale Ohmart
    Test SPC: A Process to Improve Test System Integrity. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:224-232 [Conf]
  28. Alex M. Ijaz, Eugene R. Hnatek
    User Application of Statistical Process Monitor Techniques to ASIC Critical Parameters. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:233-241 [Conf]
  29. Susan D. Shaye
    A Test Data Collection System for Uniform Data Analysis. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:242-251 [Conf]
  30. Jos van Sas, Erik Huyskens, Hans Naert, Fred Schell, A. J. van de Goor
    Coping with Re-usability Using Sequential ATPG: A Practical Case Study. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:252-261 [Conf]
  31. Ben Mathew, Daniel G. Saab
    DFT & ATPG: Together Again. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:262-271 [Conf]
  32. Irith Pomeranz, Sudhakar M. Reddy
    Low-Complexity Fault Simulation under the Multiplie Observation Time Testing Approach. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:272-281 [Conf]
  33. Stefan Weiner
    A Fault Model and a Test Method for Analog Fuzzy Logic Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:282-291 [Conf]
  34. Thomas L. Anderson
    A Designer's View of Chip Test. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:292- [Conf]
  35. Rabindra K. Roy
    Advantages of High-Level Test Synthesis over Design for Test. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:293- [Conf]
  36. Christian Landrault, Marie-Lise Flottes, Bruno Rouzeyre
    Is High-Level Test Synthesis Just Design for Test? [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:294- [Conf]
  37. Peter C. Maxwell
    The Many Faces of Test Synthesis. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:295- [Conf]
  38. Randall Hassig
    The Case for Contract Manufacturing. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:296- [Conf]
  39. Tom Langford
    Contract Manufacturing: How Much Can They Do? [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:297- [Conf]
  40. Gordon W. Roberts
    Re-examining the Needs of the Mixed-Signal Test. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:298- [Conf]
  41. Keith Baker
    Stuck-at Faults, PPMs Rejects or? What doe the SIA Roadmaps Say? [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:299- [Conf]
  42. John M. Acken
    The Final Barriers to Widespread Use of IDDQ Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:300- [Conf]
  43. Ron Wantuck
    Test Quality: Required Stuck-at Fault Coverage with the Use of IDDQ Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:301- [Conf]
  44. Vishwani D. Agrawal, Tapan J. Chakraborty
    High-Performance Circuit Testing with Slow-Speed Testers. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:302-310 [Conf]
  45. Stephen Pateras, Martin S. Schmookler
    Avoiding Unknown States When Scanning Mutually Exclusive Latches. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:311-318 [Conf]
  46. Richard M. Sedmak, John Evans
    A Hierarchical, Desgin-for-Testability (DFT) Methodology for the Rapid Prototyping of Application-Specific Signal Processors (RASSP). [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:319-327 [Conf]
  47. A. Frisch, Mitch Aigner, T. Almy, Hans J. Greub, M. Hazra, S. Mohr, Nicholas J. Naclerio, W. Russell, M. Stebniskey
    Supplying Known-Good Die for MCM Applications Using Low-Cost Embedded Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:328-335 [Conf]
  48. V. Ramakrishnan, D. M. H. Walker
    IC Performance Prediction System. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:336-344 [Conf]
  49. Fabian Vargas, Michael Nicolaidis, Yervant Zorian
    An Approach for Designing Total-Dose Tolerant MCMs Based on Current Monitoring. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:345-354 [Conf]
  50. Mark Burns
    Improving DSP-Based Measurements with Spectral Interpolation. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:355-363 [Conf]
  51. Luke S. L. Hsieh, Andrew Grochowski
    THD and SNR Tests Using the Simplified Volterra Series with Adaptive Algorithms. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:364-369 [Conf]
  52. Harold Bogard, Celeste Repasky
    Increasing Test Throughput Through the Implementation of Parallel Test on a 16-Bit Multimedia Audio CODEC. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:370-376 [Conf]
  53. Junichi Hirase
    Improvement of the Defect Level of Micro-computer LSI Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:377-383 [Conf]
  54. Janusz Sosnowski
    In-System Testing of Cache Memories. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:384-393 [Conf]
  55. Laurence Goodby, Alex Orailoglu
    Towards 100% Testable FIR Digital Filters. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:394-402 [Conf]
  56. Xinli Gu, Krzysztof Kuchcinski, Zebo Peng
    An Efficient and Economic Partitioning Approach for Testability. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:403-412 [Conf]
  57. Insung Park, Dong Sam Ha, Gyoochan Sim
    A New Method for Partial Scan Design Based on Propagation and Justification Requirements of Faults. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:413-422 [Conf]
  58. Prashant S. Parikh, Miron Abramovici
    On Combining Design for Testability Techniques. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:423-429 [Conf]
  59. Chryssa Dislis, A. F. Al-Ani, Ian P. Jalowiecki
    MCM Quality and Cost Analysis Using Economics Models. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:430-437 [Conf]
  60. Junichi Hirase
    Study on the Costs of On-site VLSI Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:438-443 [Conf]
  61. Stephen K. Sunter
    The P1149.4 Mixed Signal Test Bus: Costs and Benefits. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:444-450 [Conf]
  62. Shuji Kikuchi, Yoshihiko Hayashi, Takashi Suga, Jun Saitou, Masahiko Kaneko, Takashi Matsumoto, Ryozou Yoshino
    A Gate-Array-Based 666MHz VLSI Test System. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:451-458 [Conf]
  63. Jim Chapman, Jeff Currin, Steve Payne
    A Low-Cost High-Performance CMOS Timing Vernier for ATE. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:459-468 [Conf]
  64. Michael G. Davis
    Evaluating Waveform-Generation Capabilities of VLSI Test Systems. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:469-478 [Conf]
  65. Adit D. Singh, Haroon Rasheed, Walter W. Weber
    IDDQ Testing of CMOS Opens: An Experimental Study. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:479-489 [Conf]
  66. Gregory A. Maston
    Production IDDQ Testing with Passive Current Compensation. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:490-497 [Conf]
  67. Robert C. Aitken
    Finding Defects with Fault Models. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:498-505 [Conf]
  68. Kwang-Ting Cheng, Chih-Jen Lin
    Timing-Driven Test Point Insertion for Full-Scan and Partial-Scan BIST. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:506-514 [Conf]
  69. Claus Schotten, Heinrich Meyr
    Test Point Insertion for an Area Efficient BIST. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:515-523 [Conf]
  70. Charles Njinda, Neeraj Kaul
    Performance Driven BIST Technique for Random Logic. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:524-533 [Conf]
  71. Manoj Sachdev
    IDDQ and Voltage Testable CMOS Flip-flop Configurations. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:534-543 [Conf]
  72. Jaume Segura, Carol de Benito, A. Rubio, Charles F. Hawkins
    A Detailed Analysis of GOS Defects in MOS Transistors: Testing Implications at Circuit Level. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:544-551 [Conf]
  73. Jitendra Khare, Wojciech Maly
    Inductive Contamination Analysis (ICA) with SRAM Application. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:552-560 [Conf]
  74. Douglas W. Raymond, D. Eugene Wedge, Philip J. Stringer, Harold W. Ng, Suzanne T. Jennings, Craig T. Pynn, Winsor Soule Jr.
    Algorithmic Extraction of BSDL from 1149.1-compliant Sample ICs. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:561-568 [Conf]
  75. David J. Cheek, Ramaswami Dandapani
    Integration of IEEE Std. 1149.1 and Mixed-Signal Test Architectures. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:569-576 [Conf]
  76. Douglas Reed, Jason Doege, Antonio Rubio
    Improving Board and System Test: A Proposal to Integrate Boundary Scan and IDDQ. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:577-585 [Conf]
  77. Mark C. Hansen, John P. Hayes
    High-Level Test Generation Using Symbolic Scheduling. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:586-595 [Conf]
  78. Mark Kassab, Janusz Rajski, Jerzy Tyszer
    Hierarchical Functional-Fault Simulation for High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:596-605 [Conf]
  79. Samy Makar, Edward J. McCluskey
    Functional Tests for Scan Chain Latches. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:606-615 [Conf]
  80. Li-C. Wang, M. Ray Mercer, Thomas W. Williams
    On Efficiently and Reliably Achieving Low Defective Part Levels. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:616-625 [Conf]
  81. Young-Jun Kwon, D. M. H. Walker
    Yiel Learning via Functional Test Data. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:626-635 [Conf]
  82. Kaushik De, Arun Gunda
    Failure Analysis for Full-Scan Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:636-645 [Conf]
  83. Michael K. Williams
    A Discussion of Methods for Measuring Low-Amplitude Jitter. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:646-652 [Conf]
  84. Piero Franco, William D. Farwell, Robert L. Stokes, Edward J. McCluskey
    An Experimental Chip to Evaluate Test Techniques: Chip and Experiment Design. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:653-662 [Conf]
  85. Siyad C. Ma, Piero Franco, Edward J. McCluskey
    An Experimental Chip to Evaluate Test Techniques: Experiment Results. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:663-672 [Conf]
  86. Andrew Flint
    Using the Right Tools and Techniques leads to Successful Testing of MCMs. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:673- [Conf]
  87. Nur A. Touba, Edward J. McCluskey
    Synthesis of Mapping Logic for Generating Transformed Pseudo-Random Patterns for BIST. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:674-682 [Conf]
  88. Samir Lejmi, Bozena Kaminska, Bechir Ayari
    Synthesis and Retiming for the Pseudo-Exhaustive BIST of Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:683-692 [Conf]
  89. Christos A. Papachristou, Joan Carletta
    Test Synthesis in the Behavioral Domain. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:693-702 [Conf]
  90. Roger Ferguson, Bogdan Korel
    Software Test Data Generation Using the Chaining Approach. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:703-709 [Conf]
  91. Yves Le Traon, Chantal Robach
    From Hardware to Software Testability. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:710-719 [Conf]
  92. Charles Anderson, Anneliese von Mayrhauser, Richard T. Mraz
    On the Use of Neural Networks to Guide Software Testing Activities. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:720-729 [Conf]
  93. John C. Munson, Gregory A. Hall
    Dynamic Program Complexity and Software Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:730-737 [Conf]
  94. Kamalesh N. Ruparel
    Test Synthesis: From Wishful Thinking to Reality. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:738- [Conf]
  95. Keith Baker, T. F. Waayers, F. G. M. Bouwman, M. J. W. Verstraelen
    Plug & Play IDDQ Monitoring with QTAG. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:739-749 [Conf]
  96. Birger Schneider, Soeren Soegaard
    IntegraTEST: The New Wave in Mixed-Signal Test. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:750-760 [Conf]
  97. Jean Qincui Xia, Tom Austin, Nash Khouzam
    Dynamic Test Emulation for EDA-Based Mixed-Signal Test Development Automation. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:761-770 [Conf]
  98. Scot Bullock
    Report on a Pilot Project Successfully Implementing a Design-to-Test Methodology. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:771-780 [Conf]
  99. Chouki Aktouf, Chantal Robach, A. Marinescu
    A Routing Testing of a VLSI Massively Parallel Machine Based on IEEE 1149.1. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:781-788 [Conf]
  100. Wuudiann Ke, Duy Le, Najmi T. Jarwala
    A Secure Data Transmission Scheme for 1149.1 Backplane Test Bus. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:789-796 [Conf]
  101. Rodham E. Tulloss
    Leave the Wires to Last - Funcitonal Evaluation of the IEEE Std 1149.5 Module Test and Maintenance Bus. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:797-806 [Conf]
  102. Des Farren, Anthony P. Ambler
    Cost-Effective System-Level Test Strategies. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:807-813 [Conf]
  103. Chih-Ang Chen, Sandeep K. Gupta
    A Methodology to Design Efficient BIST Test Pattern Generators. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:814-823 [Conf]
  104. Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian
    An Effective BIST Scheme for Booth Multipliers. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:824-833 [Conf]
  105. Krishnendu Chakrabarty, Brian T. Murray, John P. Hayes
    Optimal Space Compaction of Test Responses. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:834-843 [Conf]
  106. Carol Pyron, W. C. Bruce
    Implementing 1149.1 in the PowerPCTM RISC Microprocessor Family. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:844-850 [Conf]
  107. Lee Whetsel
    Improved Boundary Scan Design. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:851-860 [Conf]
  108. Kamal K. Varma
    Compiled Code, Dynamic Worst Case Timing Simulation Tracking Multiple Causality. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:861-869 [Conf]
  109. Ulrich Schoettmer, Toshiyuki Minami
    Challenging the "High Performance - High Cost" Paradigm in Test. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:870-879 [Conf]
  110. Garry C. Gillette
    A Single Board Test System: Changing the Test Paradigm. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:880-885 [Conf]
  111. Gary J. Lesmeister
    A Tester for DesignTM (TFD). [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:886-891 [Conf]
  112. Rafic Z. Makki, Shyang-Tai Su, Troy Nagle
    Transient Power Supply Current Testing of Digital CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:892-901 [Conf]
  113. Hitesh Ahuja, Dean Arriens, Ben Schneller, Vandana Verma, Wendy Whitman
    Intel 386TM EX Embedded Processor IDDQ Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:902-909 [Conf]
  114. Kenneth M. Wallquist
    On the Effect of ISSQ Testing in Reducing Early Failure Rate. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:910-915 [Conf]
  115. Alan W. Righter
    Solving Known Good Die (and Substrate) Test Issues. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:916- [Conf]
  116. David C. Keezer
    Electrical Troubleshooting, Diagnostics, and Repair of Multichip Modules. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:917- [Conf]
  117. Lawrence D. Carpenter
    Required - A Portable Test Standard. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:918- [Conf]
  118. Gregory A. Maston
    STIL from the Users Perspective. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:919- [Conf]
  119. Gary O'Donnell
    It's DFT, Boundary Scan and Life Cycle Benefits. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:920- [Conf]
  120. William R. Simpson
    Cutting the Cost of Test; the Value-added Way. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:921- [Conf]
  121. Prab Varma
    Optimizing Product Profitability - The Test Way. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:922- [Conf]
  122. Kenneth M. Butler
    Deep Submicron: Is Test Up to the Challenge? [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:923- [Conf]
  123. Craig Hunter
    What's So Different about Deep-Submicron Test? [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:924- [Conf]
  124. Kenneth P. Parker, David Greene
    The ITC Lecture Series: An Experiment. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:925- [Conf]
  125. Jack Ferguson
    Finding I/O Faults on In-Circuit ICs Using Parasitic Transistor Tests. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:926- [Conf]
  126. Joe Wrinn
    Two New Techniques for Identifying Opens on Printed Circuit Boards: Analog Junction Test & Radio Frequency Induction Test. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:927- [Conf]
  127. Ted T. Turner
    Capacitive Leadframe Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:928- [Conf]
  128. James Jamieson
    Telecom Test: New Challenges, Old Roots. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:929- [Conf]
  129. Benoît R. Veillette, Gordon W. Roberts
    A Bulti-in Self-Test Strategy for Wireless Communication Systems. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:930-939 [Conf]
  130. Madhuri Jarwala, Duy Le, Michael S. Heutmaker
    End-to-End Test Strategy for Wireless Systems. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:940-946 [Conf]
  131. Stefano Barbagallo, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
    Testing a Switching Memory in a Telcommunication System. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:947-956 [Conf]
  132. Rob Tepper, Jim Tarpo
    Automated 1.5 GHz Sonet Characterization. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:957-965 [Conf]
  133. Michael T. Freeman
    Development of an ATE Test Station for Mixed CATV/TELCO Products. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:966-972 [Conf]
  134. Mark Hoogerbrugge
    Optimizing Test Strategies for SONET/SDH/ATM Network Element Manufacturing. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:973-978 [Conf]
  135. Martin A. Schulman
    End-to-End Performance Measurement for Interactive Multimedia Television. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:979-985 [Conf]
  136. Harry Hulvershorn, Paul Soong, Saman Adham
    Linking Diagnostic Software to Hardware Self Test in Telecom Systems. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:986-993 [Conf]
  137. Benoit Nadeau-Dostie, Harry Hulvershorn, Saman Adham
    A New Hardware Fault Insertion Scheme for System Diagnostics Verification. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:994-1002 [Conf]
NOTICE1
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NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
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