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Conferences in DBLP

International Test Conference (ITC) (itc)
1999 (conf/itc/1999)

  1. David R. Lakin II, Adit D. Singh
    Exploiting defect clustering to screen bare die for infant mortality failures: an experimental study. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:23-30 [Conf]
  2. Bruce C. Kim, Pinshan Jiang, Se Hyun Park
    A probe scheduling algorithm for MCM substrates. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:31-37 [Conf]
  3. Alfredo Benso, Silvia Chiusano, Paolo Prinetto, Simone Giovannetti, Riccardo Mariani, Silvano Motto
    Testing an MCM for high-energy physics experiments: a case study. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:38-46 [Conf]
  4. Bram Kruseman, Peter Janssen, Victor Zieren
    Transient current testing of 0.25 /spl mu/m CMOS devices. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:47-56 [Conf]
  5. Wanli Jiang, Bapiraju Vinnakota
    Statistical threshold formulation for dynamic I_dd test. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:57-66 [Conf]
  6. Amy Germida, Zheng Yan, James F. Plusquellic, Fidel Muradali
    Defect detection using power supply transient signal analysis. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:67-76 [Conf]
  7. Stefan Gerstendorfer, Hans-Joachim Wunderlich
    Minimized power consumption for scan-based BIST. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:77-84 [Conf]
  8. Seongmoon Wang, Sandeep K. Gupta
    LT-RTPG: a new test-per-scan BIST TPG for low heat dissipation. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:85-94 [Conf]
  9. Jayabrata Ghosh-Dastidar, Debaleena Das, Nur A. Touba
    Fault diagnosis in scan-based BIST using both time and space information. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:95-102 [Conf]
  10. Hari Balachandran, Jason Parker, Gordon Gammie, John W. Olson, Craig Force, Kenneth M. Butler, Sri Jandhyala
    Expediting ramp-to-volume production. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:103-112 [Conf]
  11. Andrew C. Evans
    Applications of semiconductor test economics, and multisite testing to lower cost of test. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:113-123 [Conf]
  12. Norma Barrett, Simon Martin, Chryssa Dislis
    Test process optimization: closing the gap in the defect spectrum. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:124-129 [Conf]
  13. Timothy J. Wood
    The test and debug features of the AMD-K7 microprocessor. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:130-136 [Conf]
  14. Carol Pyron, Mike Alexander, James Golab, George Joos, Bruce Long, Robert F. Molyneaux, Rajesh Raina, Nandu Tendolkar
    DFT advances in the Motorola's MPC7400, a PowerPC G4 microprocessor. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:137-146 [Conf]
  15. Anjali Kinra
    Towards reducing "functional only" fails for the UltraSPARC microprocessors. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:147-154 [Conf]
  16. Stehpehn F. Scheiber
    Breaking the complexity spiral in board test. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:155-158 [Conf]
  17. Adam W. Ley
    The integration of boundary-scan test methods to a mixed-signal environment. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:159-162 [Conf]
  18. Thomas A. Ziaja
    Using LSSD to test modules at the board level. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:163-170 [Conf]
  19. Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer
    Switch-level delay test. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:171-180 [Conf]
  20. Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng
    Delay testing considering power supply noise effects. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:181-190 [Conf]
  21. Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer
    Test generation for crosstalk-induced delay in integrated circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:191-200 [Conf]
  22. Spyros Tragoudas
    Accurate path delay fault coverage is feasible. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:201-210 [Conf]
  23. Clifford B. Cole, Thomas P. Warwick
    High speed digital transceivers: A challenge for manufacturing. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:211-215 [Conf]
  24. Dino Ren Tao
    A new approach to RF impedance test. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:216-220 [Conf]
  25. Jeongjin Roh, Jacob A. Abraham
    Subband filtering scheme for analog and mixed-signal circuit testing. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:221-229 [Conf]
  26. Abdelhakim Khouas, Anne Derieux
    Speed-up of high accuracy analog test stimulus optimization. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:230-236 [Conf]
  27. J. J. O. Riordan
    Design of a test simulation environment for test program development. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:237-244 [Conf]
  28. Mitsuo Matsumoto, Yoshiharu Ikeda
    Automatic timing margin failure location analysis by CycleStretch method. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:245-251 [Conf]
  29. David A. Bonnett
    Design for In-System Programming. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:252-259 [Conf]
  30. Ramesh C. Tekumalla, Premachandran R. Menon
    Robust testability of primitive faults using test points. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:260-268 [Conf]
  31. Eric MacDonald, Nur A. Touba
    Delay testing of SOI circuits: Challenges with the history effect. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:269-275 [Conf]
  32. Mansour Shashaani, Manoj Sachdev
    A DFT technique for high performance circuit testing. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:276-285 [Conf]
  33. Adit D. Singh, Egor S. Sogomonyan, Michael Gössel, Markus Seuring
    Testability evaluation of sequential designs incorporating the multi-mode scannable memory element. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:286-293 [Conf]
  34. Jeff Rearick
    Practical scan test generation and application for embedded FIFOs. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:294-300 [Conf]
  35. Shigeru Nakahara, Keiichi Higeta, Masaki Kohno, Toshiaki Kawamura, Keizo Kakitani
    Built-in self-test for GHz embedded SRAMs using flexible pattern generator and new repair algorithm. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:301-310 [Conf]
  36. Dilip K. Bhavsar
    An algorithm for row-column self-repair of RAMs and its implementation in the Alpha 21264. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:311-318 [Conf]
  37. Benoît Charlot, Salvador Mir, Érika F. Cota, Marcelo Lubaszewski, Bernard Courtois
    Fault modeling of suspended thermal MEMS. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:319-328 [Conf]
  38. Tao Jiang, Ronald D. Blanton
    Particulate failures for surface-micromachined MEMS. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:329-337 [Conf]
  39. Richard W. Beegle, Robert W. Brocato, Ronald W. Grant
    IMEMS accelerometer testing-test laboratory development and usage. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:338-347 [Conf]
  40. Michinobu Nakao, Seiji Kobayashi, Kazumi Hatayama, Kazuhiko Iijima, Seiji Terada
    Low overhead test point insertion for scan-based BIST. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:348-357 [Conf]
  41. Graham Hetherington, Tony Fryars, Nagesh Tamarapalli, Mark Kassab, Abu S. M. Hassan, Janusz Rajski
    Logic BIST for large industrial designs: real issues and case studies. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:358-367 [Conf]
  42. Grzegorz Mrugalski, Jerzy Tyszer, Janusz Rajski
    Synthesis of pattern generators based on cellular automata with phase shifters. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:368-377 [Conf]
  43. Minh Quach, Rich Samuelson, David Shaw
    Characterization and optimization of the production probing process. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:378-387 [Conf]
  44. Dean A. Gahagan
    RF (gigahertz) ATE production testing on wafer: options and tradeoffs. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:388-395 [Conf]
  45. Jerry J. Broz, Reynaldo M. Rincon
    Probe contact resistance variations during elevated temperature wafer test. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:396-405 [Conf]
  46. Sezer Gören, F. Joel Ferguson
    Checking sequence generation for asynchronous sequential elements. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:406-413 [Conf]
  47. Manfred Stadler, Thomas Röwer, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner, Markus Thalmann
    Functional verification of intellectual properties (IP): a simulation-based solution for an application-specific instruction-set processor. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:414-420 [Conf]
  48. Kyung Tek Lee, Jacob A. Abraham
    Critical path identification and delay tests of dynamic circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:421-430 [Conf]
  49. Benoit Nadeau-Dostie, Jean-Francois Cote, Harry Hulvershorn, Stephen Pateras
    An embedded technique for at-speed interconnect testing. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:431-438 [Conf]
  50. Alex Biewenga, Henk D. L. Hollmann, Frans de Jong, Maurice Lousberg
    Static component interconnect test technology (SCITT) a new technology for assembly testing. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:439-448 [Conf]
  51. Yuejian Wu, Paul Soong
    Interconnect delay fault testing with IEEE 1149.1. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:449-457 [Conf]
  52. Hari Balachandran, Jason Parker, Daniel Shupp, Stephanie Butler, Kenneth M. Butler, Craig Force, Jason Smith
    Correlation of logical failures to a suspect process step. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:458-476 [Conf]
  53. Michel Renovell, André Ivanov, Yves Bertrand, Florence Azaïs, Sumbal Rafiq
    Optimal conditions for Boolean and current detection of floating gate faults. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:477-486 [Conf]
  54. Luis Basto, Asif Khan, Pete Hodakievic
    Embedded X86 testing methodology. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:487-492 [Conf]
  55. Peter Harrod
    Testing reusable IP-a case study. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:493-498 [Conf]
  56. Rochit Rajsuman
    Testing a system-on-a-chip with embedded microprocessor. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:499-508 [Conf]
  57. Y. Cai, W. R. Ortner, C. T. Garrenton
    Towards a standardized procedure for automatic test equipment timing accuracy evaluation. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:509-517 [Conf]
  58. Wajih Dalal, Song Miao
    The value of tester accuracy. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:518-523 [Conf]
  59. Thomas P. Warwick, Jung Cho, Yi Cai, Bill Ortner
    An accurate simulation model of the ATE test environment for very high speed devices. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:524-531 [Conf]
  60. Stephen K. Sunter, Aubin Roy
    BIST for phase-locked loops in digital applications. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:532-540 [Conf]
  61. B. Provost, E. Sanchez-Sinencio
    Auto-calibrating analog timer for on-chip testing. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:541-548 [Conf]
  62. Gloria Huertas, Diego Vázquez, Adoración Rueda, José L. Huertas
    Effective oscillation-based test for application to a DTMF filter bank. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:549-555 [Conf]
  63. Frans de Jong, Rob Raaijmakers
    Static component interconnection test technology in practice. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:556-565 [Conf]
  64. David Rahe
    The HASS development process. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:566-576 [Conf]
  65. Cherif Ahrikencheikh, Michael Spears
    Limited access testing of analog circuits: handling tolerances. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:577-586 [Conf]
  66. R. Scott Fetherston, Imtiaz P. Shaik, Siyad C. Ma
    A comparison of bridging fault simulation methods. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:587-595 [Conf]
  67. Vijay R. Sar-Dessai, D. M. H. Walker
    Resistive bridge fault modeling, simulation and test generation. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:596-605 [Conf]
  68. Sitaran Yadavalli, Sudhakar M. Reddy
    SymSim: symbolic fault simulation of data-flow data-path designs at the Register-Transfer level. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:606-615 [Conf]
  69. Yervant Zorian, Erik Jan Marinissen, Rohit Kapur, Tony Taylor, Lee Whetsel
    Towards a standard for embedded core test: an example. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:616-627 [Conf]
  70. Robert C. Aitken, Fidel Muradali
    Trends in SLI design and their effect on test. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:628-637 [Conf]
  71. Jos van Beers, Harry Van Herten
    Test features of a core-based co-processor array for video applications. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:638-647 [Conf]
  72. Bozena Kaminska
    Is Analog Fault Simulation a Key to Product Quality? Practical Considerations. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:648-648 [Conf]
  73. Eugene R. Atwood
    Analog Fault Simulation: Need it? No. It is already done. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:649- [Conf]
  74. Craig Force
    Analog Fault Simulation: Key to Product Quality, or a Foot in the Door. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:650- [Conf]
  75. Hosam Haggag
    Closing The Gap Between Process Development and Mixed Signal Design and Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:651- [Conf]
  76. Cecilia Metra, Flavio Giovanelli, Mani Soma, Bruno Riccò
    Self-checking scheme for very fast clocks' skew correction. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:652-661 [Conf]
  77. Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey
    A design diversity metric and reliability analysis for redundant systems. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:662-671 [Conf]
  78. Chaohuang Zeng, Nirmal R. Saxena, Edward J. McCluskey
    Finite state machine synthesis with concurrent error detection. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:672-679 [Conf]
  79. Simon Martin, Robert Bleck, Chryssa Dislis, Des Farren
    The evolution of a system test process [for Motorola GSM products]. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:680-688 [Conf]
  80. Susana Stoica
    System design verification tests - an overview. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:689-697 [Conf]
  81. David Williams
    PC manufacturing test in a high volume environment. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:698-704 [Conf]
  82. Gordon D. Robinson
    DFT, test lifecycles and the product lifecycle. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:705-713 [Conf]
  83. Claude Thibeault
    An histogram based procedure for current testing of active defects. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:714-723 [Conf]
  84. Anthony C. Miller
    I/sub DDQ/ testing in deep submicron integrated circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:724-729 [Conf]
  85. Sri Jandhyala, Hari Balachandran, Anura P. Jayasumana
    Clustering based techniques for I_DDQ testing. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:730-737 [Conf]
  86. Peter C. Maxwell, Pete O'Neill, Robert C. Aitken, Ronald Dudley, Neal Jaarsma, Minh Quach, Don Wiseman
    Current ratios: a self-scaling technique for production I_DDQ testing. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:738-746 [Conf]
  87. Turker Kuyel
    Linearity testing issues of analog to digital converters. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:747-756 [Conf]
  88. Nico Csizmadia, Augustus J. E. M. Janssen
    Estimating the integral non-linearity of A/D-converters via the frequency domain. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:757-762 [Conf]
  89. Solomon Max
    Testing high speed high accuracy analog to digital converters embedded in systems on a chip. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:763-771 [Conf]
  90. Turker Kuyel, Haydar Bilhan
    Relating linearity test results to design flaws of pipelined analog to digital converters. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:772-779 [Conf]
  91. Burnell G. West
    Accuracy requirements in at-speed functional test. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:780-787 [Conf]
  92. Mike P. Li, Jan B. Wilstrup, Ross Jessen, Dennis Petrich
    A new method for jitter decomposition through its distribution tail fitting. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:788-794 [Conf]
  93. Burnell G. West
    At-speed structural test. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:795-800 [Conf]
  94. David C. Keezer, Q. Zhou
    Test support processors for enhanced testability of high performance circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:801-809 [Conf]
  95. Magdy S. Abadir, Rajesh Raina
    Design-for-test methodology for Motorola PowerPC microprocessors. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:810-819 [Conf]
  96. M. H. Konijnenburg, J. Th. van der Linden, A. J. van de Goor
    Testability of the Philips 80C51 micro-controller. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:820-829 [Conf]
  97. Li-C. Wang, Magdy S. Abadir
    Tradeoff analysis for producing high quality tests for custom circuits in PowerPC microprocessors. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:830-838 [Conf]
  98. Kenneth M. Butler
    A study of test quality/tester scan memory trade-offs using the SEMATECH test methods data. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:839-847 [Conf]
  99. Susana Stoica
    Robust test methods applied to functional design verification. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:848-857 [Conf]
  100. Sandhyo Seshadri, Michael S. Hsiao
    An integrated approach to behavioral-level design-for-testability using value-range and variable testability techniques. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:858-867 [Conf]
  101. Lee A. Shombert, Danny C. Davis, Eric M. Bukata
    The test requirements model (TeRM) communicating test information throughout the product life cycle. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:868-876 [Conf]
  102. Richard H. Livengood, Donna Medeiros
    Design for (physical) debug for silicon microsurgery and probing of flip-chip packaged integrated circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:877-882 [Conf]
  103. William V. Huott, Moyra K. McManus, Daniel R. Knebel, Steve Steen, Dennis Manzer, Pia Sanda, Steven Wilson, Yuen Chan, Antonio Pelella, Stanislav Polonsky
    The attack of the "Holey Shmoos": a case study of advanced DFD and picosecond imaging circuit analysis (PICA). [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:883-891 [Conf]
  104. Gert-Jan van Rootselaar, Bart Vermeulen
    Silicon debug: scan chains alone are not enough. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:892-902 [Conf]
  105. Han Bin Kim, Dong Sam Ha
    A high-level BIST synthesis method based on a region-wise heuristic for an integer linear programming. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:903-912 [Conf]
  106. Alfred L. Crouch, Michael Mateja, Teresa L. McLaurin, John C. Potter, Dat Tran
    The testability features of the 3rd generation ColdFire family of microprocessors. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:913-922 [Conf]
  107. Irith Pomeranz, Sudhakar M. Reddy
    On achieving complete coverage of delay faults in full scan circuits using locally available lines. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:923-931 [Conf]
  108. Keneth R. Wilsher, William K. Lo
    Practical optical waveform probing of flip-chip CMOS devices. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:932-939 [Conf]
  109. Tagashi Kitagaki
    Flexible ATE module with reconfigurable circuit and its application [to CMOS imager test]. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:940-946 [Conf]
  110. Koji Asami, Shinsuke Tajiri
    A method to improve the performance of high-speed waveform digitizing. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:947-954 [Conf]
  111. Sudip Chakrabarti, Abhijit Chatterjee
    On-line fault detection in DSP circuits using extrapolated checksums with minimal test points. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:955-963 [Conf]
  112. Matthias Pflanz, Heinrich Theodor Vierhaus, F. Pompsch
    An efficient on-line-test and back-up scheme for embedded processors. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:964-972 [Conf]
  113. Miron Abramovici, Charles E. Stroud, Carter Hamilton, Sajitha Wijesuriya, Vinay Verma
    Using roving STARs for on-line testing and diagnosis of FPGAs in fault-tolerant applications. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:973-982 [Conf]
  114. A. J. van de Goor, Ivo Schanstra
    Industrial evaluation of stress combinations for march tests applied to SRAMs. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:983-992 [Conf]
  115. Monica Lobetti Bodoni, Alessio Pricco, Alfredo Benso, Silvia Chiusano, Paolo Prinetto
    An on-line BISTed SRAM IP core. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:993-1000 [Conf]
  116. Said Hamdioui, A. J. van de Goor
    Port interference faults in two-port memories. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1001-1010 [Conf]
  117. Peter Wohl, John A. Waicukauski
    Using Verilog simulation libraries for ATPG. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1011-1020 [Conf]
  118. Kuo-Hui Tsai, Tompson, Janusz Rajski, Malgorzata Marek-Sadowska
    STAR-ATPG: a high speed test pattern generator for large scan designs. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1021-1030 [Conf]
  119. Jennifer Dworak, Michael R. Grimaila, Sooryong Lee, Li-C. Wang, M. Ray Mercer
    Modeling the probability of defect excitation for a commercial IC with implications for stuck-at fault-based ATPG strategies. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1031-1037 [Conf]
  120. Alfredo Benso, Silvia Cataldo, Silvia Chiusano, Paolo Prinetto, Yervant Zorian
    HD-BIST: a hierarchical framework for BIST scheduling and diagnosis in SOCs. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1038-1044 [Conf]
  121. Hyungwon Kim, John P. Hayes
    Delay fault testing of IP-based designs via symbolic path modeling. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1045-1054 [Conf]
  122. Lee Whetsel
    Addressable test ports an approach to testing embedded cores. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1055-1064 [Conf]
  123. David B. Lavo, Tracy Larrabee, Jonathon E. Colburn
    Eliminating the Ouija board: automatic thresholds and probabilistic I_DDQ diagnosis. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1065-1072 [Conf]
  124. Peilin Song, Franco Motika, Daniel R. Knebel, Rick Rizzolo, Mary P. Kusko, Julie Lee, Moyra K. McManus
    Diagnostic techniques for the IBM S/390 600 MHz G5 microprocessor. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1073-1082 [Conf]
  125. Yun Shao, Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz
    The effects of test compaction on fault diagnosis. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1083-1089 [Conf]
  126. Jim Johnson
    Is DFT right for you? [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1090-1097 [Conf]
  127. Jon Turino
    Design for test and time to market-friends or foes. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1098-1101 [Conf]
  128. Bulent Dervisolu
    Design for testability: it is time to deliver it for Time-to-Market. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1102-1111 [Conf]
  129. Mahesh A. Iyer
    High Time For High Level ATPG. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1112- [Conf]
  130. Wu-Tung Cheng
    High time for high level ATPG. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1113- [Conf]
  131. Scott Davidson
    Changing our Path to High Level ATPG. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1114- [Conf]
  132. Rohit Kapur
    High level ATPG is important and is on its way! [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1115-1116 [Conf]
  133. Christos A. Papachristou
    High Time for Higher Level BIST. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1117- [Conf]
  134. Matteo Sonza Reorda
    High-level ATPG: a real topic or an academic amusement? [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1118- [Conf]
  135. Wolfgang Roethig
    High-level ATPG for Early Power Analysis. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1119-1120 [Conf]
  136. Keith Baker
    SIA Roadmaps: Sunset Boulevard for l_DDQ. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1121- [Conf]
  137. Jeffrey L. Roehr
    Thin Gate Oxide Reliability. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1122- [Conf]
  138. E. James Prendergast
    Applying lessons learned from TDDB testing. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1123-1124 [Conf]
  139. Scott Davidson
    ITC'99 Benchmark Circuits - Preliminary Results. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1125- [Conf]
  140. Chouki Aktouf
    Scan Insertion at the Behavioral Level. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1126- [Conf]
  141. Mario H. Konijnenburg, Hans van der Linden, Jeroen Geuzebroek
    Benchmarking DAT with the ITC'99 ATPG Benchmarks. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1127- [Conf]
  142. Sudhakar M. Reddy
    Application of Tools Developed at the University of Iowa to ITC Benchmarks. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1128- [Conf]
  143. Jean François Santucci, Cristophe Paoli
    High level test bench generation using software engineering concepts. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1129- [Conf]
  144. Raghuram S. Tapuri
    Automatic Functional Test Generation - A Reality. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1130- [Conf]
  145. Vishwani D. Agrawal
    Panel: Increasing test coverage in a VLSI desgin course. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1131- [Conf]
  146. Jacob A. Abraham
    Position Statement: Increasing Test Coverage in a VLSI Design Course. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1132- [Conf]
  147. Michael L. Bushnell
    Increasing Test Coverage in a VLSI Design Course. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1133- [Conf]
  148. John Harrington
    VLSI design 101 - The test module. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1134- [Conf]
  149. Michel Robert
    Increasing test coverage in a VLSI design course. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1135- [Conf]
  150. Mani Soma
    Panel Statement: Increasing test coverage in a VLSI design course. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1136- [Conf]
  151. Wayne Wolf
    Position Statement: Testing in a VLSI Design Course. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1137- [Conf]
  152. Frans de Jong
    SCITT: Back to Basics in Mass Production Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1138- [Conf]
  153. Frank W. Angelotti
    SCITT: Bringing DRAMs Into the Test Fold. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1139- [Conf]
  154. Steffen Hellmold
    Static Component Interconnection Test Technology (SCITT). [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1140- [Conf]
  155. David M. Wu
    DFT is all I can afford, who cares about Design for Yield or Design for Reliability! [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1141-1142 [Conf]
  156. Robert C. Aitken
    It Makes Sense to Combine DFT and DFR/DFY. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1143- [Conf]
  157. R. Scott Fetherston
    DFT, DFY, DFR: Who Cares? [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1144- [Conf]
  158. James A. Monzel
    DFT, DFY, and DFR; Which One(s) Do You Worry About? [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1145- [Conf]
  159. D. M. H. Walker
    Design for Yield and Reliability is MORE Important Than DFT. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1146- [Conf]
  160. David M. Wu
    "DFY and DFR are more important than DFT". [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1147- [Conf]
  161. Peter Wohl
    Output in still, input in still. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1148- [Conf]
  162. Nathan Biggs
    STIL: the device-oriented database for the test development lifecycle. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1149- [Conf]
  163. Brion L. Keller
    Using STIL to describe embedded core test requirements. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1150- [Conf]
  164. Marc Loranger
    Is there a STIL for mixed signal testing? [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1151- [Conf]
  165. Phil Nigh, David P. Vallett, Atul Patel, Jason Wright, Franco Motika, Donato Forlenza, Ray Kurtulik, Wendy Chong
    Failure analysis of timing and IDDq-only failures from the SEMATECH test methods experiment. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1152-1161 [Conf]
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NOTICE2
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