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Conferences in DBLP

International Test Conference (ITC) (itc)
2000 (conf/itc/2000)

  1. L. Derere
    Case-based reasoning: diagnosis of faults in complex systems through reuse of experience. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:27-34 [Conf]
  2. Jacob Savir
    On-line and off-line test of airborne digital systems: a reliability study. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:35-44 [Conf]
  3. Stephen Harrison, Peter Collins, Greg Noeninckx
    The implementation of IEEE Std 1149.1 boundary scan test strategy within a cellular infrastructure production environment. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:45-54 [Conf]
  4. Martin Bell, Givargis Danialy, Michael C. Howells, Stephen Pateras
    Bridging the gap between embedded test and ATE. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:55-63 [Conf]
  5. Bruce R. Parnas
    Doing it in STIL: intelligent conversion from STIL to an ATE format. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:64-71 [Conf]
  6. Andy Kittross
    Easy mixed signal test creation with test elements and procedures. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:72-79 [Conf]
  7. Travis M. Eiles, Keneth R. Wilsher, William K. Lo, G. Xiao
    Optical interferometric probing of advanced microprocessors. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:80-84 [Conf]
  8. Chien-Mo James Li, Edward J. McCluskey
    Testing for tunneling opens. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:85-94 [Conf]
  9. Will Moore, Guido Gronthoud, Keith Baker, Maurice Lousberg
    Delay-fault testing and defects in deep sub-micron ICs-does critical resistance really mean anything? [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:95-104 [Conf]
  10. Gundolf Kiefer, Hans-Joachim Wunderlich, Harald P. E. Vranken, Erik Jan Marinissen
    Application of deterministic logic BIST on industrial circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:105-114 [Conf]
  11. Debaleena Das, Nur A. Touba
    Reducing test data volume using external/LBIST hybrid test patterns. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:115-122 [Conf]
  12. Michael Cogswell, Don Pearl, James Sage, Alan Troidl
    Test structure verification of logical BIST: problems and solutions. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:123-130 [Conf]
  13. Rajesh Raina, Robert Bailey, Dawit Belete, Vikram Khosa, Robert F. Molyneaux, Javier Prado, Ashutosh Razdan
    DFT advances in Motorola's Next-Generation 74xx PowerPCTM microprocessor. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:131-140 [Conf]
  14. Farideh Golshan
    Test and on-line debug capabilities of IEEE Std 1149.1 in UltraSPARC-III microprocessor. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:141-150 [Conf]
  15. Teresa L. McLaurin, Frank Frederick
    The testability features of the MCF5407 containing the 4th generation ColdFire(R) microprocessor core. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:151-159 [Conf]
  16. Zan Yang, Byeong Min, Gwan Choi
    Si-emulation: system verification using simulation and emulation. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:160-169 [Conf]
  17. Alfredo Benso, Silvia Chiusano, Paolo Prinetto
    A software development kit for dependable applications in embedded systems. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:170-178 [Conf]
  18. Subhasish Mitra, Edward J. McCluskey
    Combinational logic synthesis for diversity in duplex systems. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:179-188 [Conf]
  19. W. Robert Daasch, James McNames, Daniel Bockelman, Kevin Cota
    Variance reduction using wafer patterns in I_ddQ data. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:189-198 [Conf]
  20. Yukio Okuda
    DECOUPLE: defect current detection in deep submicron I_DDQ. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:199-206 [Conf]
  21. Claude Thibeault
    Improving Delta-I_DDQ-based test methods. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:207-216 [Conf]
  22. Pramodchandran N. Variyam
    Increasing the IDDQ test resolution using current prediction. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:217-224 [Conf]
  23. Xiaoming Yu, Jue Wu, Elizabeth M. Rudnick
    Diagnostic test generation for sequential circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:225-234 [Conf]
  24. Kazuki Shigeta, Toshio Ishiyama
    An improved fault diagnosis algorithm based on path tracing with dynamic circuit extraction. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:235-244 [Conf]
  25. Pankaj Pant, Abhijit Chatterjee
    Path-delay fault diagnosis in non-scan sequential circuits with at-speed test application. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:245-252 [Conf]
  26. Srikanth Venkataraman, Scott Brady Drummonds
    POIROT: a logic fault diagnosis tool and its applications. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:253-262 [Conf]
  27. Subrata Roy, Gokhan Guner, Kwang-Ting Cheng
    Efficient test mode selection and insertion for RTL-BIST. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:263-272 [Conf]
  28. Ismet Bayraktaroglu, Alex Orailoglu
    Deterministic partitioning techniques for fault diagnosis in scan-based BIST. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:273-282 [Conf]
  29. Yasuo Sato, Toyohito Ikeya, Machinobu Nakao, Takaharu Nagumo
    A BIST approach for very deep sub-micron (VDSM) defects. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:283-291 [Conf]
  30. M. J. Geuzebroek, J. Th. van der Linden, A. J. van de Goor
    Test point insertion for compact test sets. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:292-301 [Conf]
  31. Qiushuang Zhang, Ian G. Harris
    A domain coverage metric for the validation of behavioral VHDL descriptions. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:302-308 [Conf]
  32. Chung-Yang Huang, Bwolen Yang, Huan-Chih Tsai, Kwang-Ting Cheng
    Static property checking using ATPG vs. BDD techniques. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:309-316 [Conf]
  33. Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara, Atsushi Murakami, Sadami Takeoka, Mitsuyasu Ohta
    On validating data hold times for flip-flops in sequential circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:317-325 [Conf]
  34. Nabil M. Abdulrazzaq, Sandeep K. Gupta
    Test generation for path-delay faults in one-dimensional iterative logic arrays. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:326-335 [Conf]
  35. Edward J. McCluskey, Chao-Wen Tseng
    Stuck-fault tests vs. actual defects. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:336-343 [Conf]
  36. Ronald A. Richmond
    Successful implementation of structured testing. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:344-348 [Conf]
  37. Pramodchandran N. Variyam, Vinay Agrawal
    Measuring code edges of ADCs using interpolation and its application to offset and gain error testing. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:349-357 [Conf]
  38. Sasikumar Cherubal, Abhijit Chatterjee
    Optimal INL/DNL testing of A/D converters using a linear model. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:358-366 [Conf]
  39. Turker Kuyel, Frank Tsay
    Optimal analog trim techniques for improving the linearity of pipeline ADCs. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:367-375 [Conf]
  40. Atsushi Murakami, Seiji Kajihara, Tsutomu Sasao, Irith Pomeranz, Sudhakar M. Reddy
    Selection of potentially testable path delay faults for test generation. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:376-384 [Conf]
  41. Manish Sharma, Janak H. Patel
    Enhanced delay defect coverage with path-segments. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:385-392 [Conf]
  42. Haluk Konuk
    On invalidation mechanisms for non-robust delay tests. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:393-399 [Conf]
  43. Peter C. Maxwell, Ismed Hartanto, Lee Bentz
    Comparing functional and structural tests. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:400-407 [Conf]
  44. Jayashree Saxena, Kenneth M. Butler
    An empirical study on the effects of test type ordering on overall test efficiency. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:408-416 [Conf]
  45. Jais Abraham, Narayan Prasad, Srinivasa Chakravarthy B. S., Ameet Bagwe, Rubin A. Parekhji
    A framework to evaluate test tradeoffs in embedded core based systems-case study on TI's TMS320C27xx. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:417-425 [Conf]
  46. A. J. van de Goor, A. Paalvast
    Industrial evaluation of DRAM SIMM tests. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:426-435 [Conf]
  47. Herold Pilo, Stu Hall, Patrick Hansen, Steve Lamphier, Chris Murphy
    Design-for-test methods for stand-alone SRAMs at 1 Gb/s/pin and beyond. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:436-443 [Conf]
  48. John Privitera, Steven Woo, Craig Soldat
    Pattern generation tools for the development of memory core test patterns for Rambus devices. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:444-453 [Conf]
  49. Phil Nigh, Anne E. Gattiker
    Test method evaluation experiments and data. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:454-463 [Conf]
  50. Mike Rodgers
    Defect screening challenges in the Gigahertz/Nanometer age: keeping up with the tails of defect behaviors. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:464-467 [Conf]
  51. Jerry Katz, Rochit Rajsuman
    A new paradigm in test for the next millennium. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:468-476 [Conf]
  52. Jerry J. Broz, James C. Andersen, Reynaldo M. Rincon
    Reducing device yield fallout at wafer level test with electrohydrodynamic (EHD) cleaning. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:477-484 [Conf]
  53. Cristo da Costa
    Hardware for production test of RFID interface embedded into chips for smart cards and labels used in contactless applications. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:485-491 [Conf]
  54. Yi Zhao, Sujit Dey
    Analysis of interconnect crosstalk defect coverage of test sets. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:492-501 [Conf]
  55. Rahul Kundu, Ronald D. Blanton
    Identification of crosstalk switch failures in domino CMOS circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:502-509 [Conf]
  56. Toshiyuki Maeda, Kozo Kinoshita
    Precise test generation for resistive bridging faults of CMOS combinational circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:510-519 [Conf]
  57. Dong Xiang, Yi Xu, Hideo Fujiwara
    Non-scan design for testability for synchronous sequential circuits based on conflict analysis. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:520-529 [Conf]
  58. Robert Butler, Brion L. Keller, Sarala Paliwal, Richard Schoonover, Joseph Swenton
    Design and implementation of a parallel automatic test pattern generation algorithm with low test vector count. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:530-537 [Conf]
  59. Mark W. Weiss, Sharad C. Seth, Shashank K. Mehta, Kent L. Einspahr
    Exploiting don't cares to enhance functional tests. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:538-546 [Conf]
  60. Kamran Zarrineh, R. Dean Adams, Thomas J. Eckenrode, Steven P. Gregor
    Self test architecture for testing complex memory structures. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:547-556 [Conf]
  61. Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto, Monica Lobetti Bodoni
    A programmable BIST architecture for clusters of multiple-port SRAMs. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:557-566 [Conf]
  62. Tomoya Kawagoe, Jun Ohtani, Mitsutaka Niiro, Tukasa Ooishi, Mitsuhiro Hamada, Hideto Hidaka
    A built-in self-repair analyzer (CRESTA) for embedded DRAMs. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:567-574 [Conf]
  63. Frans de Jong, Ben Kup, Rodger Schuttert
    Power pin testing: making the test coverage complete. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:575-584 [Conf]
  64. Robert W. Barr, Chen-Huan Chiang, Edward L. Wallace
    End-to-end testing for boards and systems using boundary scan. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:585-592 [Conf]
  65. David McClintock, Lance Cunningham, Takis Petropoulos
    Motherboard testing using the PCI bus. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:593-599 [Conf]
  66. Yongming Cai, T. P. Warwick, Sunil G. Rane, E. Masserrat
    Digital serial communication device testing and its implications on automatic test equipment architecture. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:600-609 [Conf]
  67. Dieu Van Dinh, Virginia Rabitoy
    An approach to testing 200 ps echo clock to output timing on the double data rate synchronous memory. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:610-618 [Conf]
  68. Luca Sartori, Burnell G. West
    The path to one-picosecond accuracy. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:619-627 [Conf]
  69. Steven F. Oakland
    Considerations for implementing IEEE 1149.1 on system-on-a-chip integrated circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:628-637 [Conf]
  70. Helmut Lang, Jens Pfeiffer, Jeff Maguire
    Using on-chip test pattern compression for full scan SoC designs. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:638-643 [Conf]
  71. Silvia Chiusano, Paolo Prinetto, Hans-Joachim Wunderlich
    Non-intrusive BIST for systems-on-a-chip. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:644-651 [Conf]
  72. Patrick Girard, Christian Landrault, Loïs Guiller, Serge Pravossoudovitch
    Low power BIST design by hypergraph partitioning: methodology and architectures. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:652-661 [Conf]
  73. Nicola Nicolici, Bashir M. Al-Hashimi
    Power conscious test synthesis and scheduling for BIST RTL data paths. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:662-671 [Conf]
  74. David Berthelot, Marie-Lise Flottes, Bruno Rouzeyre
    BISTing data paths at behavioral level. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:672-680 [Conf]
  75. Peter Wohl, John A. Waicukauski
    Optimizing the flattened test-generation model for very large designs. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:681-690 [Conf]
  76. Don E. Ross, Tim Wood, Grady Giles
    Conversion of small functional test sets of nonscan blocks to scan patterns. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:691-700 [Conf]
  77. Anjali Kinra, Hari Balachandran, Regy Thomas, John Carulli
    Logic mapping on a microprocessor. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:701-710 [Conf]
  78. Julia A. Keahey
    Programming of flash with ICT rights and responsibilities. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:711-717 [Conf]
  79. Stephen F. Scheiber
    It isn't just testing anymore (REDUX). [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:718-723 [Conf]
  80. Kenneth P. Parker
    System issues in boundary-scan board test. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:724-728 [Conf]
  81. Zoran Stanojevic, Hari Balachandran, D. M. H. Walker, Fred Lakbani, Jayashree Saxena, Kenneth M. Butler
    Computer-aided fault to defect mapping (CAFDM) for defect diagnosis. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:729-738 [Conf]
  82. Nilmoni Deb, Ronald D. Blanton
    Analysis of failure sources in surface-micromachined MEMS. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:739-749 [Conf]
  83. Sujit T. Zachariah, Sreejit Chakravarty
    A scalable and efficient methodology to extract two node bridges from large industrial circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:750-759 [Conf]
  84. Charles E. Stroud, John M. Emmert, John R. Bailey, Khushru S. Chhor, Dragan Nikolic
    Bridging fault extraction from physical design data for manufacturing test development. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:760-769 [Conf]
  85. Yervant Zorian, Erik Jan Marinissen, Rohit Kapur
    On using IEEE P1500 SECT for test plug-n-play. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:770-777 [Conf]
  86. Sybille Hellebrand, Hans-Joachim Wunderlich, Huaguo Liang
    A mixed mode BIST scheme based on reseeding of folding counters. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:778-784 [Conf]
  87. Miron Abramovici, Charles E. Stroud
    DIST-based detection and diagnosis of multiple faults in FPGAs. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:785-794 [Conf]
  88. Xiaoling Sun, Jian Xu, Ben Chan, Pieter M. Trouborst
    Novel technique for built-in self-test of FPGA interconnects. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:795-803 [Conf]
  89. Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos
    Test response compaction by an accumulator behaving as a multiple input non-linear feedback shift register. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:804-811 [Conf]
  90. Rao Desineni, Kumar N. Dwarakanath, Ronald D. Blanton
    Universal test generation using fault tuples. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:812-819 [Conf]
  91. Thomas Bartenstein
    Fault distinguishing pattern generation. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:820-828 [Conf]
  92. Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
    : Reducing test application time in high-level test generation. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:829-838 [Conf]
  93. Qiang Peng, Miron Abramovici, Jacob Savir
    MUST: multiple-stem analysis for identifying sequentially untestable faults. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:839-846 [Conf]
  94. Neil G. Jacobson
    Streamlining programmable device and system test using IEEE Std 1532. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:847-853 [Conf]
  95. Michel Renovell, Yervant Zorian
    Different experiments in test generation for XILINX FPGAs. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:854-862 [Conf]
  96. Lee Whetsel
    Adapting scan architectures for low power operation. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:863-872 [Conf]
  97. Bahram Pouya, Alfred L. Crouch
    Optimization trade-offs for vector volume and test power. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:873-881 [Conf]
  98. Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu
    A comparison of classical scheduling approaches in power-constrained block-test scheduling. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:882-891 [Conf]
  99. Alfredo Benso, Silvia Chiusano, Stefano Di Carlo, Paolo Prinetto, Fabio Ricciato, Maurizio Spadari, Yervant Zorian
    HD/sup 2/BIST: a hierarchical framework for BIST scheduling, data patterns delivering and diagnosis in SoCs. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:892-901 [Conf]
  100. Mehrdad Nourani, Christos A. Papachristou
    An ILP formulation to optimize test access mechanism in system-on-chip testing. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:902-910 [Conf]
  101. Yervant Zorian, Erik Jan Marinissen, Maurice Lousberg, Sandeep Kumar Goel
    Wrapper design for embedded core test. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:911-920 [Conf]
  102. Peter C. Maxwell, Jeff Rearick
    Deception by design: fooling ourselves with gate-level models. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:921-929 [Conf]
  103. Jennifer Dworak, Michael R. Grimaila, Sooryong Lee, Li-C. Wang, M. Ray Mercer
    Enhanced DO-RE-ME based defect level prediction using defect site aggregation-MPG-D. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:930-939 [Conf]
  104. Pradip A. Thaker, Vishwani D. Agrawal, Mona E. Zaghloul
    Register-transfer level fault modeling and test evaluation techniques for VLSI circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:940-949 [Conf]
  105. Peter M. Higgins, Jim Lampos
    Microwave test mismatch and power de-embedding. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:950-954 [Conf]
  106. Takahiro J. Yamaguchi, Mani Soma, David Halter, Jim Nissen, Rajesh Raina, Masahiro Ishida, Toshifumi Watanabe
    Jitter measurements of a PowerPCTM microprocessor using an analytic signal method. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:955-964 [Conf]
  107. Doug Matthes, John Ford
    Technique for testing a very high speed mixed signal read channel design. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:965-970 [Conf]
  108. Ramesh Karri, Kaijie Wu
    Algorithm level re-computing with shifted operands-a register transfer level concurrent error detection technique. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:971-978 [Conf]
  109. Santiago Fernández-Gomez, Juan J. Rodríguez-Andina, Enrique Mandado
    Concurrent error detection in block ciphers [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:979-984 [Conf]
  110. Subhasish Mitra, Edward J. McCluskey
    Which concurrent error detection scheme to choose ? [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:985-994 [Conf]
  111. Ulrich Schoettmer, Chris Wagner, Tom Bleakley
    Device interfacing: the weakest link in the chain to break into the giga bit domain? [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:995-1004 [Conf]
  112. Ulf Pillkahn
    Structural test in a board self test environment. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:1005-1012 [Conf]
  113. Gerald H. Johnson
    Challenges of high supply currents during VLSI test. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:1013-1020 [Conf]
  114. Jiun-Lang Huang, Kwang-Ting Cheng
    Testing and characterization of the one-bit first-order delta-sigma modulator for on-chip analog signal analysis. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:1021-1030 [Conf]
  115. Mohamed Hafed, Nazmy Abaskharoun, Gordon W. Roberts
    A stand-alone integrated test core for time and frequency domain measurements. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:1031-1040 [Conf]
  116. Anna Maria Brosa, Joan Figueras
    Digital signature proposal for mixed-signal circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:1041-1050 [Conf]
  117. Ali Keshavarzi, Kaushik Roy, Charles F. Hawkins, Manoj Sachdev, K. Soumyanath, Vivek De
    Multiple-parameter CMOS IC testing with increased sensitivity for I_DDQ. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:1051-1059 [Conf]
  118. Seonki Kim, Sreejit Chakravarty, Bapiraju Vinnakota
    An analysis of the delay defect detection capability of the ECR test method. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:1060-1069 [Conf]
  119. James F. Plusquellic, Amy Germida, Jonathan Hudson, Ernesto Staroswiecki, Chintan Patel
    Predicting device performance from pass/fail transient signal analysis data. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:1070-1079 [Conf]
  120. Wei-Cheng Lai, Angela Krstic, Kwang-Ting Cheng
    Test program synthesis for path delay faults in microprocessor cores. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:1080-1089 [Conf]
  121. David B. Lavo
    A good excuse for reuse: "open" TAP controller design. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:1090-1099 [Conf]
  122. Teresa L. McLaurin, John C. Potter
    On-the-shelf core pattern methodology for ColdFire(R) microprocessor cores. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:1100-1107 [Conf]
  123. Peter C. Maxwell, Pete O'Neill, Robert C. Aitken, Ronald Dudley, Neal Jaarsma, Minh Quach, Don Wiseman
    Current ratios: a self-scaling technique for production IDDQ testing. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:1148-1156 [Conf]
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