Conferences in DBLP
Sung Soo Chung , Sanghyeon Baeg AC-JTAG: empowering JTAG beyond testing DC nets. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen K. Sunter , Ken Filliter , Joe Woo , Pat McHugh A general purpose 1149.4 IC with HF analog test capabilities. [Citation Graph (0, 0)][DBLP ] Conf ] Young Kim , Benny Lai , Kenneth P. Parker , Jeff Rearick Frequency detection-based boundary-scan testing of AC coupled nets. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Wohl , John A. Waicukauski , Thomas W. Williams Design of compactors for signature-analyzers in built-in self-test. [Citation Graph (0, 0)][DBLP ] Conf ] Jongshin Shin , Xiaoming Yu , Elizabeth M. Rudnick , Miron Abramovici At-speed logic BIST using a frozen clock testing strategy. [Citation Graph (0, 0)][DBLP ] Conf ] Nicola Nicolici , Bashir M. Al-Hashimi Tackling test trade-offs for BIST RTL data paths: BIST area overhead, test application time and power dissipation. [Citation Graph (0, 0)][DBLP ] Conf ] Sagar S. Sabade , D. M. H. Walker Improved wafer-level spatial analysis for I_DDQ limit setting. [Citation Graph (0, 0)][DBLP ] Conf ] W. Robert Daasch , Kevin Cota , James McNames , Robert Madge Neighbor selection for variance reduction in I_DDQ and other parametric data. [Citation Graph (0, 0)][DBLP ] Conf ] Bram Kruseman , Rudger van Veen , Kees van Kaam The future of delta I_DDQ testing. [Citation Graph (0, 0)][DBLP ] Conf ] Patrick R. Gallagher Jr. , Vivek Chickermane , Steven Gregor , Thomas S. Pierre A building block BIST methodology for SOC designs: a case study. [Citation Graph (0, 0)][DBLP ] Conf ] Bart Vermeulen , Steven Oostdijk , Frank Bouwman Test and debug strategy of the PNX8525 NexperiaTM digital video platform system chip. [Citation Graph (0, 0)][DBLP ] Conf ] Rohit Kapur , Maurice Lousberg , Tony Taylor , Brion L. Keller , Paul Reuter , Douglas Kay CTL the language for describing core-based test. [Citation Graph (0, 0)][DBLP ] Conf ] A. T. Sivaram Split timing mode (STM)-answer to dual frequency domain testing. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew Moran , Jim Teisher , Andrew Gill , Emir Pasalic , John Veneruso Automated translation of legacy code for ATE. [Citation Graph (0, 0)][DBLP ] Conf ] R. L. Stevenson , M. E. Jarosz , C. V. Verver Remote access to engineering test-a case study in providing engineering/diagnostic IC test services to Canadian universities. [Citation Graph (0, 0)][DBLP ] Conf ] Roderick McConnell , Rochit Rajsuman , Eric A. Nelson , Jeffrey Dreibelbis Test and repair of large embedded DRAMs. I. [Citation Graph (0, 0)][DBLP ] Conf ] Eric A. Nelson , Jeffrey Dreibelbis , Roderick McConnell Test and repair of large embedded DRAMs. 2. [Citation Graph (0, 0)][DBLP ] Conf ] Yoshihiro Nagura , Michael Mullins , Anthony Sauvageau , Yoshinoro Fujiwara , Katsuya Furue , Ryuji Ohmura , Tatsunori Komoike , Takenori Okitaka , Tetsushi Tanizaki , Katsumi Dosaka , Kazutami Arimoto , Yukiyoshi Koda , Tetsuo Tada Test cost reduction by at-speed BISR for embedded DRAMs. [Citation Graph (0, 0)][DBLP ] Conf ] Kee Sup Kim , Rathish Jayabharathi , Craig Carstens , Praveen Vishakantaiah , Derek Feltham , Adrian Carbine DPDAT: data path direct access testing. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy A method to enhance the fault coverage obtained by output response comparison of identical circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen K. Sunter , Charles McDonald , Givargis Danialy Contactless digital testing of IC pin leakage currents. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy On improving the stuck-at fault coverage of functional test sequences by using limited-scan operations. [Citation Graph (0, 0)][DBLP ] Conf ] Kaijie Wu , Ramesh Karri Algorithm level recomputing with allocation diversity: a register transfer level time redundancy based concurrent error detection technique. [Citation Graph (0, 0)][DBLP ] Conf ] Karl Thaller A highly-efficient transparent online memory test. [Citation Graph (0, 0)][DBLP ] Conf ] Shu-Yi Yu , Edward J. McCluskey On-line testing and recovery in TMR systems for real-time applications. [Citation Graph (0, 0)][DBLP ] Conf ] Silvia Chiusano , Giorgio Di Natale , Paolo Prinetto , Franco Bigongiari GRAAL: a tool for highly dependable SRAMs generation. [Citation Graph (0, 0)][DBLP ] Conf ] John T. Chen , Jitendra Khare , Ken Walker , Saghir A. Shaikh , Janusz Rajski , Wojciech Maly Test response compression and bitmap encoding for embedded memories in manufacturing process monitoring. [Citation Graph (0, 0)][DBLP ] Conf ] Ruifeng Guo , Srikanth Venkataraman A technique for fault diagnosis of defects in scan chains. [Citation Graph (0, 0)][DBLP ] Conf ] David B. Lavo , Tracy Larrabee Making cause-effect cost effective: low-resolution fault dictionaries. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas Bartenstein , Douglas Heaberlin , Leendert M. Huisman , David Sliwinski Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigm. [Citation Graph (0, 0)][DBLP ] Conf ] Bernd Laquai , Yi Cai Testing gigabit multilane SerDes interfaces with passive jitter injection filters. [Citation Graph (0, 0)][DBLP ] Conf ] Amir Attarha , Mehrdad Nourani Testing interconnects for noise and skew in gigahertz SoCs. [Citation Graph (0, 0)][DBLP ] Conf ] Ming-Jun Hsiao , Jing-Reng Huang , Shao-Shen Yang , Tsin-Yuan Chang A built-in timing parametric measurement unit. [Citation Graph (0, 0)][DBLP ] Conf ] Takahiro J. Yamaguchi , Mani Soma , Jim Nissen , David Halter , Rajesh Raina , Masahiro Ishida Testing clock distribution circuits using an analytic signal method. [Citation Graph (0, 0)][DBLP ] Conf ] Aranggan Venkataratnam , Kimberly E. Newman Rapid prototyping of time-based PDIT for substrate networks [MCM] . [Citation Graph (0, 0)][DBLP ] Conf ] Thomas S. Barnett , Adit D. Singh , Victor P. Nelson Estimating burn-in fall-out for redundant memory. [Citation Graph (0, 0)][DBLP ] Conf ] Mohammad Athar Khalil , Chin-Long Wey Extreme-voltage stress vector generation of analog CMOS ICs for gate-oxide reliability enhancement. [Citation Graph (0, 0)][DBLP ] Conf ] Chao-Wen Tseng , Edward J. McCluskey Multiple-output propagation transition fault test. [Citation Graph (0, 0)][DBLP ] Conf ] Suriyaprakash Natarajan , Sandeep K. Gupta , Melvin A. Breuer Switch-level delay test of domino logic circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Fernando M. Gonçalves , Marcelino B. Santos , Isabel C. Teixeira , João Paulo Teixeira Implicit functionality and multiple branch coverage (IFMB): a testability metric for RT-level. [Citation Graph (0, 0)][DBLP ] Conf ] Erik Peterson , Wanli Jiang Practical application of energy consumption ratio test. [Citation Graph (0, 0)][DBLP ] Conf ] Abhishek Singh , Chintan Patel , Shirong Liao , James F. Plusquellic , Anne E. Gattiker Detecting delay faults using power supply transient signal analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Hoki Kim , D. M. H. Walker , David Colby A practical built-in current sensor for I_DDQ testing. [Citation Graph (0, 0)][DBLP ] Conf ] Klaus Helmreich Test path simulation and characterisation. [Citation Graph (0, 0)][DBLP ] Conf ] Sunil K. Jain , Greg P. Chema Testing beyond EPA: TDF methodology solutions matrix. [Citation Graph (0, 0)][DBLP ] Conf ] G. Dajee , N. Goldblatt , T. Lundquist , S. Kasapi , Keneth R. Wilsher Practical, non-invasive optical probing for flip-chip devices. [Citation Graph (0, 0)][DBLP ] Conf ] Ken Tumin , Carmen Vargas , Ross Patterson , Chris Nappi Scan vs. functional testing - a comparative effectiveness study on Motorola's MMC2107TM . [Citation Graph (0, 0)][DBLP ] Conf ] Don Douglas Josephson , Steve Poehhnan , Vincent Govan Debug methodology for the McKinley processor. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Kessler , Gundolf Kiefer , Jens Leenstra , Knut Schünemann , Thomas Schwarz , Hans-Joachim Wunderlich Using a hierarchical DfT methodology in high frequency processor designs for improved delay fault testability. [Citation Graph (0, 0)][DBLP ] Conf ] F. G. M. de Jong , Alex S. Biewenga , D. C. L. van Geest , T. F. Waayers Testing and programming flash memories on assemblies during high volume production. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen Harrison , Peter Collins , Greg Noeninckx , Peter Horwood Hierarchical boundary-scan: a Scan Chip-Set solution. [Citation Graph (0, 0)][DBLP ] Conf ] Alan Albee A practical guide to combining ICT & boundary scan testing. [Citation Graph (0, 0)][DBLP ] Conf ] Solomon Max Ramp testing of ADC transition levels using finite resolution ramps. [Citation Graph (0, 0)][DBLP ] Conf ] Udaya Natarajan Test challenges for SONET/SDH physical layer OC3 devices and beyond. [Citation Graph (0, 0)][DBLP ] Conf ] Mamoru Tamba , Atsushi Shimizu , Hideharu Munakata , Takanori Komuro A method to improve SFDR with random interleaved sampling method. [Citation Graph (0, 0)][DBLP ] Conf ] Ozgur Sinanoglu , Alex Orailoglu Space and time compaction schemes for embedded cores. [Citation Graph (0, 0)][DBLP ] Conf ] Rainer Dorsch , Hans-Joachim Wunderlich Tailoring ATPG for embedded testing. [Citation Graph (0, 0)][DBLP ] Conf ] Frank F. Hsu , Kenneth M. Butler , Janak H. Patel A case study on the implementation of the Illinois Scan Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Liang-Chi Chen , T. M. Mak , Sandeep K. Gupta , Melvin A. Breuer Crosstalk test generation on pseudo industrial circuits: a case study. [Citation Graph (0, 0)][DBLP ] Conf ] Angela Krstic , Jing-Jia Liou , Yi-Min Jiang , Kwang-Ting Cheng Delay testing considering crosstalk-induced effects. [Citation Graph (0, 0)][DBLP ] Conf ] Keith J. Keller , Hiroshi Takahashi , Kewal K. Saluja , Yuzo Takamatsu On reducing the target fault list of crosstalk-induced delay faults in synchronous sequential circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Don Douglas Josephson , Steve Poehlman , Vincent Govan , Clint Mumford Test methodology for the McKinley processor. [Citation Graph (0, 0)][DBLP ] Conf ] Mary P. Kusko , Bryan J. Robbins , Timothy J. Koprowski , William V. Huott 99% AC test coverage using only LBIST on the 1 GHz IBM S/390 zSeries 900 Microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Gilbert Vandling Modeling and testing the Gekko microprocessor, an IBM PowerPC derivative for Nintendo. [Citation Graph (0, 0)][DBLP ] Conf ] Andrea Baldini , Alfredo Benso , Paolo Prinetto , Sergio Mo , Andrea Taddei Towards a unified test process: from UML to end-of-line functional test. [Citation Graph (0, 0)][DBLP ] Conf ] Robert Tappe , Dietmar Ehrhardt Dynamic tests in complex systems [automotive electronics]. [Citation Graph (0, 0)][DBLP ] Conf ] William Eklow , Richard M. Sedmak , Dan Singletary , Toai Vo Unsafe board states during PC-based boundary-scan testing. [Citation Graph (0, 0)][DBLP ] Conf ] Jeff Rearick Too much delay fault coverage is a bad thing. [Citation Graph (0, 0)][DBLP ] Conf ] Manish Sharma , Janak H. Patel Testing of critical paths for delay faults. [Citation Graph (0, 0)][DBLP ] Conf ] Saravanan Padmanaban , Maria K. Michael , Spyros Tragoudas Exact path delay grading with fundamental BDD operations. [Citation Graph (0, 0)][DBLP ] Conf ] Lei Xu , Yihe Sun , Hongyi Chen Scan array solution for testing power and testing time. [Citation Graph (0, 0)][DBLP ] Conf ] Tsung-Chu Huang , Kuen-Jong Lee A token scan architecture for low power testing. [Citation Graph (0, 0)][DBLP ] Conf ] Jayashree Saxena , Kenneth M. Butler , Lee Whetsel An analysis of power reduction techniques in scan testing. [Citation Graph (0, 0)][DBLP ] Conf ] Nandini Sridhar , Michael S. Hsiao On efficient error diagnosis of digital circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Venkatram Krishnaswamy , A. B. Ma , Praveen Vishakantaiah A study of bridging defect probabilities on a Pentium (TM) 4 CPU. [Citation Graph (0, 0)][DBLP ] Conf ] Zoran Stanojevic , D. M. H. Walker FedEx - a fast bridging fault extractor. [Citation Graph (0, 0)][DBLP ] Conf ] Chintan Patel , Fidel Muradali , James F. Plusquellic Power supply transient signal integration circuit. [Citation Graph (0, 0)][DBLP ] Conf ] Jamie Cullen Scan test sequencing hardware for structural test. [Citation Graph (0, 0)][DBLP ] Conf ] Rohit Kapur , Thomas W. Williams Tester retargetable patterns. [Citation Graph (0, 0)][DBLP ] Conf ] Yu Huang , Chien-Chung Tsai , Neelanjan Mukherjee , Omer Samman , Dan Devries , Wu-Tung Cheng , Sudhakar M. Reddy On RTL scan design. [Citation Graph (0, 0)][DBLP ] Conf ] Harald P. E. Vranken , Tom Waayers , Hérvé Fleury , David Lelouvier Enhanced reduced pin-count test for full-scan design. [Citation Graph (0, 0)][DBLP ] Conf ] Carl Barnhart , Vanessa Brunkhorst , Frank Distler , Owen Farnsworth , Brion L. Keller , Bernd Könemann , Andrej Ferko OPMISR: the foundation for compressed ATPG vectors. [Citation Graph (0, 0)][DBLP ] Conf ] Jin-Fu Li , Kuo-Liang Cheng , Chih-Tsun Huang , Cheng-Wen Wu March-based RAM diagnosis algorithms for stuck-at and coupling faults. [Citation Graph (0, 0)][DBLP ] Conf ] Jörg E. Vollrath , Randall Rooney Pseudo fail bit map generation for RAMs during component test and burn-in in a manufacturing environment. [Citation Graph (0, 0)][DBLP ] Conf ] Herold Pilo , R. Dean Adams , Robert E. Busch , Eric A. Nelson , Geoerge E. Rudgers Bitline contacts in high density SRAMs: design for testability and stressability. [Citation Graph (0, 0)][DBLP ] Conf ] Zaid Al-Ars , A. J. van de Goor , Jens Braun , Detlev Richter Simulation based analysis of temperature effect on the faulty behavior of embedded DRAMs. [Citation Graph (0, 0)][DBLP ] Conf ] Gilly Nativ , Steven Mittermaier , Shmuel Ur , Avi Ziv Cost evaluation of coverage directed test generation for the IBM mainframe. [Citation Graph (0, 0)][DBLP ] Conf ] Zeljko Zilic , Katarzyna Radecka : Identifying redundant gate replacements in verification by error modeling. [Citation Graph (0, 0)][DBLP ] Conf ] Qiushuang Zhang , Ian G. Harris A validation fault model for timing-induced functional errors. [Citation Graph (0, 0)][DBLP ] Conf ] Alessandro Fin , Franco Fummi , Graziano Pravadelli AMLETO: a multi-language environment for functional test generation. [Citation Graph (0, 0)][DBLP ] Conf ] Seongwon Kim , Mani Soma Test evaluation and data on defect-oriented BIST architecture for high-speed PLL. [Citation Graph (0, 0)][DBLP ] Conf ] Sasikumar Cherubal , Abhijit Chatterjee A high-resolution jitter measurement technique using ADC sampling. [Citation Graph (0, 0)][DBLP ] Conf ] Masashi Shimanouchi An approach to consistent jitter modeling for various jitter aspects and measurement methods. [Citation Graph (0, 0)][DBLP ] Conf ] Antonio H. Chan , Gordon W. Roberts A synthesizable, fast and high-resolution timing measurement device using a component-invariant vernier delay line. [Citation Graph (0, 0)][DBLP ] Conf ] Seongrnoon Wang Low hardware overhead scan based 3-weight weighted random BIST. [Citation Graph (0, 0)][DBLP ] Conf ] Hong-Sik Kim , Jin-kyue Lee , Sungho Kang A new multiple weight set calculation algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] C. V. Krishna , Abhijit Jas , Nur A. Touba Test vector encoding using partial LFSR reseeding. [Citation Graph (0, 0)][DBLP ] Conf ] Huaguo Liang , Sybille Hellebrand , Hans-Joachim Wunderlich Two-dimensional test data compression for scan-based deterministic BIST. [Citation Graph (0, 0)][DBLP ] Conf ] Mark Malinoski , Burnell G. West Rapid-response temperature control provides new defect screening opportunities. [Citation Graph (0, 0)][DBLP ] Conf ] Scott Benner , Oluseyi Boroffice Optimal production test times through adaptive test programming. [Citation Graph (0, 0)][DBLP ] Conf ] Ajay Khoche , Rohit Kapur , David Armstrong , Thomas W. Williams , Mick Tegethoff , Jochen Rivoir A new methodology for improved tester utilization. [Citation Graph (0, 0)][DBLP ] Conf ] Michel Renovell , Penelope Faure , Jean Michel Portal , Joan Figueras , Yervant Zorian IS-FPGA : a new symmetric FPGA architecture with implicit scan. [Citation Graph (0, 0)][DBLP ] Conf ] Ian G. Harris , Premachandran R. Menon , Russell Tessier BIST-based delay path testing in FPGA architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Cecilia Metra , Andrea Pagano , Bruno Riccò On-line testing of transient and crosstalk faults affecting interconnections of FPGA-implemented systems. [Citation Graph (0, 0)][DBLP ] Conf ] John Ferrario , Randy Wolf , Hanyi Ding Moving from mixed signal to RF test hardware development. [Citation Graph (0, 0)][DBLP ] Conf ] Hui S. Nam , Bernard Cuddy , Dieter Luecking A phase noise spectrum test solution for high volume mixed signal/wireless automatic test equipments. [Citation Graph (0, 0)][DBLP ] Conf ] Christian Olgaard , Sule Ozev , Alex Orailoglu Testability implications in low-cost integrated radio transceivers: a Bluetooth case study. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Jakobsen , Jeffrey Dreibelbis , Gary Pomichter , Darren Anand , John E. Barth Jr. , Michael R. Nelms , Jeffrey Leach , George M. Belansek Embedded DRAM built in self test and methodology for test insertion. [Citation Graph (0, 0)][DBLP ] Conf ] Yuejian Wu , Liviu Calin Shadow write and read for at-speed BIST of TDM SRAMs. [Citation Graph (0, 0)][DBLP ] Conf ] Volker Schöber , Steffen Paul , Olivier Picot Memory built-in self-repair using redundant words. [Citation Graph (0, 0)][DBLP ] Conf ] Xinli Gu , Sung Soo Chung , Frank Tsang , Jan Arild Tofte , Hamid Rahmanian An effort-minimized logic BIST implementation method. [Citation Graph (0, 0)][DBLP ] Conf ] Snezana Dikic , Lars-Johan Fritz , Dario Dell'Aquia BIST and fault insertion re-use in telecom systems. [Citation Graph (0, 0)][DBLP ] Conf ] John Braden , Qing Lin , Brian Smith Use of BIST in Sun FireTM servers. [Citation Graph (0, 0)][DBLP ] Conf ] Vikram Iyengar , Krishnendu Chakrabarty , Erik Jan Marinissen Test wrapper and test access mechanism co-optimization for system-on-chip. [Citation Graph (0, 0)][DBLP ] Conf ] Chauchin Su , Wenliang Tseng Configuration free SoC interconnect BIST methodology. [Citation Graph (0, 0)][DBLP ] Conf ] Michel Renovell , Jean Marc Galliere , Florence Azaïs , Serge Bernard , Yves Bertrand Boolean and current detection of MOS transistor with gate oxide short. [Citation Graph (0, 0)][DBLP ] Conf ] Chao-Wen Tseng , Chien-Mo James Li , Mike Purtell , Edward J. McCluskey Testing for resistive opens and stuck opens. [Citation Graph (0, 0)][DBLP ] Conf ] Yasuo Sato , Msaki Kohno , Toshio Ikeda , Iwao Yamazaki , Masato Hamamoto An evaluation of defect-oriented test: WELL-controlled low voltage test. [Citation Graph (0, 0)][DBLP ] Conf ] Srivaths Ravi , Niraj K. Jha Fast test generation for circuits with RTL and gate-level views. [Citation Graph (0, 0)][DBLP ] Conf ] Yong Chang Kim , Vishwani D. Agrawal , Kewal K. Saluja Combinational test generation for various classes of acyclic sequential circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Xijiang Lin , Janusz Rajski , Irith Pomeranz , Sudhakar M. Reddy On static test compaction and test pattern ordering for scan designs. [Citation Graph (0, 0)][DBLP ] Conf ] Erik H. Volkerink , Ajay Khoche , Linda A. Kamas , Jochen Rivoir , Hans G. Kerkhoff Tackling test trade-offs from design, manufacturing to market using economic modeling. [Citation Graph (0, 0)][DBLP ] Conf ] Thiagarajan Trichy , Peter Sandborn , Ravi Raghavan , Shubhada Sahasrabudhe A new test/diagnosis/rework model for use in technical cost modeling of electronic systems assembly. [Citation Graph (0, 0)][DBLP ] Conf ] Russell B. Miller , Walter C. Riordan Unit level predicted yield: a method of identifying high defect density die at wafer sort. [Citation Graph (0, 0)][DBLP ] Conf ] Atsushi Oshima , John Poniatowski , Toshihiro Nomura Pin electronics IC for high speed differential devices. [Citation Graph (0, 0)][DBLP ] Conf ] John Cheng When zero picoseconds edge placement accuracy is not enough. [Citation Graph (0, 0)][DBLP ] Conf ] David C. Keezer , Q. Zhou , C. Bair , J. Kuan , B. Poole Terabit-per-second automated digital testing. [Citation Graph (0, 0)][DBLP ] Conf ] Mohamed Hafed , Nazmy Abaskharoun , Gordon W. Roberts A stand-alone integrated test core for time and frequency domain measurements. [Citation Graph (0, 0)][DBLP ] Conf ] 