Conferences in DBLP
David W. Yen Seeing Chip Testability Through a Systems Person's Eyes. [Citation Graph (0, 0)][DBLP ] Conf ] Janusz Rajski Test Challenges of Nanometer Technology. [Citation Graph (0, 0)][DBLP ] Conf ] Jean Michel Portal , H. Aziza , Didier Née EEPROM Memory: Threshold Voltage Built In Self Diagnosis. [Citation Graph (0, 0)][DBLP ] Conf ] Chih-Wea Wang , Kuo-Liang Cheng , Jih-Nung Lee , Yung-Fa Chou , Chih-Tsun Huang , Cheng-Wen Wu , Frank Huang , Hong-Tzer Yang Fault Pattern Oriented Defect Diagnosis for Memories. [Citation Graph (0, 0)][DBLP ] Conf ] Derek Wright , Manoj Sachdev Transistor-Level Fault Analysis and Test Algorithm Development for Ternary Dynamic Content Addressable Memorie. [Citation Graph (0, 0)][DBLP ] Conf ] Masashi Shimanouchi Periodic Jitter Injection with Direct Time Synthesis by SPPTM ATE for SerDes Jitter Tolerance Test in Production. [Citation Graph (0, 0)][DBLP ] Conf ] Takahiro J. Yamaguchi , Mani Soma , Masahiro Ishida , Makoto Kurosawa , Hirobumi Musha Effects of Deterministic Jitter in a Cable on Jitter Tolerance Measurements. [Citation Graph (0, 0)][DBLP ] Conf ] Henry C. Lin , Karen Taylor , Alan Chong , Eddie Chan , Mani Soma , Hosam Haggag , Jeff Huard , Jim Braatz CMOS Built-In Test Architecture for High-Speed Jitter Measurement. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas S. Barnett , Adit D. Singh Relating Yield Models to Burn-In Fall-Out in Time. [Citation Graph (0, 0)][DBLP ] Conf ] Yoshihito Nishizaki , Osamu Nakayama , Chiaki Matsumoto , Yoshitaka Kimura , Toshimi Kobayashi , Hiroyuki Nakamura Testing DSM ASIC With Static, \DeltaIDDQ, And Dynamic Test Suite: Implementation And Results. [Citation Graph (0, 0)][DBLP ] Conf ] Oleg Semenov , Arman Vassighi , Manoj Sachdev , Ali Keshavarzi , Charles F. Hawkins Burn-in Temperature Projections for Deep Sub-micron Technologies. [Citation Graph (0, 0)][DBLP ] Conf ] Haihua Yan , Adit D. Singh Experiments in Detecting Delay Faults using Multiple Higher Frequency Clocks and Results from Neighboring Die. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaoliang Bai , Sujit Dey , Angela Krstic HyAC: A Hybrid Structural SAT Based ATPG for Crosstalk. [Citation Graph (0, 0)][DBLP ] Conf ] Rahul Kundu , R. D. (Shawn) Blanton Path Delay Test Generation for Domino Logic Circuits in the Presence of Crosstalk. [Citation Graph (0, 0)][DBLP ] Conf ] S. R. Seward , Parag K. Lala Fault Injection for Verifying Testability at the VHDL Level. [Citation Graph (0, 0)][DBLP ] Conf ] Miroslav N. Velev Collection of High-Level Microprocessor Bugs from Formal Verification of Pipelined and Superscalar Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Amir Hekmatpour , James Coulter Coverage-Directed Management and Optimization of Random Functional Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Eric Starkloff , Tim Fountain , Garth Black The PXI Modular Instrumentation Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] J. S. Davis , David C. Keezer , O. Liboiron-Ladouceur , K. Bergman Application and Demonstration of a Digital Test Core: Optoelectronic Test Bed and Wafer-level Prober. [Citation Graph (0, 0)][DBLP ] Conf ] Ahmed Rashid Syed RIC/DICMOS-- Multi-channel CMOS Formatter. [Citation Graph (0, 0)][DBLP ] Conf ] Maurizio Gavardoni Data flow within an open architecture tester. [Citation Graph (0, 0)][DBLP ] Conf ] David C. Keezer , Dany Minier , Marie-Christine Caron A Production-Oriented Multiplexing System for Testing above 2.5 Gbps. [Citation Graph (0, 0)][DBLP ] Conf ] Serge Bernard , Mariane Comte , Florence Azaïs , Yves Bertrand , Michel Renovell A New Methodology For ADC Test Flow Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Gwenolé Maugard , Carsten Wegener , Tom O'Dwyer , Michael Peter Kennedy Method of reducing contactor effect when testing high-precision ADCs. [Citation Graph (0, 0)][DBLP ] Conf ] Le Jin , Kumar Parthasarathy , Turker Kuyel , Degang Chen , Randall L. Geiger Linearity Testing of Precision Analog-to-Digital Converters Using Stationary Nonlinear Inputs. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen K. Sunter Testing High Frequency ADCs and DACs with a Low Frequency Analog Bus. [Citation Graph (0, 0)][DBLP ] Conf ] Franco Stellari , Peilin Song , Moyra K. McManus , Robert Gauthier , Alan J. Weger , Kiran V. Chatty , Mujahid Muhammad , Pia Sanda Optical and Electrical Testing of Latchup in I/O Interface Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Keneth R. Wilsher Designed -in-diagnostics: A new optical method. [Citation Graph (0, 0)][DBLP ] Conf ] Romain Desplats , Felix Beaudoin , Philippe Perdu , Nagamani Nataraj , Ted Lundquist , Ketan Shah Fault Localization using Time Resolved Photon Emission and STIL Waveforms. [Citation Graph (0, 0)][DBLP ] Conf ] Jeremy A. Rowlette , Travis M. Eiles Critical Timing Analysis in Microprocessors Using Near-IR Laser Assisted Device Alteration (LADA). [Citation Graph (0, 0)][DBLP ] Conf ] Vishwani D. Agrawal , A. V. S. S. Prasad , Madhusudan V. Atre Fault Collapsing via Functional Dominance. [Citation Graph (0, 0)][DBLP ] Conf ] Qingwei Wu , Michael S. Hsiao Efficient Sequential ATPG Based on Partitioned Finite-State-Machine Traversal. [Citation Graph (0, 0)][DBLP ] Conf ] Liang Zhang , Indradeep Ghosh , Michael S. Hsiao Efficient Sequential ATPG for Functional RTL Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Mahesh A. Iyer Race: A Word-Level ATPG-Based Constraints Solver System For Smart Random Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas J. Vogels , Wojciech Maly , R. D. (Shawn) Blanton Progressive Bridge Identification. [Citation Graph (0, 0)][DBLP ] Conf ] Yu Huang , Wu-Tung Cheng , Sudhakar M. Reddy , Cheng-Ju Hsieh , Yu-Ting Hung Statistical Diagnosis for Intermittent Scan Chain Hold-Time Fault. [Citation Graph (0, 0)][DBLP ] Conf ] Zhiyuan Wang , Kun-Han Tsai , Malgorzata Marek-Sadowska , Janusz Rajski An Efficient and Effective Methodology on the Multiple Fault Diagnosis. [Citation Graph (0, 0)][DBLP ] Conf ] Angela Krstic , Li-C. Wang , Kwang-Ting Cheng , T. M. Mak Diagnosis-Based Post-Silicon Timing Validation Using Statistical Tools and Methodologies. [Citation Graph (0, 0)][DBLP ] Conf ] YongJoon Kim , DongSub Song , YongSeung Shin , Sunghoon Chun , Sungho Kang A New Maximal Diagnosis Algorithm for Bus-structured Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Kevin Melocco , Hina Arora , Paul Setlak , Gary Kunselman , Shazia Mardhani A Comprehensive Approach to Assessing and Analyzing 1149.1 Test Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Kendrick Baker Constructive Pattern Generation Heuristic for Meeting SSO Limits. [Citation Graph (0, 0)][DBLP ] Conf ] Henk D. L. Hollmann , Erik Jan Marinissen , Bart Vermeulen Optimal Interconnect ATPG Under a Ground-Bounce Constraint. [Citation Graph (0, 0)][DBLP ] Conf ] Davide Appello , Paolo Bernardi , Alessandra Fudoli , Maurizio Rebaudengo , Matteo Sonza Reorda , Vincenzo Tancorre , Massimo Violante Exploiting Programmable BIST For The Diagnosis of Embedded Memory Cores. [Citation Graph (0, 0)][DBLP ] Conf ] Theo J. Powell , Wu-Tung Cheng , Joseph Rayhawk , Omer Samman , Paul Policke , Sherry Lai BIST for Deep Submicron ASIC Memories with High Performance Application. [Citation Graph (0, 0)][DBLP ] Conf ] Jin-Fu Li , Jen-Chieh Yeh , Rei-Fu Huang , Cheng-Wen Wu , Peir-Yuan Tsai , Archer Hsu , Eugene Chow A Built-In Self-Repair Scheme for Semiconductor Memories with 2-D Redundancy. [Citation Graph (0, 0)][DBLP ] Conf ] Kranthi K. Pinjala , Bruce C. Kim , Pramodchandran N. Variyam Automatic Diagnostic Program Generation for Mixed Signal Load Board. [Citation Graph (0, 0)][DBLP ] Conf ] Nobuhiro Sato , Yoshihiro Hashimoto A High Precision IDDQ Measurement System With Improved Dynamic Load Regulation. [Citation Graph (0, 0)][DBLP ] Conf ] Tomokazu Yoneda , Tetsuo Uchiyama , Hideo Fujiwara Area and Time Co-Optimization for System-on-a-Chip based on Consecutive Testability. [Citation Graph (0, 0)][DBLP ] Conf ] Yu-Shen Yang , Jiang Brandon Liu , Paul J. Thadikaran , Andreas G. Veneris Extraction Error Diagnosis and Correction in High-Performance Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Nektarios Kranitis , George Xenoulis , Antonis M. Paschalis , Dimitris Gizopoulos , Yervant Zorian Application and Analysis of RT-Level Software-Based Self-Testing for Embedded Processor Cores. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz Reducing Test Data Volume Using Random-Testable and Periodic-Testable Scan Chains in Circuits with Multiple Scan Chains. [Citation Graph (0, 0)][DBLP ] Conf ] Armin Würtenberger , Christofer S. Tautermann , Sybille Hellebrand A Hybrid Coding Strategy For Optimized Test Data Compression. [Citation Graph (0, 0)][DBLP ] Conf ] Lei Li , Krishnendu Chakrabarty Deterministic BIST Based on a Reconfigurable Interconnection Network. [Citation Graph (0, 0)][DBLP ] Conf ] Bhargab B. Bhattacharya , Sharad C. Seth , Sheng Zhang Double-Tree Scan: A Novel Low-Power Scan-Path Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Takaki Yoshida , Masafumi Watati A New Approach for Low Power Scan Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Yannick Bonhomme , Patrick Girard , Loïs Guiller , Christian Landrault , Serge Pravossoudovitch Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint. [Citation Graph (0, 0)][DBLP ] Conf ] Bill Eklow , Carl Barnhart , Mike Ricchetti , Terry Borroz IEEE 1149.6 - A Practical Perspective. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth E. Posse , Geir Eide Key Impediments to DFT-Focused Test and How to Overcome Them. [Citation Graph (0, 0)][DBLP ] Conf ] George Bao Challenges in Low Cost Test Approach for ARM9TM Core Based Mixed-Signal SoC DragonBallTM-MX1. [Citation Graph (0, 0)][DBLP ] Conf ] Michael A. Jones Ultra Low Cost Linear Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Jie Sun , Mike Li A Generic Test Path and DUT Model for DataCom ATE. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas P. Warwick Mitigating the Effects of The DUT Interface board and Test System Parasitics in Gigabit-Plus Measurements. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaoyun Sun , Larry L. Kinney , Bapiraju Vinnakota Test Vector Generation Based on Correlation Model for Ratio-Iddq. [Citation Graph (0, 0)][DBLP ] Conf ] Yukio Okuda , Nobuyuki Furukawa Hysteresis of Intrinsic IDDQ Currents. [Citation Graph (0, 0)][DBLP ] Conf ] Chris Schuermyer , Brady Benware , Kevin Cota , Robert Madge , W. Robert Daasch , L. Ning Screening VDSM Outliers using Nominal and Subthreshold Supply Voltage IDDQ. [Citation Graph (0, 0)][DBLP ] Conf ] Seongmoon Wang , Srimat T. Chakradhar A Scalable Scan-Path Test Point Insertion Technique to Enhance Delay Fault Coverage for Standard Scan Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Puneet Gupta , Michael S. Hsiao High Quality ATPG for Delay Defects. [Citation Graph (0, 0)][DBLP ] Conf ] Wangqi Qiu , D. M. H. Walker An Efficient Algorithm for Finding the K Longest Testable Paths Through Each Gate in a Combinational Circuit. [Citation Graph (0, 0)][DBLP ] Conf ] Ozgur Sinanoglu , Alex Orailoglu Modeling Scan Chain Modifications For Scan-in Test Power Minimization. [Citation Graph (0, 0)][DBLP ] Conf ] Érika F. Cota , Luigi Carro , Flávio Rech Wagner , Marcelo Lubaszewski Power-aware NoC Reuse on the Testing of Core-based Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Qiang Xu , Nicola Nicolici On Reducing Wrapper Boundary Register Cells in Modular SOC Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Suzette Vandivier , Mark Wahl , Jeff Rearick First IC Validation of IEEE Std. 1149.6. [Citation Graph (0, 0)][DBLP ] Conf ] Ivan Duzevik Design and Implementation of IEEE 1149.6. [Citation Graph (0, 0)][DBLP ] Conf ] Lee Whetsel Adapting JTAG for AC Interconnect Testing. [Citation Graph (0, 0)][DBLP ] Conf ] José Pineda de Gyvez , Guido Gronthoud , Rashid Amine VDD Ramp Testing for RF Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Iboun Taimiya Sylla Building An RF Source For Low Cost Testers Using An ADPLL Controlled By Texas Instruments Digital Signal Processor (DSP) TMS320C5402. [Citation Graph (0, 0)][DBLP ] Conf ] Achintya Halder , Soumendu Bhattacharya , Abhijit Chatterjee Automatic Multitone Alternate Test Generation For RF Circuits Using Behavioral Models. [Citation Graph (0, 0)][DBLP ] Conf ] Jeremy A. Walraven Introduction to Applications and Industries for Microelectromechanical Systems (MEMS). [Citation Graph (0, 0)][DBLP ] Conf ] Tamal Mukherjee MEMS Design And Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Gary K. Fedder MEMS Fabrication. [Citation Graph (0, 0)][DBLP ] Conf ] Wanli Jiang , Erik Peterson , Bob Robotka Effectiveness Improvement of ECR Tests. [Citation Graph (0, 0)][DBLP ] Conf ] Dhruva Acharyya , Jim Plusquellic Impedance Profile of a Commercial Power Grid and Test System. [Citation Graph (0, 0)][DBLP ] Conf ] B. Alorda , B. Bloechel , Ali Keshavarzi , Jaume Segura CHARDIN: An Off-Chip Transient Current Monitor with Digital Interface for Production Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Wohl , John A. Waicukauski , Sanjay Patel , Minesh B. Amin X-Tolerant Compression And Application of Scan-ATPG Patterns In A BIST Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Ramesh C. Tekumalla On Reducing Aliasing Effects and Improving Diagnosis of Logic BIST Failures. [Citation Graph (0, 0)][DBLP ] Conf ] Janusz Rajski , Jerzy Tyszer , Chen Wang , Sudhakar M. Reddy Convolutional Compaction of Test Responses. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Dahlgren , Paul Dickinson , Ishwar Parulkar Latch Divergency In Microprocessor Failure Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Scott Erlanger , Dilip K. Bhavsar , Richard Davies Testability Features of the Alpha 21364 Microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Teresa L. McLaurin , Frank Frederick , Rich Slobodnik The Testability Features of The ARM1026EJ Microprocessor Core. [Citation Graph (0, 0)][DBLP ] Conf ] Jay J. Nejedlo TRIBuTETM Board and Platform Test Methodology: Intel's Next-Generation Test and Validation Methodology for Platforms. [Citation Graph (0, 0)][DBLP ] Conf ] Jay J. Nejedlo IBISTTM (Interconnect Built-in Self-Test) Architecture and Methodology for PCI Express: Intel?s Next-Generation Test and Validation Methodology for Performance IO. [Citation Graph (0, 0)][DBLP ] Conf ] Leon van de Logt , Frank van der Heyden , Tom Waayers An extension to JTAG for at-speed debug on a system. [Citation Graph (0, 0)][DBLP ] Conf ] A. T. Sivaram , Daniel Fan , Jon Pryce XML And Java For Open ATE Programming Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Alfredo Benso , Stefano Di Carlo , Giorgio Di Natale , Paolo Prinetto , Luca Tagliaferri Data Critically Estimation In Software Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Fan , Steve Roehling , Rusty Carruth Case Study - Using STIL as Test Pattern Language. [Citation Graph (0, 0)][DBLP ] Conf ] Paul Buxton , Paul Tabor Outlier Detection for DPPM Reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Jeremy A. Walraven Failure Mechanisms in MEMS. [Citation Graph (0, 0)][DBLP ] Conf ] Jeremy A. Walraven Tools and Techniques for Failure Analysis and Qualification of MEMS. [Citation Graph (0, 0)][DBLP ] Conf ] Theresa Maudie , Alex Hardt , Rick Nielsen , Dennis Stanerson , Ron Bieschke , Mike Miller MEMS Manufacturing Testing: An Accelerometer Case Study. [Citation Graph (0, 0)][DBLP ] Conf ] Jeremy A. Walraven Future Challenges for MEMS Failure Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Wojciech Maly , Anne E. Gattiker , Thomas Zanon , Thomas J. Vogels , R. D. (Shawn) Blanton , Thomas M. Storey Deformations of IC Structure in Test and Yield Learning. [Citation Graph (0, 0)][DBLP ] Conf ] Bram Kruseman , Stefan van den Oetelaar Detection of Resistive Shorts in Deep Sub-micron Technologies. [Citation Graph (0, 0)][DBLP ] Conf ] R. D. (Shawn) Blanton , Kumar N. Dwarakanath , Anirudh B. Shah Analyzing the Effectiveness of Multiple-Detect Test Sets. [Citation Graph (0, 0)][DBLP ] Conf ] Martin Omaña , Daniele Rossi , Cecilia Metra Novel Transient Fault Hardened Static Latch. [Citation Graph (0, 0)][DBLP ] Conf ] Kartik Mohanram , Nur A. Touba Cost-Effective Approach for Reducing Soft Error Failure Rate in Logic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Kaijie Wu , Ramesh Karri Register Transfer Level Approach to Hybrid Time and Hardware Redundancy Based Fault Secure Datapath Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] B. Kiran Kumar , Parag K. Lala On-line Detection of Faults in Carry-Select Adders. [Citation Graph (0, 0)][DBLP ] Conf ] Ramesh Karri , Grigori Kuznetsov , Michael Gössel Parity-Based Concurrent Error Detection in Symmetric Block Ciphers. [Citation Graph (0, 0)][DBLP ] Conf ] Hamidreza Hashempour , Fred J. Meyer , Fabrizio Lombardi , Farzin Karimi Hybrid Multisite Testing at Manufacturing. [Citation Graph (0, 0)][DBLP ] Conf ] Zhen Shi , Peter Sandborn Optimization of Test/Diagnosis/Rework Location(s) and Characteristics in Electronic Systems Assembly Using Real-Coded Genetic Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Burnell G. West Simultaneous Bidirectional Test Data Flow for a Low-cost Wafer Test Strategy. [Citation Graph (0, 0)][DBLP ] Conf ] Liviu Miclea , Enyedi Szilárd , Gavril Toderean , Alfredo Benso , Paolo Prinetto Agent Based DBIST/DBISR And Its Web/Wireless Management. [Citation Graph (0, 0)][DBLP ] Conf ] Olivier Caty , Ismet Bayraktaroglu , Amitava Majumdar , Richard Lee , John Bell , Lisa Curhan Instruction Based BIST for Board/System Level Test of External Memories and Internconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Hardi Hungar , Tiziana Margaria , Bernhard Steffen Test-Based Model Generation For Legacy Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Rakesh N. Joshi , Kenneth L. Williams , Lee Whetsel Evolution of IEEE 1149.1 Addressable Shadow Protocol Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Francisco DaSilva , Yervant Zorian , Lee Whetsel , Karim Arabi , Rohit Kapur Overview of the IEEE P1500 Standard. [Citation Graph (0, 0)][DBLP ] Conf ] Michael G. Wahl , Sudipta Bhawmik , Kamran Zarrineh , Pradipta Ghosh , Scott Davidson , Peter Harrod The P1500 DFT Disclosure Document: A Standard to Communicate Mergeable Core DFT Data. [Citation Graph (0, 0)][DBLP ] Conf ] Kenichi Kataoka , Toshihiro Itoh , Tadatomo Suga Low Contact-Force Fritting Probe Card Using Buckling Microcantilevers. [Citation Graph (0, 0)][DBLP ] Conf ] Mike Tripp , T. M. Mak , Anne Meixner Elimination of Traditional Functional Testing of Interface Timings at Intel. [Citation Graph (0, 0)][DBLP ] Conf ] Cheng Jia , Linda S. Milor A BIST Solution for The Test of I/O Speed. [Citation Graph (0, 0)][DBLP ] Conf ] Brady Benware , Chris Schuermyer , Sreenevasan Ranganathan , Robert Madge , Prabhu Krishnamurthy , Nagesh Tamarapalli , Kun-Han Tsai , Janusz Rajski Impact of Multiple-Detect Test Patterns on Product Quality. [Citation Graph (0, 0)][DBLP ] Conf ] Li-C. Wang , Angela Krstic , Leonard Lee , Kwang-Ting Cheng , M. Ray Mercer , Thomas W. Williams , Magdy S. Abadir Using Logic Models To Predict The Detection Behavior Of Statistical Timing Defects. [Citation Graph (0, 0)][DBLP ] Conf ] Piet Engelke , Ilia Polian , Michel Renovell , Bernd Becker Simulating Resistive Bridging and Stuck-At Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Masao Naruse , Irith Pomeranz , Sudhakar M. Reddy , Sandip Kundu On-chip Compression of Output Responses with Unknown Values Using LFSR Reseeding. [Citation Graph (0, 0)][DBLP ] Conf ] Harald P. E. Vranken , Friedrich Hapke , Soenke Rogge , Domenico Chindamo , Erik H. Volkerink ATPG Padding And ATE Vector Repeat Per Port For Reducing Test Data Volume. [Citation Graph (0, 0)][DBLP ] Conf ] Huaxing Tang , Sudhakar M. Reddy , Irith Pomeranz On Reducing Test Data Volume and Test Application Time for Multiple Scan Chain Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Kun Young Chung , Sandeep K. Gupta Structural Delay Testing of Latch-based High-speed Pipelines with Time Borrowing. [Citation Graph (0, 0)][DBLP ] Conf ] Jayashree Saxena , Kenneth M. Butler , Vinay B. Jayaram , Subhendu Kundu , N. V. Arvind , Pravin Sreeprakash , Manfred Hachinger A Case Study of IR-Drop in Structured At-Speed Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Haluk Konuk , Leon Xiao DFFT : Design For Functional Testability. [Citation Graph (0, 0)][DBLP ] Conf ] Clayton Gibbs Backplane Test Bus Applications For IEEE STD 1149.1. [Citation Graph (0, 0)][DBLP ] Conf ] L. Forli , Jean Michel Portal , Didier Née , B. Borot Infrastructure IP for Back-End Yield Improvement. [Citation Graph (0, 0)][DBLP ] Conf ] Erik Larsson , Zebo Peng A Reconfigurable Power-Conscious Core Wrapper and its Application to SOC Test Scheduling. [Citation Graph (0, 0)][DBLP ] Conf ] Tom Waayers An improved Test Control Architecture and Test Control Expansion for Core-Based System Chips. [Citation Graph (0, 0)][DBLP ] Conf ] Zhen Guo , Jacob Savir Analog Circuit Test using Transfer Function Coe .cient Estimates. [Citation Graph (0, 0)][DBLP ] Conf ] Haralampos-G. D. Stratigopoulos , Yiorgos Makris Concurrent Error Detection in Linear Analog Circuits Using State Estimation. [Citation Graph (0, 0)][DBLP ] Conf ] Ramakrishna Voorakaranam , Randy Newby , Sasikumar Cherubal , Bob Cometta , Thomas Kuehl , David M. Majernik , Abhijit Chatterjee Production Deployment of a Fast Transient Testing Methodology for Analog Circuits : Case Study and Results. [Citation Graph (0, 0)][DBLP ] Conf ] Arun A. Joseph , Hans G. Kerkhoff Towards Structural Testing of Superconductor Electronics. [Citation Graph (0, 0)][DBLP ] Conf ] Fei Su , Sule Ozev , Krishnendu Chakrabarty Testing of Droplet-Based Microelectrofluidic Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Mahim Mishra , Seth Copen Goldstein Defect Tolerance at the End of the Roadmap. [Citation Graph (0, 0)][DBLP ] Conf ] Frank Poehl , Matthias Beck , Ralf Arnold , Peter Muhmenthaler , Nagesh Tamarapalli , Mark Kassab , Nilanjan Mukherjee , Janusz Rajski Industrial Experience with Adoption of EDT for Low-Cost Test without Concessions. [Citation Graph (0, 0)][DBLP ] Conf ] Graham Hetherington , Richard Simpson Circular BIST testing the digital logic within a high speed Serdes. [Citation Graph (0, 0)][DBLP ] Conf ] David M. Wu , Mike Lin , Subhasish Mitra , Kee Sup Kim , Anil Sabbavarapu , Talal Jaber , Pete Johnson , Dale March , Greg Parrish H-DFT: A Hybrid DFT Architecture For Low-Cost High Quality Structural Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Erik Chmelar FPGA Interconnect Delay Fault Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Dereck A. Fernandes , Ian G. Harris Application of Built in Self-Test for Interconnect Testing of FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Charles E. Stroud , Keshia N. Leach , Thomas A. Slaughter BIST for Xilinx 4000 and Spartan Series FPGAs: A Case Study. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth P. Parker Defect Coverage of Boundary-Scan Tests: What does it mean when a Boundary-Scan test passes?. [Citation Graph (0, 0)][DBLP ] Conf ] Wouter Rijckaert , Frans de Jong Board Test Coverage: The Value of Prediction and How to Compare Numbers. [Citation Graph (0, 0)][DBLP ] Conf ] Frans de Jong , Leon van de Logt IEEE P1581: To Live or Let die? [Citation Graph (0, 0)][DBLP ] Conf ] Rubin A. Parekhji Panel Synopsis - How (In)Adequate is One Time Testing?. [Citation Graph (0, 0)][DBLP ] Conf ] Adit D. Singh Should Nanometer Circuits be Periodically Tested in the Field?. [Citation Graph (0, 0)][DBLP ] Conf ] Phil Nigh The Increasing Importance of On-line Testing to Ensure High-Reliability Products. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Nicolaidis Reliability Threats in VDSM - Shortcomings in Conventional Test and Fault-Tolerance Alternatives. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Ehlig How (In)Adequate is One-time Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Yervant Zorian Yield Threats and Inadequacy of One-time Test. [Citation Graph (0, 0)][DBLP ] Conf ] Geir Eide , Kenneth E. Posse Open Microphone - My DFT is better than yours ... [Citation Graph (0, 0)][DBLP ] Conf ] Mustapha Slamani RF Test 101: Defining the Problem, Finding Solutions. [Citation Graph (0, 0)][DBLP ] Conf ] Abhijit Chatterjee Seamless Research Between Academia And Industry To Facilitate Test Of Integrated High-Speed Wireless Systems: Is This An Illusion? [Citation Graph (0, 0)][DBLP ] Conf ] William R. Eisenstadt Improving Wireless Product Testing via University and Industry Collaboration. [Citation Graph (0, 0)][DBLP ] Conf ] Jim Paviol Improving Wireless Product Testing: An Opportunity for University and Industry Collaboratio. [Citation Graph (0, 0)][DBLP ] Conf ] Ian G. Harris The Confluence of Manufacturing Test and Design Validation. [Citation Graph (0, 0)][DBLP ] Conf ] Franco Fummi The Confluence of Manufacturing Test and Design Validation. [Citation Graph (0, 0)][DBLP ] Conf ] Prab Varma Design Verification Problems: Test To The Rescue?. [Citation Graph (0, 0)][DBLP ] Conf ] Kwang-Ting Cheng The Confluence of Manufacturing Test and Design Validation. [Citation Graph (0, 0)][DBLP ] Conf ] Jim Webster PXI: A Solution For Board Functional Test? [Citation Graph (0, 0)][DBLP ] Conf ] Eric L. Smitt Selecting PXI Architecture for Board (System) Functional Test. [Citation Graph (0, 0)][DBLP ] Conf ] Bob Stasonis PXI - A New Architecture for Many Testing Requirements. [Citation Graph (0, 0)][DBLP ] Conf ] Fidel Muradali Future ATE: Perspectives & Requirements. [Citation Graph (0, 0)][DBLP ] Conf ] Donald L. Wheater ATE-Customer Perspectives & Requirements Panel. [Citation Graph (0, 0)][DBLP ] Conf ] John Roberts Test Outsourcing - A Subcontract Manufacturer's Perspective. [Citation Graph (0, 0)][DBLP ] Conf ] Lee Y. Song Future ATE: Perspectives & Requirements. [Citation Graph (0, 0)][DBLP ] Conf ] Tom Newsom Future ATE for System on a Chip... Some Perspectives. [Citation Graph (0, 0)][DBLP ] Conf ] Fidel Muradali Diagnosis in Modern Design - Just the Tip of the Iceberg. [Citation Graph (0, 0)][DBLP ] Conf ] Robert F. Molyneaux Debug and Diagnosis in the Age of System-on-a-Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Bill Huott Diagnosis in Modern Design to Volume - The Tip of the Iceberg. [Citation Graph (0, 0)][DBLP ] Conf ] Wu-Tung Cheng Silicon Diagnosis. [Citation Graph (0, 0)][DBLP ] Conf ] Mike Li Production Test Challenges And Possible Solutions For Multiple GB/s ICs. [Citation Graph (0, 0)][DBLP ] Conf ] Takahiro J. Yamaguchi Open Architecture ATE and 250 Consecutive UIs. [Citation Graph (0, 0)][DBLP ] Conf ] John C. Johnson Cost Containment for High-Volume Test of Multi-GB/s Ports. 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