Conferences in DBLP
Wayne M. Needham , Cheryl Prunty , Yeoh Eng Hong High volume microprocessor test escapes, an analysis of defects our tests are missing. [Citation Graph (0, 0)][DBLP ] Conf ] Fernando M. Gonçalves , Marcelino B. Santos , Isabel C. Teixeira , João Paulo Teixeira Defect-oriented test quality assessment using fault sampling and simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Phil Nigh , David P. Vallett , Atul Patel , Jason Wright Failure analysis of timing and IDDq-only failures from the SEMATECH test methods experiment. [Citation Graph (0, 0)][DBLP ] Conf ] Jan Otterstedt , Dirk Niggemeyer , T. W. Williams Detection of CMOS address decoder open faults with March and pseudo random memory tests. [Citation Graph (0, 0)][DBLP ] Conf ] Said Hamdioui , A. J. van de Goor Consequences of port restrictions on testing two-port memories. [Citation Graph (0, 0)][DBLP ] Conf ] Kamran Zarrineh , Shambhu J. Upadhyaya , Sreejit Chakravarty A new framework for generating optimal March tests for memory arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Pamela S. Gillis , Francis Woytowich , Kevin McCauley , Ulrich Baur Delay test of chip I/Os using LSSD boundary scan. [Citation Graph (0, 0)][DBLP ] Conf ] Karim Arabi , Hassan Ihs , Christian Dufaza , Bozena Kaminska Digital oscillation-test method for delay and stuck-at fault testing of digital circuits. [Citation Graph (0, 0)][DBLP ] Conf ] E. Kofi Vida-Torku , George Joos Designing for scan test of high performance embedded memories. [Citation Graph (0, 0)][DBLP ] Conf ] Andreas C. Pfahnl , John H. Lienhard V. , Alexander H. Slocum Maximizing handler thermal throughput with a rib-roughened test tray. [Citation Graph (0, 0)][DBLP ] Conf ] Andreas C. Pfahnl , John H. Lienhard V. , Alexander H. Slocum Temperature control of a handler test interface. [Citation Graph (0, 0)][DBLP ] Conf ] Mark Malinoski , James Maveety , Steve Knostman , Tom Jones A test site thermal control system for at-speed manufacturing testing. [Citation Graph (0, 0)][DBLP ] Conf ] Yervant Zorian , Erik Jan Marinissen , Sujit Dey Testing embedded-core based system chips. [Citation Graph (0, 0)][DBLP ] Conf ] Zhe Zhao , Bahram Pouya , Nur A. Touba BETSY: synthesizing circuits for a specified BIST environment. [Citation Graph (0, 0)][DBLP ] Conf ] Han Bin Kim , Takeshi Takahashi , Dong Sam Ha Test session oriented built-in self-testable data path synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Srinivas Devadas , Kurt Keutzer An algorithmic approach to optimizing fault coverage for BIST logic synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Anne E. Gattiker , Wojciech Maly Toward understanding "Iddq-only" fails. [Citation Graph (0, 0)][DBLP ] Conf ] Jonathan T.-Y. Chang , Chao-Wen Tseng , Chien-Mo James Li , Mike Purtell , Edward J. McCluskey Analysis of pattern-dependent and timing-dependent failures in an experimental test chip. [Citation Graph (0, 0)][DBLP ] Conf ] Alan W. Righter , Charles F. Hawkins , Jerry M. Soden , Peter C. Maxwell CMOS IC reliability indicators and burn-in economics. [Citation Graph (0, 0)][DBLP ] Conf ] Manoj Sachdev , Peter Janssen , Victor Zieren Defect detection with transient current testing and its potential for deep sub-micron CMOS ICs. [Citation Graph (0, 0)][DBLP ] Conf ] Rajesh Pendurkar , Abhijit Chatterjee , Yervant Zorian A distributed BIST technique for diagnosis of MCM interconnections. [Citation Graph (0, 0)][DBLP ] Conf ] Alex S. Biewenga , Math Muris , Rodger Schuttert , Urs Fawer Testing a multichip package for a consumer communications application. [Citation Graph (0, 0)][DBLP ] Conf ] David C. Keezer , K. E. Newman , J. S. Davis Improved sensitivity for parallel test of substrate interconnections. [Citation Graph (0, 0)][DBLP ] Conf ] Bruce C. Kim , David C. Keezer , Abhijit Chatterjee A high throughput test methodology for MCM substrates. [Citation Graph (0, 0)][DBLP ] Conf ] Benoit Dufort , Gordon W. Roberts Increasing the performance of arbitrary waveform generators using sigma-delta coding techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Eric Rosenfeld , Solomon Max When "almost" is good enough: a fresh look at DSP clock rates. [Citation Graph (0, 0)][DBLP ] Conf ] Luke S. L. Hsieh Reduction of errors due to source and meter in the nonlinearity test. [Citation Graph (0, 0)][DBLP ] Conf ] S. Sasho , M. Shibata Multi-output one-digitizer measurement. [Citation Graph (0, 0)][DBLP ] Conf ] Hervé Deshayes Cost of test reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Toshinori Ishii , Hideaki Yoshida Fine pitch (45 micron) P4 probing. [Citation Graph (0, 0)][DBLP ] Conf ] Frederick L. Taber An introduction to area array probing. [Citation Graph (0, 0)][DBLP ] Conf ] Jim Anderson Integrated probe card/interface solutions for specific test applications. [Citation Graph (0, 0)][DBLP ] Conf ] Erik Jan Marinissen , Robert G. J. Arendsen , Gerard Bos , Hans Dingemanse , Maurice Lousberg , Clemens Wouters A structured and scalable mechanism for test access to embedded reusable cores. [Citation Graph (0, 0)][DBLP ] Conf ] Prab Varma , Sandeep Bhatia A structured test re-use methodology for core-based system chips. [Citation Graph (0, 0)][DBLP ] Conf ] Lee Whetsel Core test connectivity, communication, and control. [Citation Graph (0, 0)][DBLP ] Conf ] Janusz Rajski , Jerzy Tyszer Modular logic built-in self-test for IP cores. [Citation Graph (0, 0)][DBLP ] Conf ] Wen-Ben Jone , Jiann-Chyi Rau , Shih-Chieh Chang , Yu-Liang Wu A tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Srivaths Ravi , Ganesh Lakshminarayana , Niraj K. Jha TAO: regular expression based high-level testability analysis and optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Samy Makar A layout-based approach for ordering scan chain flip-flops. [Citation Graph (0, 0)][DBLP ] Conf ] Mokhtar Hirech , James Beausang , Xinli Gu A new approach to scan chain reordering using physical design information. [Citation Graph (0, 0)][DBLP ] Conf ] R. Dean Adams , Edmond S. Cooley , Patrick R. Hansen Quad DCVS dynamic logic fault modeling and testing. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Dahlgren Switch-level bridging fault simulation in the presence of feedbacks. [Citation Graph (0, 0)][DBLP ] Conf ] Sandip Kundu GateMaker: a transistor to gate level model extractor for simulation, automatic test pattern generation and verification. [Citation Graph (0, 0)][DBLP ] Conf ] Reuben Schrift Digital bus faults measuring techniques. [Citation Graph (0, 0)][DBLP ] Conf ] John McDermid Limited access testing: IEEE 1149.4-instrumentation and methods. [Citation Graph (0, 0)][DBLP ] Conf ] Frank W. Angelotti Generating interconnect models from prototype hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Charles E. Stroud , Sajitha Wijesuriya , Carter Hamilton , Miron Abramovici Built-in self-test of FPGA interconnect. [Citation Graph (0, 0)][DBLP ] Conf ] Rainer Dorsch , Hans-Joachim Wunderlich Accumulator based deterministic BIST. [Citation Graph (0, 0)][DBLP ] Conf ] Nilanjan Mukherjee , Tapan J. Chakraborty , Sudipta Bhawmik A BIST scheme for the detection of path-delay faults. [Citation Graph (0, 0)][DBLP ] Conf ] Kaigham J. Gabriel Microelectromechanical systems (MEMS) tutorial. [Citation Graph (0, 0)][DBLP ] Conf ] Glenn F. LaVigne , Sam L. Miller A performance analysis system for MEMS using automated imaging methods. [Citation Graph (0, 0)][DBLP ] Conf ] Joep Aerts , Erik Jan Marinissen Scan chain design for test time reduction in core-based ICs. [Citation Graph (0, 0)][DBLP ] Conf ] Abhijit Jas , Nur A. Touba Test vector decompression via cyclical scan chains and its application to testing core-based designs. [Citation Graph (0, 0)][DBLP ] Conf ] Makoto Sugihara , Hiroshi Date , Hiroto Yasuura A novel test methodology for core-based system LSIs and a testing time minimization problem. [Citation Graph (0, 0)][DBLP ] Conf ] Craig Hunter , Justin Gaither Design and implementation of the "G2" PowerPC 603e-embedded microprocessor core. [Citation Graph (0, 0)][DBLP ] Conf ] Anjali Kinra , Aswin Mehta , Neal Smith , Jackie Mitchell , Fred Valente Diagnostic techniques for the UltraSPARC microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Dilip K. Bhavsar , David R. Akeson , Michael K. Gowan , Daniel B. Jackson Testability access of the high speed test features in the Alpha 21264 microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Naveed Zaman , Antony Spilman Triggering and clocking architecture for mixed signal test. [Citation Graph (0, 0)][DBLP ] Conf ] Ed Chang , David Cheung , Robert E. Huston , Jim Seaton , Gary Smith A scalable architecture for VLSI test. [Citation Graph (0, 0)][DBLP ] Conf ] Robert Gage , Ben Brown The CAT-exact data transfer to DDS-generated clock domains in a single-chip modular solution. [Citation Graph (0, 0)][DBLP ] Conf ] Steffen Tarnick , Albrecht P. Stroele Embedded self-testing checkers for low-cost arithmetic codes. [Citation Graph (0, 0)][DBLP ] Conf ] Cecilia Metra , Michele Favalli , Bruno Riccò On-line detection of logic errors due to crosstalk, delay, and transient faults. [Citation Graph (0, 0)][DBLP ] Conf ] Eduardo J. Peralías , Adoración Rueda , Juan A. Prieto , José L. Huertas DfT and on-line test of high-performance data converters: a practical case. [Citation Graph (0, 0)][DBLP ] Conf ] A. Castillejo , D. Veychard , Salvador Mir , Jean-Michel Karam , Bernard Courtois Failure mechanisms and fault classes for CMOS-compatible microelectromechanical systems. [Citation Graph (0, 0)][DBLP ] Conf ] Abhijeet Kolpekwar , Ronald D. Blanton , David Woodilla Failure modes for stiction in surface-micromachined MEMS. [Citation Graph (0, 0)][DBLP ] Conf ] Abhijeet Kolpekwar , Chris S. Kellen , Ronald D. Blanton MEMS fault model generation using CARAMEL. [Citation Graph (0, 0)][DBLP ] Conf ] Kuo-Chan Huang , Chung-Len Lee , Jwu E. Chen Maximization of power dissipation under random excitation for burn-in testing. [Citation Graph (0, 0)][DBLP ] Conf ] Hyungwon Kim , John P. Hayes High-coverage ATPG for datapath circuits with unimplemented blocks. [Citation Graph (0, 0)][DBLP ] Conf ] Fabrizio Ferrandi , Franco Fummi , Donatella Sciuto Implicit test generation for behavioral VHDL models. [Citation Graph (0, 0)][DBLP ] Conf ] Dan Proskauer High quality, easy to use, on time ATE software Can it be done? [Citation Graph (0, 0)][DBLP ] Conf ] John Oonk Leveraging new standards in ATE software. [Citation Graph (0, 0)][DBLP ] Conf ] Craig Force , Tom Austin Testing the design: the evolution of test simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Wohl , John A. Waicukauski Extracting gate-level networks from simulation tables. [Citation Graph (0, 0)][DBLP ] Conf ] Brion L. Keller , Kevin McCauley , Joseph Swenton , James Youngs ATPG in practical and non-traditional applications. [Citation Graph (0, 0)][DBLP ] Conf ] Weiyu Chen , Sandeep K. Gupta , Melvin A. Breuer Test generation in VLSI circuits for crosstalk noise. [Citation Graph (0, 0)][DBLP ] Conf ] Priyank Kalla , Maciej J. Ciesielski A comprehensive approach to the partial scan problem using implicit state enumeration. [Citation Graph (0, 0)][DBLP ] Conf ] Shih-Chieh Chang , Shi-Sen Chang , Wen-Ben Jone , Chien-Chung Tsai A novel combinational testability analysis by considering signal correlation. [Citation Graph (0, 0)][DBLP ] Conf ] Yiorgos Makris , Alex Orailoglu DFT guidance through RTL test justification and propagation analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Y. Xing Defect-oriented testing of mixed-signal ICs: some industrial experience. [Citation Graph (0, 0)][DBLP ] Conf ] Ara Hajjar , Gordon W. Roberts A high speed and area efficient on-chip analog waveform extractor. [Citation Graph (0, 0)][DBLP ] Conf ] Benoît R. Veillette , Gordon W. Roberts Stimulus generation for built-in self-test of charge-pump phase-locked loops. [Citation Graph (0, 0)][DBLP ] Conf ] Leland L. Day , Paul A. Ganfield , Dennis M. Rickert , Fred J. Ziegler Test methodology for a microprocessor with partial scan. [Citation Graph (0, 0)][DBLP ] Conf ] Mary P. Kusko , Bryan J. Robbins , Thomas J. Snethen , Peilin Song , Thomas G. Foote , William V. Huott Microprocessor test and test tool methodology for the 500 MHz IBM S/390 G5 chip. [Citation Graph (0, 0)][DBLP ] Conf ] Young-Jun Kwon , Ben Mathew , Hong Hao FakeFault: a silicon debug software tool for microprocessor embedded memory arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel R. Knebel , Pia Sanda , Moyra K. McManus , Jeffrey A. Kash , James C. Tsang , David P. Vallett , Leendert M. Huisman , Phil Nigh , Rick Rizzolo , Peilin Song , Franco Motika Diagnosis and characterization of timing-related defects by time-dependent light emission. [Citation Graph (0, 0)][DBLP ] Conf ] Mario Paniccia , Travis M. Eiles , V. R. M. Rao , Wai Mun Yee Novel optical probing technique for flip chip packaged microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Jayashree Saxena , Kenneth M. Butler , Hari Balachandran , David B. Lavo , Tracy Larrabee , F. Joel Ferguson , Brian Chess On applying non-classical defect models to automated diagnosis. [Citation Graph (0, 0)][DBLP ] Conf ] Yuan-Chieh Hsu , Sandeep K. Gupta A new path-oriented effect-cause methodology to diagnose delay failures. [Citation Graph (0, 0)][DBLP ] Conf ] Alfredo Benso , Paolo Prinetto , Maurizio Rebaudengo , Matteo Sonza Reorda A fault injection environment for microprocessor-based boards. [Citation Graph (0, 0)][DBLP ] Conf ] Chauchin Su , Shung-Won Jeng , Yue-Tsang Chen Boundary scan BIST methodology for reconfigurable systems. [Citation Graph (0, 0)][DBLP ] Conf ] Susana Stoica A lifecycle approach to design validation is it necessary? Is it feasible? [Citation Graph (0, 0)][DBLP ] Conf ] Moshe Ben-Bassat , Israel Beniaminy , David Joseph Can model-based and case-based expert systems operate together? [Citation Graph (0, 0)][DBLP ] Conf ] Leendert M. Huisman Correlations between path delays and the accuracy of performance prediction. [Citation Graph (0, 0)][DBLP ] Conf ] Jerry Katz High speed testing-have the laws of physics finally caught up with us? [Citation Graph (0, 0)][DBLP ] Conf ] Wajih Dalal , Daniel A. Rosenthal Measuring jitter of high speed data channels using undersampling techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Jan B. Wilstrup A method of serial data jitter analysis using one-shot time interval measurements. [Citation Graph (0, 0)][DBLP ] Conf ] David C. Keezer , Q. Zhou Alternative interface methods for testing high speed bidirectional signals. [Citation Graph (0, 0)][DBLP ] Conf ] Bob Hickling AVM/sup TM/ a more usable way to execute vectors at double speed. [Citation Graph (0, 0)][DBLP ] Conf ] Rajiv Pandey , Dan Higgins probe card-a solution for at-speed, high density, wafer probing. [Citation Graph (0, 0)][DBLP ] Conf ] W. Mertin , Anton Leyk , Ulf Behnke , V. Wittpahl Contactless gigahertz testing. [Citation Graph (0, 0)][DBLP ] Conf ] Dilip K. Bhavsar , Ugonna Echeruo , David R. Akeson , William J. Bowhill A highly testable and diagnosable fabrication process test chip. [Citation Graph (0, 0)][DBLP ] Conf ] T. M. Mak , Debika Bhattacharya , Cheryl Prunty , Bob Roeder , Nermine Ramadan , Joel Ferguson , Jianlin Yu Cache RAM inductive fault analysis with fab defect modeling. [Citation Graph (0, 0)][DBLP ] Conf ] Ivo Schanstra , Dharmajaya Lukita , A. J. van de Goor , Kees Veelenturf , Paul J. van Wijnen Semiconductor manufacturing process monitoring using built-in self-test for embedded memories. [Citation Graph (0, 0)][DBLP ] Conf ] Peter C. Maxwell , Jeff Rearick Estimation of defect-free IDDQ in submicron circuits using switch level simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Jonathan T.-Y. Chang , Edward J. McCluskey Detecting resistive shorts for CMOS domino circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Yukio Okuda , Isao Kubota , Masahiro Watanabe Defect level prediction for I_DDQ testing. [Citation Graph (0, 0)][DBLP ] Conf ] Ramesh Karri , Nilanjan Mukherjee Versatile BIST: an integrated approach to on-line/off-line BIST. [Citation Graph (0, 0)][DBLP ] Conf ] Ioannis Voyiatzis , Antonis M. Paschalis , Dimitris Nikolos , Constantinos Halatsis R-CBIST: an effective RAM-based input vector monitoring concurrent BIST technique. [Citation Graph (0, 0)][DBLP ] Conf ] Chouki Aktouf , Ghassan Al Hayek , Chantal Robach On-line testing of scalable signal processing architectures using a software test method. [Citation Graph (0, 0)][DBLP ] Conf ] Carlos G. Parodi , Vishwani D. Agrawal , Michael L. Bushnell , Shianling Wu A non-enumerative path delay fault simulator for sequential circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Ilker Hamzaoglu , Janak H. Patel Compact two-pattern test set generation for combinational and full scan circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Surendra Bommu , Srimat T. Chakradhar , Kiran B. Doreswamy Static test sequence compaction based on segment reordering and accelerated vector restoration. [Citation Graph (0, 0)][DBLP ] Conf ] Tony Taylor Standard test interface language (STIL), extending the standard. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Wohl , John A. Waicukauski Defining ATPG rules checking in STIL. [Citation Graph (0, 0)][DBLP ] Conf ] Bulent I. Dervisoglu , Mike Ricchetti , William Eklow Shared I/O-cell structures: a framework for extending the IEEE 1149.1 boundary-scan standard. [Citation Graph (0, 0)][DBLP ] Conf ] Jian Shen , Jacob A. Abraham Native mode functional test generation for processors with applications to self test and design validation. [Citation Graph (0, 0)][DBLP ] Conf ] Morris Lin , James R. Armstrong , F. Gail Gray A goal tree based high-level test planning system for DSP real number models. [Citation Graph (0, 0)][DBLP ] Conf ] Maisaa Khalil , Yves Le Traon , Chantal Robach Towards an automatic diagnosis for high-level design validation. [Citation Graph (0, 0)][DBLP ] Conf ] Claude Thibeault , Luc Boisvert Diagnosis method based on /spl Delta/Iddq probabilistic signatures: experimental results. [Citation Graph (0, 0)][DBLP ] Conf ] Bapiraju Vinnakota , Wanli Jiang , Dechang Sun Process-tolerant test with energy consumption ratio. [Citation Graph (0, 0)][DBLP ] Conf ] Lan Zhao , D. M. H. Walker , Fabrizio Lombardi Detection of bridging faults in logic resources of configurable FPGAs using I_DDQ. [Citation Graph (0, 0)][DBLP ] Conf ] Janusz Rajski , Nagesh Tamarapalli , Jerzy Tyszer Automated synthesis of large phase shifters for built-in self-test. [Citation Graph (0, 0)][DBLP ] Conf ] Gundolf Kiefer , Hans-Joachim Wunderlich Deterministic BIST with multiple scan chains. [Citation Graph (0, 0)][DBLP ] Conf ] Huan-Chih Tsai , Sudipta Bhawmik , Kwang-Ting Cheng An almost full-scan BIST solution-higher fault coverage and shorter test application time. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy A diagnostic test generation procedure for synchronous sequential circuits based on test elimination. [Citation Graph (0, 0)][DBLP ] Conf ] David B. Lavo , Brian Chess , Tracy Larrabee , Ismed Hartanto Probabilistic mixed-model fault diagnosis. [Citation Graph (0, 0)][DBLP ] Conf ] Vamsi Boppana , Masahiro Fujita Modeling the unknown! Towards model-independent fault and error diagnosis. [Citation Graph (0, 0)][DBLP ] Conf ] Michel Renovell , Jean Michel Portal , Joan Figueras , Yervant Zorian SRAM-based FPGA's: testing the LUT/RAM modules. [Citation Graph (0, 0)][DBLP ] Conf ] Ilyoung Kim , Yervant Zorian , Goh Komoriya , Hai Pham , Frank P. Higgins , Jim L. Lewandowski Built in self repair for embedded high density SRAM. [Citation Graph (0, 0)][DBLP ] Conf ] Roderick McConnell , Udo Möller , Detlev Richter How we test Siemens Embedded DRAM Cores. [Citation Graph (0, 0)][DBLP ] Conf ] William R. Simpson Enough is enough already. [Citation Graph (0, 0)][DBLP ] Conf ] Bret A. Stewart Test: when is enough enough? [Citation Graph (0, 0)][DBLP ] Conf ] Susana Stoica How much testing is enough. [Citation Graph (0, 0)][DBLP ] Conf ] Keith Baker Spice up your life: simulate mixed-signal ICs! [Citation Graph (0, 0)][DBLP ] Conf ] Mark Burns Testing mixed signal SOCs. [Citation Graph (0, 0)][DBLP ] Conf ] Ken Lanier When two worlds merge [test issues for system-level ICs]. [Citation Graph (0, 0)][DBLP ] Conf ] Brian Chess Accounting for the unexpected: fault diagnosis out of the ivory tower. [Citation Graph (0, 0)][DBLP ] Conf ] Scott Davidson ASIC jeopardy-diagnosing without a FAB. [Citation Graph (0, 0)][DBLP ] Conf ] Vallluri R. Rao Design for diagnostics views and experiences. [Citation Graph (0, 0)][DBLP ] Conf ] Jayashree Saxena IC diagnosis: preventing wars and war stories. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Nicolaidis Scaling Deeper to Submicron: On-Line Testing to the Rescue. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Nicolaidis Design for soft-error robustness to rescue deep submicron scaling. [Citation Graph (0, 0)][DBLP ] Conf ] Todd E. Rockoff Learning to knit SOCs profitably. [Citation Graph (0, 0)][DBLP ] Conf ] Kamalesh N. Ruparel SOC test: the devil is in the details of integration/implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Prab Varma System chip test: are we there yet? [Citation Graph (0, 0)][DBLP ] Conf ] Robert C. Aitken On-chip versus off-chip test: an artificial dichotomy. [Citation Graph (0, 0)][DBLP ] Conf ] Neil Kelly BIST vs. ATE for testing system-on-a-chip. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen K. Sunter BIST vs. ATE: need a different vehicle? [Citation Graph (0, 0)][DBLP ] Conf ] Satoru Tanoi BIST: required for embedded DRAM. [Citation Graph (0, 0)][DBLP ] Conf ] Wayne M. Needham Just how real is the SIA roadmap. [Citation Graph (0, 0)][DBLP ] Conf ] Phil Nigh SIA Roadmap: test must not limit future technologies. [Citation Graph (0, 0)][DBLP ] Conf ] William R. Ortner How real is the new SIA roadmap for mixed-signal test equipment? [Citation Graph (0, 0)][DBLP ] Conf ] Todd E. Rockoff The rise and fall of the ATE industry. [Citation Graph (0, 0)][DBLP ] Conf ] Burnell G. West Functional ATE can meet the challenges. [Citation Graph (0, 0)][DBLP ] Conf ] Kwang-Ting Cheng National Science Foundation Workshop on Future Research Directions in Testing of Electronic Circuits and Systems: executive summary of workshop report. [Citation Graph (0, 0)][DBLP ] Conf ] Jack Ferguson Flying probe test systems: capabilities for effective testing. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth M. Butler The stuck-at fault: it ain't over 'til it's over. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth M. Butler Stuck-at fault: a fault model for the next millennium. [Citation Graph (0, 0)][DBLP ] Conf ] Jeff Rearick Buying time for the stuck-at fault model. [Citation Graph (0, 0)][DBLP ] Conf ] Anne E. Gattiker , Wojciech Maly Current signatures: application [to CMOS]. [Citation Graph (0, 0)][DBLP ] Conf ] 