Conferences in DBLP
Phil Robinson Concurrent Engineering: Creating Designs That Are Faster, Better and Available Sooner. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:19- [Conf ] Sudha Sarma Built-In Self-Test Considerations in a High-Performance, General-Purpose Processor. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:21-27 [Conf ] Paul H. Bardell , Michael J. Lapointe Production Experience with Built-In Self-Test in the IBM ES/9000 System. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:28-36 [Conf ] Richard Illman , Terry Bird , George Catlow , Steve Clarke , Len Theobald , Gil Willetts Built-In Self-Test of the VLSI Content Addressable Filestore. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:37-46 [Conf ] Charles E. Stroud Built-In Self-Test for High-Speed Data-Path Circuitry. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:47-56 [Conf ] Thomas Kropf , Hans-Joachim Wunderlich A Common Approach to Test Generation and Hardware Verification Based on Temporal Logic. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:57-66 [Conf ] Hyunwoo Cho , Gary D. Hachtel , Fabio Somenzi Fast Sequential ATPG Based on Implicit State Enumeration. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:67-74 [Conf ] Toshinobu Ono , Masaaki Yoshida A Test Generation Method for Sequential Circuits Based on Maximum Utilization of Internal States. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:75-82 [Conf ] Tsu-Wei Ku , Wei-Kong Chia A Sequential Test Generator with Explicit Elimination of Easy-to-Test Faults. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:83-87 [Conf ] Mark F. Lefebvre Test Generation: A Boundary Scan Implementation for Module Interconnect Testing. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:88-95 [Conf ] Jung-Cheun Lien , Melvin A. Breuer Maximal Diagnosis for Wiring Networks. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:96-105 [Conf ] Frans de Jong , Frank van der Heyden Testing the Integrity of the Boundary Scan Test Infrastructure. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:106-112 [Conf ] Kenneth E. Posse A Design-for-Testability Architecture for Multichip Modules. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:113-121 [Conf ] Jose A. Lyon , Mike Gladden , Eytan Hartung , Eric Hoang , K. Raghunathan Testability Features of the 68HC16Z1. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:122-130 [Conf ] P. Thorel , J. L. Rainard , A. Botta , A. Chemarin , J. Majos Implementing Boundary-Scan and Pseudo-Random BIST in an Asynchronous Transfer Mode Switch. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:131-139 [Conf ] Johan Karlsson , Ulf Gunneflo , Peter Lidén , Jan Torin Two Fault Injection Techniques for Test of Fault Handling Mechanisms. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:140-149 [Conf ] Tony Cheng , Eric Hoang , David Rivera , Alan Haedge , Jamie Fontenot , Glenn Carson Test Grading the 68332. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:150-156 [Conf ] SungHo Kim , Prithviraj Banerjee , Srinivas Patil A Layout Driven Design for Testability Technique for MOS VLSI Circuits. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:157-165 [Conf ] Miron Abramovici , James J. Kulikowski , Rabindra K. Roy The Best Flip-Flops to Scan. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:166-173 [Conf ] Magdy S. Abadir , Joe Newman , Desmond D'Souza , Steve Spencer Partitioning Hierarchical Designs for Testability. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:174-183 [Conf ] John Giraldi , Michael L. Bushnell Search State Equivalence for Redundancy Identification and Test Generation. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:184-193 [Conf ] Irith Pomeranz , Lakshmi N. Reddy , Sudhakar M. Reddy COMPACTEST: A Method to Generate Compact Test Sets for Combinatorial Circuits. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:194-203 [Conf ] Gert-Jan Tromp Minimal Test Sets for Combinatorial Circuits. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:204-209 [Conf ] Dharam Vir Das , Sharad C. Seth , Vishwani D. Agrawal Estimating the Quality of Manufactured Digital Sequential Circuits. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:210-217 [Conf ] Eric Bruls , F. Camerik , H. J. Kretschman , Jochen A. G. Jess A Generic Method to Develop a Defect Monitoring System for IC Processes. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:218-227 [Conf ] Adit D. Singh , C. Mani Krishna On Optimizing Wafer-Probe Testing for Product Quality Using Die-Yield Prediction. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:228-237 [Conf ] M. Marzouki , J. Laurent , Bernard Courtois Coupling Electron-Beam Probing with Knowledge-Based Fault Localization. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:238-247 [Conf ] Rafic Z. Makki , Kasra Daneshvar , Farid Tranjan , Richard Greene On the Integration of Design and Manufacturing for Improved Testability. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:248-255 [Conf ] Klaus Helmreich , Peter Nagel , Werner Wolz , Klaus D. Müller-Glaser An Approach to Chip-Internal Current Monitoring and Measurement Using an Electron Beam Tester. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:256-262 [Conf ] Bong-Hee Park , Premachandran R. Menon Robustly Scan-Testable CMOS Sequential Circuits. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:263-272 [Conf ] Irith Pomeranz , Sudhakar M. Reddy Achieving Complete Delay Fault Testability by Extra Inputs. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:273-282 [Conf ] Rubin A. Parekhji , G. Venkatesh , Sunil D. Sherlekar A Methodology for Designing Optimal Self-Checking Sequential Circuits. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:283-291 [Conf ] Hong Hao , Edward J. McCluskey "Resistive Shorts" Within CMOS Gates. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:292-301 [Conf ] Christopher L. Henderson , Jerry M. Soden , Charles F. Hawkins The Behavior and Testing Implications of CMOS IC Logic Gate Open Circuits. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:302-310 [Conf ] Thomas M. Storey , Wojciech Maly , John Andrews , Myron Miske Stuck Fault and Current Testing Comparison Using CMOS Chip Test. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:311-318 [Conf ] John McWha , Peter Kouklamanis A Product Information Access System for the Verification, Test, Diagnosis and Repair of Electronic Assemblies. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:319-326 [Conf ] Vijay Pitchumani , Pankaj Mayor , Nimish Radia Fault Diagnosis using Functional Fault Models for VHDL descriptions. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:327-337 [Conf ] Gordon F. Taylor , Steven M. Blumenau A Pragmatic Test Data Management System. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:338-344 [Conf ] Scott A. Erjavic Characterization and Control of PLCC and MQFP Lead Inspection Systems. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:345-353 [Conf ] E. Weis , E. Kinsbron , M. Snyder , B. Vogel , N. Croitoru Electromigration Effects in VLSI Due to Various Current Types. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:354-357 [Conf ] Peter C. Maxwell , Robert C. Aitken , Vic Johansen , Inshen Chiang The Effect of Different Test Sets on Quality Level Prediction: When is 80% better than 90%? [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:358-364 [Conf ] Bulent I. Dervisoglu , Gayvin E. Stong Design for Testability: Using Scanpath Techniques for Path-Delay Test and Measurement. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:365-374 [Conf ] Jens Leenstra , Lambert Spaanenburg Hierarchical Test Program Development for Scan Testable Circuits. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:375-384 [Conf ] Sean P. Morley , Ralph Marlett Selectable Length Partial Scan: A Method to Reduce Vector Length. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:385-392 [Conf ] Ankan K. Pramanick , Sudhakar M. Reddy On Multiple Path Propagating Tests for Path Delay Faults. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:393-402 [Conf ] Kwang-Ting Cheng , Srinivas Devadas , Kurt Keutzer A Partial Enhanced-Scan Approach to Robust Delay-Fault Test Generation for Sequential Circuits. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:403-410 [Conf ] Steven D. Millman , James P. Garvey Sr. An Accurate Bridging Fault Test Pattern Generator. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:411-418 [Conf ] William R. Simpson , John W. Sheppard An Intelligent Approach to Automatic Test Equipment. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:419-425 [Conf ] Gary J. Lesmeister A Densely Integrated High Performance CMOS Tester. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:426-429 [Conf ] Bryan J. Dinteman Arbitrary Waveform Generation with Absolute Duration Control. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:430-436 [Conf ] Sally Wilk Effective Implementation of Statistical Process Control in an Integrated Circuit Test Environment. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:437-445 [Conf ] Barbara Cole , Glen Herzog , Phung Ngo , Steven Hinkle , Peter Sherry Statistical Product Monitoring: A Powerful Tool for Quality Improvement. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:446-453 [Conf ] D. L. Smoot , Babur Mustafa Pulat Don't Eliminate Incoming Test - Move It. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:454-462 [Conf ] LaNae J. Avra Allocation and Assignment in High-Level Synthesis for Self-Testable Data Paths. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:463-472 [Conf ] Stephen Pateras , Janusz Rajski Cube-Contained Random Patterns and Their Applications to the Complete Testing of Synthesized Multi-Level Circuits. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:473-482 [Conf ] Andrzej Krasniewski Can Redundancy Enhance Testability? [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:483-491 [Conf ] F. Joel Ferguson , Tracy Larrabee Test Pattern Generation for Realistic Bridge Faults in CMOS ICs. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:492-499 [Conf ] José T. de Sousa , Fernando M. Gonçalves , João Paulo Teixeira IC Defects-Based Testability Analysis. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:500-509 [Conf ] Rosa Rodríguez-Montañés , J. A. Segura , Víctor H. Champac , Joan Figueras , J. A. Rubio Current vs. Logic Testing of Gate Oxide Short, Floating Gate and Bridging Failures in CMOS. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:510-519 [Conf ] Stephen M. Lorusso , Paul N. Bompastore , Michael T. Fertsch Integrating CrossCheck Technology into the Raytheon Test Environment. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:520-529 [Conf ] Robert W. Bassett , Pamela S. Gillis , John J. Shushereba High-Density CMOS Multichip-Module Testing and Diagnosis. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:530-539 [Conf ] J. Miyamoto , N. Ohtsuka , K. Imamiya , N. Tomita , Y. Iyama Multi-Step Stress Test for Yield Improvement of 16Mbit EPROMs with Redundancy Scheme. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:540-547 [Conf ] H.-D. Oberle , Peter Muhmenthaler Test Pattern Development and Evaluation for DRAMs with Fault Simulator RAMSIM. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:548-555 [Conf ] Yoshikazu Morooka , Shigeru Mori , Hiroshi Miyamoto , Michihiro Yamada An Address Maskable Parallel Testing for Ultra High Density DRAMs. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:556-563 [Conf ] Anne Meixner , Wojciech Maly Fault Modeling for the Testing of Mixed Integrated Circuits. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:564-572 [Conf ] Gerard N. Stenbakken , T. Michael Souders Linear Error Modeling of Analog and Mixed-Signal Devices. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:573-581 [Conf ] Abhijit Chatterjee Concurrent Error Detection in Linear Analog and Switched-Capacitor State Variable Systems Using Continuous Checksums. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:582-591 [Conf ] Sheng-Jen Tsai Test Vector Generation for Linear Analog Devices. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:592-597 [Conf ] S. Wayne Bollinger , Scott F. Midkiff On Test Generation for Iddq Testing of Bridging Faults in CMOS Circuits. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:598-607 [Conf ] E. Vandris , Gerald E. Sobelman A Mixed Functional/IDDQ Testing Methodology for CMOS Transistor Faults. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:608-614 [Conf ] Chun-Hung Chen , Jacob A. Abraham High Quality Tests for Switch-Level Circuits Using Current and Logic Test Generation Algorithms. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:615-622 [Conf ] Robert C. Aitken Fault Location with Current Monitoring. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:623-632 [Conf ] Kenneth D. Wagner , Thomas W. Williams Enhancing Board Functional Self-Test by Concurrent Sampling. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:633-640 [Conf ] Partha Raghavachari Circuit Pack BIST from System to Factory - The MCERT Chip. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:641-648 [Conf ] Najmi T. Jarwala , Chi W. Yau Achieving Board-Level BIST Using the Boundary-Scan Master. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:649-658 [Conf ] Charles W. Buenzli Jr. , Robert Gonzalez A Case Study of Mixed Signal Fault Isolation: Knowledge Based vs. Decision Tree Programming. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:659-664 [Conf ] Sundarar Mohan , Pinaki Mazumder Fault Modeling and Testing of GaAs Static Random Access Memories. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:665-674 [Conf ] Manoj Franklin , Kewal K. Saluja An Algorithm to Test Rams for Physical Neighborhood Pattern Sensitive Faults. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:675-684 [Conf ] A. J. van de Goor , P. C. M. van der Arend , Gert-Jan Tromp Locating Bridging Faults in Memory Arrays. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:685-694 [Conf ] Prawat Nagvajara , Mark G. Karpovsky Built-In Self-Diagnostic Read-Only-Memories. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:695-703 [Conf ] Kiyoshi Furuya , Edward J. McCluskey Two-Pattern Test Capabilities of Autonomous TPG Circuits. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:704-711 [Conf ] Wen-Ben Jone Defect Level Estimation of Random and Pseudorandom Testing. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:712-721 [Conf ] Jacob Savir , Robert F. Berry At-Speed Test is not Necessarily an AC Test. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:722-728 [Conf ] Jaushin Lee , Janak H. Patel ARTEST: An Architectural Level Test Generator for Data Path Faults and Control Faults. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:729-738 [Conf ] M. Karam , Régis Leveugle , Gabriele Saucier Hierarchical Test Generation Based on Delayed Propagation. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:739-747 [Conf ] Brian T. Murray , John P. Hayes Test Propagation Through Modules and Circuits. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:748-757 [Conf ] Marius V. A. Hâncu , Kazuhiko Iwasaki , Yuji Sato , Mamoru Sugie A Concurrent Test Architecture for Massively-Parallel Computers and its Error Detection Capability. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:758-767 [Conf ] Dilip K. Bhavsar An Architecture for Extending the IEEE Standard 1149.1 Test Access Port to System Backplanes. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:768-776 [Conf ] Barry Baril , Dan Clayson , David McCracken , Stewart Taylor High Performance Pin Electronics Employing GaAs IC and Hybrid Circuit Packaging Technology. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:777-789 [Conf ] David C. Keezer Real-Time Data Comparison for GigaHertz Digital Test. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:790-797 [Conf ] Piero Franco , Edward J. McCluskey Delay Testing of Digital Circuits by Output Waveform Analysis. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:798-807 [Conf ] D. Lambidonis , André Ivanov , Vinod K. Agarwal Fast Signature Computation for Linear Compactors. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:808-817 [Conf ] Nirmal R. Saxena , Piero Franco , Edward J. McCluskey Refined Bounds on Signature Analysis Aliasing for Random Testing. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:818-827 [Conf ] Mark G. Karpovsky , Sandeep K. Gupta , Dhiraj K. Pradhan Aliasing and Diagnosis Probability in MISR and STUMPS Using a General Error Model. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:828-839 [Conf ] Vijay S. Iyengar , Gopalakrishnan Vijayan Test Application Timing: The Unexplored Issue in AC Test. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:840-847 [Conf ] Gopi Ganapathy , Jacob A. Abraham Hardware Acceleration Alone Will Not Make Fault Grading ULSI a Reality. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:848-857 [Conf ] Antonio Lioy Looking for Functional Fault Equivalence. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:858-863 [Conf ] Dick Chiles , John DeJaco Using Boundary Scan Description Language in Design. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:865-868 [Conf ] Lee Whetsel An IEEE 1149.1 Based Logic/Signature Analyzer in a Chip. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:869-878 [Conf ] W. C. Bruce , Michael G. Gallup , Grady Giles , Tom Munns Implementing 1149.1 on CMOS Microprocessors. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:879-886 [Conf ] Pranav Ashar , Srinivas Devadas , Kurt Keutzer Gate-Delay-Fault Testability Properties of Multiplexor-Based Networks. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:887-896 [Conf ] Eun Sei Park , Bill Underwood , Thomas W. Williams , M. Ray Mercer Delay Testing Quality in Timing-Optimized Designs. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:897-905 [Conf ] Kaushik De , Prithviraj Banerjee Logic Partitioning and Resynthesis for Testability. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:906-915 [Conf ] Mehdi Katoozi , Arnold Nordsiek Low Overhead Built-In Testable Error Detection and Correction with Excellent Fault Coverage. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:916-925 [Conf ] Lawrence P. Holmquist , Larry L. Kinney Concurrent Error Detection for Restricted Fault Sets in Sequential Circuits and Microprogrammed Control Units Using Convolutional Codes. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:926-935 [Conf ] X. Delord , Gabriele Saucier Formalizing Signature Analysis for Control Flow Checking of Pipelined RISC Multiprocessors. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:936-945 [Conf ] Hyung Ki Lee , Dong Sam Ha An Efficient, Forward Fault Simulation Algorithm Based on the Parallel Pattern Single Fault Propagation. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:946-955 [Conf ] Ken Kubiak , W. Kent Fuchs Multiple-Fault Simulation and Coverage of Deterministic Single-Fault Test Sets. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:956-962 [Conf ] Paul G. Ryan , Shishpal Rawat , W. Kent Fuchs Two-Stage Fault Location. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:963-968 [Conf ] Taiichi Otsuji A Picosecond Accuracy Timing Error Compensation Technique in TDR Measurement. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:969-975 [Conf ] Raymond J. Bulaga , Edward F. Westermann Maximizing and Maintaining AC Test Accuracy in the Manufacturing Environment. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:976-985 [Conf ] Eric Rosenfeld , Bradford Sumner DSP Calibration for Accurate Time Waveform Reconstruction. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:986-993 [Conf ] R. Wade Williams Integrating Emulation Techniques into General Purpose ATE. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:994-1003 [Conf ] Don Organ The enVisionTM Timing Resolver. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:1004-1008 [Conf ] Yehuda Shiran Distributed Layout Verification Using Sequential Software and Standard Hardware. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:1009-1015 [Conf ] Sungju Park , Sheldon B. Akers Parity Bit Calculation and Test Signal Compaction for BIST Applications. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:1016-1023 [Conf ] Subir Bandyopadhyay , Bhargab B. Bhattacharya On the Testable Design of Bilateral Bit-Level Systolic Arrays. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:1024-1033 [Conf ] Yutaka Tashiro , Hironori Yamauchi , Toshihiro Minami , Tetsuo Tajiri , Yutaka Suzuki An Organized Firmware Verification Environment for the Programmable Image DSP. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:1034-1041 [Conf ] Christopher J. Hannaford A Computer Architecture for High Pin Count Testers. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:1042-1048 [Conf ] Daniel A. Rosenthal A 20 Bit Waveform Source for a Mixed Signal Automatic Test System. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:1049-1054 [Conf ] Koji Karube , Yoshiyuki Bessho , Tokuo Takakura , Keita Gunji Advanced Mixed Signal Testing by DSP Localized Tester. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:1055-1060 [Conf ] M. Kanzaki , Masahiro Ishida Programming for Parallel Pattern Generators. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:1061-1068 [Conf ] S. P. Athan , David C. Keezer , J. McKinley High Frequency Wafer Probing and Power Supply Resonance Effects. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:1069-1078 [Conf ] Michael A. Perugini A Flexible Approach to Test Program Cross Compilers. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:1079-1086 [Conf ] Arthur E. Downey Industry Graphic Standards and ATE Windowing Software. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:1087-1095 [Conf ] Timothy J. Moore A Workstation Environment for Boundary Scan Interconnect Testing. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:1096-1103 [Conf ] Colin Maunder Languages to Support Boundary-Scan Test. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:1104- [Conf ] Carol Pyron Representing Boundary Scan Tests with the EDIF Test View. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:1105- [Conf ] Ted W. Gary Software Testing, the State of the Practice. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:1106- [Conf ] Edward F. Miller Software Testing - The State of the Practice. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:1107- [Conf ] A. Jefferson Offutt Unit Testing Versus Integration Testing. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:1108-1109 [Conf ] Paul D. Roddy Software Testing. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:1110- [Conf ] Tushar Gheewala For Test Automation, Silicon is Free. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:1111- [Conf ] Charles E. Stroud Distractions in Design for Testability and Built-Is Self-Test. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:1112- [Conf ] Daniel J. Burns Military Burn-In Requirements - One Perspective. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:1113- [Conf ] Noel E. Donlin Is Burn-In Burned Out? [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:1114-1115 [Conf ] Charles C. Packard Is Burn-In Burned Out? [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:1116- [Conf ] Richard Absher Can Undergraduate Test Engineering Education Be "Faster, Better, Sooner?". [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:1117- [Conf ] Charles F. Hawkins , Richard H. Williams EE Curriculum - Continuous Process Improvement? [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:1118- [Conf ] Wojciech Maly Improving the Quality of Test Education. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:1119- [Conf ] Peter C. Maxwell The Interaction of Test and Quality. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:1120- [Conf ] Kenneth Rose Quality in Test Education? [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:1121- [Conf ] Thomas M. Storey , Wojciech Maly CMOS Bridging Fault Detection. [Citation Graph (0, 0)][DBLP ] ITC, 1990, pp:1123-1132 [Conf ]