Conferences in DBLP
Prabhakar Kudva , Andrew Sullivan , William E. Dougherty Metrics for Structural Logic Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Fan Mo , Robert K. Brayton Regular Fabrics in Deep Sub-Micron Integrated-Circuit Design. [Citation Graph (0, 0)][DBLP ] Conf ] Subarnarekha Sinha , Alan Mishchenko , Robert K. Brayton Topologically Constrained Logic Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Anas Al-Rabadi , Lee W. Casperson Optical Realizations of Reversible Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Theodore W. Manikas , Gerald R. Kane Partitioning Effects on Estimated Wire Length for Mixed Macro and Standard Cell Placement. [Citation Graph (0, 0)][DBLP ] Conf ] Pawel Kerntopf An Approach to Designing Complex Reversible Logic Gates. [Citation Graph (0, 0)][DBLP ] Conf ] Mohamed A. Elgamel , Magdy A. Bayoumi On Low Power High Level Synthesis Using Genetic Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Hua Tang , Alex Doboli Layout-Aware Synthesis Methodology for Analog Systems Based on Combined Block Sizing, Floorplanning and Global Routing. [Citation Graph (0, 0)][DBLP ] Conf ] Nina Yevtushenko , Tiziano Villa , Robert K. Brayton , Alexandre Petrenko , Alberto L. Sangiovanni-Vincentelli Equisolvability of Series vs. Controller's Topology in Synchronous Language Equations. [Citation Graph (0, 0)][DBLP ] Conf ] Tomas Bengtsson , Andrés Martinelli , Elena Dubrova A Fast Heuristic Algorithm for Disjunctive. [Citation Graph (0, 0)][DBLP ] Conf ] Nattawut Thepayasuwan , Alex Doboli A Methodology for Core Placement and Bus Synthesis under Time, Area and Energy Consumption Constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Yen-Jen Chang , Feipei Lai , Shanq-Jang Ruan An Efficient Two-Level Filter Scheme for Low Power Cache. [Citation Graph (0, 0)][DBLP ] Conf ] Svetlana N. Yanushkevich , Vlad P. Shmerko , V. D. Malyugin , Piotr Dziurzanski Linearity of World-Level Circuit Models: New Understanding. [Citation Graph (0, 0)][DBLP ] Conf ] Jorgiano Vidal , David Déharbe , Dominique Borrione Improving Static Ordering of BDDs for Reachability Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Mukul R. Prasad , Michael S. Hsiao , Jawahar Jain Improving Sequential ATPG Using SAT Methods. [Citation Graph (0, 0)][DBLP ] Conf ] Pawel Kerntopf Nonlinear Sifting of Decision Diagrams. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Joey Y. Lin , Wangning Long Enhanced SPFD Rewiring on Improving Rewiring Ability. [Citation Graph (0, 0)][DBLP ] Conf ] Amit Prakash , Ramakrishna Kotla , Tanmoy Mandal , Adnan Aziz A Reconfigurable Architecture and Associated Synthesis Methodology for High Speed Packet Classification. [Citation Graph (0, 0)][DBLP ] Conf ] Yoshihisa Kojima , Hiroshi Saito , Kenshu Seto , Satoshi Komatsu , Masahiro Fujita Field Modifiable Architecture and its Design Methodology: System Design Without Logic Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Silviu M. S. A. Chiricescu , Michael A. Schuette , Herman Schmit , Robin Glinton Synthesis of Morphable Multipliers. [Citation Graph (0, 0)][DBLP ] Conf ] Alan Mishchenko , Tsutomu Sasao Encoding of Boolean Functions and its Application to LUT Cascade Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Petra Färm , Elena Dubrova Technology Mapping for Chemically Assembled Electronic Nanotechnology. [Citation Graph (0, 0)][DBLP ] Conf ] Vivek V. Shende , Aditya K. Prasad , Igor L. Markov , John P. Hayes Reversible Logic Circuit Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Fadi A. Aloul , Maher N. Mneimneh , Karem A. Sakallah ZBDD-Based Backtrack Search SAT Solver. [Citation Graph (0, 0)][DBLP ] Conf ] Fadi A. Aloul , Igor L. Markov , Karem A. Sakallah Efficient Gate and Input Ordering for Circuit-to-BDD Conversion. [Citation Graph (0, 0)][DBLP ] Conf ] Mikael Kerttu , Per Lindgren , Rolf Drechsler , Mitchell A. Thornton Low Power Optimization Techniques for BDD Mapped Finite State Machines. [Citation Graph (0, 0)][DBLP ] Conf ] Chia-Chih Yen , Kuang-Chien Chen , Jing-Yang Jou A Practical Approach to Cycle Bound Estimation for Property Checking. [Citation Graph (0, 0)][DBLP ] Conf ] Agnes Madalinski , Alexandre V. Bystrov , Alexandre Yakovlev Visualization of Coding Conflicts in Asynchronous Circuit Design. [Citation Graph (0, 0)][DBLP ] Conf ] S. G. Gibb , Laurence E. Turner The Automatic Generation of Application Specific Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Loïc Lagadec , Bernard Pottier , Oscar Villellas , Erwan Fabiani , Catherine Dezan A LUT based Approach for High Level Synthesis on FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Alan Mishchenko , Robert K. Brayton A Boolean Paradigm in Multi-Valued Logic Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Leyla Nazhandali , Karem A. Sakallah Majority-Based Decomposition of Carry Logic in Binary Adders. [Citation Graph (0, 0)][DBLP ] Conf ] Jun Yuan , Ken Albin , Adnan Aziz , Carl Pixley Simplifying Constraint Solving in Random Simulation Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Anh Vu Dihn Duc , Laurent Fesquet , Marc Renaudin Synthesis of QDI Asynchronous Circuits from DTL-Style Petri-Net. [Citation Graph (0, 0)][DBLP ] Conf ] Alan Mishchenko , Marek A. Perkowski Logic Synthesis of Reversible Wave Cascades. [Citation Graph (0, 0)][DBLP ] Conf ] Hui-Yuan Song , R. Iris Bahar , Joel Grodstein Timing Analysis for Full-Custom Circuits Using Symbolic DC Formulations. [Citation Graph (0, 0)][DBLP ] Conf ] Rupesh S. Shelar , Sachin S. Sapatnekar Efficient Layout Synthesis Algorithm for Pass Transistor Logic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Xinning Wang , Prashant Sawkar , Barbara A. Chappell A Constructive Matching Algorithm for Library-Based Domino Technology Mapping. [Citation Graph (0, 0)][DBLP ] Conf ] Federico Politi Recognition of Transistor Level Complex Sequential and Dynamic Circuits using State Based BDD's. [Citation Graph (0, 0)][DBLP ] Conf ] Cliff C. N. Sze , Ting-Chi Wang Multi-Level Circuit Clustering for Delay Minimization. [Citation Graph (0, 0)][DBLP ] Conf ] Jordi Cortadella Bi-Decomposition and Tree-Height Reduction for Timing Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Alexandre V. Bystrov , Alexandre Yakovlev Synthesis of Asynchronous Circuits with Predictable Latency. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroshi Saito , Hiroshi Nakamura , Masahiro Fujita , Takashi Nanya Logic Optimization for Asynchronous SI Controllers using Transduction Method. [Citation Graph (0, 0)][DBLP ] Conf ] Whitney J. Townsend , Mitchell A. Thornton , Parag K. Lala On-line Error Detection in a Carry-free Adder. [Citation Graph (0, 0)][DBLP ] Conf ] Amit Tandon , Federico Politi Model Generation and Gate Level Abstraction of Complex CMOS Custom Design for Functional and DFT Validation. [Citation Graph (0, 0)][DBLP ] Conf ] Andrei B. Khlopotine , Marek A. Perkowski , Pawel Kerntopf Reversible Logic Synthesis by Iterative Compositions. [Citation Graph (0, 0)][DBLP ] Conf ] Ankur Srivastava , Majid Sarrafzadeh Predictability: Definition, Analysis and Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Anas Al-Rabadi Symmetry as a Base for a New Decomposition of Boolean Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Masayuki Tsukisaka , Masashi Imai , Takashi Nanya High Throughput Asynchronous Domino Using Dual output Buffer. [Citation Graph (0, 0)][DBLP ] Conf ] Masanori Hashimoto , Yashiteru Hayashi , Hidetoshi Onodera Experimental Study on Cell-Base High-Performance Datapath Design. [Citation Graph (0, 0)][DBLP ] Conf ] Geun Rae Cho , Tom Chen On the Impact of Fanout Optimization and Redundant Buffer Removal for Mixed PTL Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Chang Woo Kang , Massoud Pedram Technology Mapping for Low Leakage Power with Hot-Carrier Effect Consideration. [Citation Graph (0, 0)][DBLP ] Conf ] Jie-Hong Roland Jiang , Robert K. Brayton On the Verification of Sequential Equivalence. [Citation Graph (0, 0)][DBLP ] Conf ] Farzan Fallah Binary Time Frame Expansion. [Citation Graph (0, 0)][DBLP ] Conf ] René Krenz , Elena Dubrova , Andreas Kuehlmann Circuit-Based Evaluation of the Arithmetic Transform of Boolean Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Yunjian Jiang , Robert K. Brayton Don't Care Computation in Minimizing Extended Finite State Machines with Presburger Arithmetic. [Citation Graph (0, 0)][DBLP ] Conf ] Alan Mishchenko , Robert K. Brayton Simplification of Non-Deterministic Multi-Valued Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Jie-Hong Roland Jiang , Alan Mishchenko , Robert K. Brayton Reducing Multi-Valued Algebraic Operations to Binary. [Citation Graph (0, 0)][DBLP ] Conf ] Anna Bernasconi , Valentina Ciriani , Fabrizio Luccio , Linda Pagli Implicit Test of Regularity for Not Completely Specified Boolean Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Jun Yuan , Kurt Shultz , John Havlicek , Ken Albin , Adnan Aziz A Method for Synthesizing Boolean Constrains. [Citation Graph (0, 0)][DBLP ] Conf ] Tiberiu Chelcea , Steven M. Nowick Resynthesis and Peephole Transformations for the Optimization of Large-Scale Asynchronous Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Felipe R. Schneider , Vinícius P. Correia , Renato P. Ribas , André Inácio Reis Comparing Transistor-Level Implementations of 4-Input Logic Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Rajeev Murgai Net Buffering in the Presence of Multiple Timing Views. [Citation Graph (0, 0)][DBLP ] Conf ] DoRon B. Motter , Igor L. Markov Overcoming Resolution-Based Lower Bounds for SAT Solvers. [Citation Graph (0, 0)][DBLP ] Conf ] Tsutomu Sasao , Yukihiro Iguchi , Munehiro Matsuura Comparison of Decision Diagrams for Multiple-Output Logic Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Christoph Meinel , Harald Sack , Volker Schillings VisBDD - A Web-based Visualization Framework for OBDD Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Christoph Meinel , Christian Stangier Modular Partitioning and Dynamic Conjunction Scheduling in Image Computation. [Citation Graph (0, 0)][DBLP ] Conf ] Jaijeet S. Roychowdhury Optical Systems 101 for EDA Practitioners. [Citation Graph (0, 0)][DBLP ] Conf ] Steven P. Levitan Giga = 1/Nano: CAD Tools and Modeling Challenges for Giga-Scale Mixed Technology Micro-Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen A. Edwards High-Level Synthesis from the Synchronous Language Esterel. [Citation Graph (0, 0)][DBLP ] Conf ] Nick Savoiu , Sandeep K. Shukla , Rajesh K. Gupta Concurrency in System Level Design: Conflict Between Simulation and Synthesis Goals. [Citation Graph (0, 0)][DBLP ] Conf ] Miodrag Vujkovic , Carl Sechen Optimized Power-Delay Curve Generation for Standard Cell ICs. [Citation Graph (0, 0)][DBLP ] Conf ] Afshin Abdollahi , Farzan Fallah Runtime Mechanisms for Leakage Current Reduction in CMOS VLSI Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] 