Conferences in DBLP
Program Committee. [Citation Graph (0, 0)][DBLP ] Conf ] Message from the Chairs. [Citation Graph (0, 0)][DBLP ] Conf ] Russell Klein SoC Integration Challenges. [Citation Graph (0, 0)][DBLP ] Conf ] James Paris Integrating a Single Physical Verification Tool for Systems-on-Chip Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Vishy Lakshmanan Automated Fixing of Complex/Process Critical DRC Violations in Place and Route Systems Using Calibre in the Synopsys/Milkyway Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Krzysztof Iniewski , Shahriar Mirabbasi High-Speed I/Os and PLLs for Data Communication Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Ashraf Salem Formal Verification of Digital Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Brian Marshall Beyond P-Cell and Gate-Level: Accuracy Requirements for Simulation of Nanometer SoC Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Minghua Shi , Amine Bermak , Sofiane Brahim-Belhouari A Real-time Architecture of SOC Selective Gas Sensor Array Using KNN Based on the Dynamic Slope and the Steady State Response. [Citation Graph (0, 0)][DBLP ] Conf ] Yat-Fong Yung , Amine Bermak A Digital CMOS Imager with Pixel Level Analog-to-digital Converter and Reconfigurable SRAM/Counter. [Citation Graph (0, 0)][DBLP ] Conf ] Alexandre Chureau , Yvon Savaria , El Mostapha Aboulhamid Interface-based Design of Systems-on-Chip using UML-RT. [Citation Graph (0, 0)][DBLP ] Conf ] Luc Charest , El Mostapha Aboulhamid , Guy Bois Using Design Patterns for Type Unification and Introspection in SystemC. [Citation Graph (0, 0)][DBLP ] Conf ] L.-P. Lafrance , Yvon Savaria A Framework for Implementing Reusable Digital Signal Processing Modules. [Citation Graph (0, 0)][DBLP ] Conf ] Samy Meftali , Jean-Luc Dekeyser An Optimal Charge Balancing Model for Fast Distributed SystemC Simulation in IP/SoC Design. [Citation Graph (0, 0)][DBLP ] Conf ] Wenjing Zhang , Graham A. Jullien , Vassil S. Dimitrov A Programmable Base MDLNS MAC with Self-Generated Look-Up Table. [Citation Graph (0, 0)][DBLP ] Conf ] Kuo-Hsing Cheng , Shun-Wen Cheng , Chan-Wei Huang 64-bit Hybrid Dual-Threshold Voltage Power-Aware Conditional Carry Adder Design. [Citation Graph (0, 0)][DBLP ] Conf ] Attif A. Ibrahem , Hamed Elsimary , Aly E. Salama FPGA Implementation of Fast Radix 4 Division Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Wei Wang , M. N. S. Swamy , M. Omair Ahmad RNS Application for Digital Image Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Bijan Alizadeh , Zainalabedin Navabi Using Integer Equations to Check PSL Properties in RT Level Design. [Citation Graph (0, 0)][DBLP ] Conf ] S. Regimbal , Yvon Savaria , Guy Bois Verification Strategy Determination Using Dependence Analysis of Transaction-Level Models. [Citation Graph (0, 0)][DBLP ] Conf ] D. Morin , F. Normandin , M.-E. Grandmaison , H. Dang , Yvon Savaria , Mohamad Sawan An Intellectual Property Module for Auto-Calibration of Time-Interleaved Pipelined Analog-to-Digital Converters. [Citation Graph (0, 0)][DBLP ] Conf ] Hung Tien Bui , Yvon Savaria 10 GHz PLL Using Active Shunt-Peaked MCML Gates and Improved Frequency Acquisition XOR Phase Detector in 0.18 µm CMOS. [Citation Graph (0, 0)][DBLP ] Conf ] R. Chebli , Mohamad Sawan A CMOS High-Voltage DC-DC Up Converter Dedicated for Ultrasonic Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Masud H. Chowdhury , Yehea I. Ismail Possible Noise Failure Modes in Static and Dynamic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Donghoon Han , Abhijit Chatterjee Simulation-in-the-Loop Analog Circuit Sizing Method using Adaptive Model-based Simulated Annealing. [Citation Graph (0, 0)][DBLP ] Conf ] Y. Ibrahim , Graham A. Jullien , William C. Miller Ultra Low Noise Signed Digit Arithmetic using Cellular Neural Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Deng Lei , Wen Gao , Ming-Zeng Hu , Zhenzhou Ji An Efficient VLSI Implementation of MC Interpolation for MPEG-4. [Citation Graph (0, 0)][DBLP ] Conf ] Ling-zhi Liu , Lin Qiu , Meng-tian Rong , Jiang Li A 2-D Forward/Inverse Integer Transform Processor of H.264 Based on Highly-parallel Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Victor H. S. Ha , Sung Kyu Choi , Jong-Gu Jeon , Geon Hyoung Lee , Won-Kap Jang , Woo-Sung Shim Real-time Audio/Video Decoders for Digital Multimedia Broadcasting. [Citation Graph (0, 0)][DBLP ] Conf ] Hongkyu Kim , D. Scott Wills , Linda M. Wills Empirical Analysis of Operand Usage and Transport in Multimedia Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Yung-Chi Chang , Chih-Wei Hsu , Liang-Gee Chen MPEG-4 FGS Encoder Design for an Interactive Content-aware MPEG-4 Video Streaming SOC. [Citation Graph (0, 0)][DBLP ] Conf ] Sherif G. Aly , Ashraf M. Salem Observability-Based RTL Simulation using JAVA. [Citation Graph (0, 0)][DBLP ] Conf ] Jean-Pierre David , Etienne Bergeron A Step towards Intelligent Translation from High-Level Design to RTL. [Citation Graph (0, 0)][DBLP ] Conf ] M. Watheq El-Kharashi , M. H. El-Malaki , S. Hammad , Ashraf Salem , A. Wahdan Towards Automating Hardware/Software Co-Design. [Citation Graph (0, 0)][DBLP ] Conf ] Ashwin K. Kumaraswamy , Ahmet T. Erdogan , Indrajit Atluri Development of Timing Driven IP Design Flow based on Physical Knowledge Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Milan Pastrnak , Peter Poplavko , Peter H. N. de With , Dirk Farin Data-flow Timing Models of Dynamic Multimedia Applications for Multiprocessor Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Krzysztof Iniewski , Valery Axelrad , Andrei Shibkov , Artur Balasinski , Marek Syrzycki Design Strategies for ESD Protection in SOC. [Citation Graph (0, 0)][DBLP ] Conf ] Mikael Olausson , Anders Edman , Dake Liu Bit Memory Instructions for a General CPU. [Citation Graph (0, 0)][DBLP ] Conf ] Keh-Jeng Chang Accurate On-Chip Variation Modeling to Achieve Design for Manufacturability. [Citation Graph (0, 0)][DBLP ] Conf ] K. Ola Andersson , Mark Vesterbacka A Parameterized Cell-Based Design Approach for Digital-to-Analog Converters. [Citation Graph (0, 0)][DBLP ] Conf ] Erik Sall , Mark Vesterbacka Design of a Comparator in CMOS SOI. [Citation Graph (0, 0)][DBLP ] Conf ] Iman Y. Taha , Majid Ahmadi , William C. Miller A Sigma-Delta Modulator for Digital Hearing Instruments Using 0.18µm CMOS Technology. [Citation Graph (0, 0)][DBLP ] Conf ] Sherif Hammouda , Mohamed Dessouky , Mohamed Tawfik , Wael M. Badawy A Fully Automated Approach for Analog Circuit Reuse. [Citation Graph (0, 0)][DBLP ] Conf ] Mountassar Maamoun , Boualem Laichi , Abdelhalim Benbelkacem , Daoud Berkani Interfacing in Microprocessor-based Systems with an Advanced Physical Addressing. [Citation Graph (0, 0)][DBLP ] Conf ] Krzysztof Iniewski , R. Badalone , M. Lapointe , Marek Syrzycki SERDES Technology for Gigabit I/O Communications in Storage Area Networking. [Citation Graph (0, 0)][DBLP ] Conf ] Tina Lindkvist , Jacob Löfvenberg , Henrik Ohlsson , Kenny Johansson , Lars Wanhammar A Power-Efficient, Low-Complexity, Memoryless Coding Scheme for Buses with Dominating Inter-Wire Capacitances. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Wiklund , Sumant Sathe , Dake Liu Network on Chip Simulations for Benchmarking. [Citation Graph (0, 0)][DBLP ] Conf ] Jacob Löfvenberg Non-Redundant Coding for Deep Sub-Micron Address Buses. [Citation Graph (0, 0)][DBLP ] Conf ] Azeddien M. Sllame A Model for a Reusable System-on-a-Chip Hardware Component Integrated with Design Exploration Methodology. [Citation Graph (0, 0)][DBLP ] Conf ] Xizhi Li , Tiecai Li ECOMIPS: An Economic MIPS CPU Design on FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] S. A. Rahim , Laurence E. Turner A Field Programmable Bit-Serial Digital Signal Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Pascal Nsame , Yvon Savaria A Customizable Embedded SoC Platform Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Holly Pekau , Joshua K. Nakaska , Jim Kulyk , Grant McGibney , James W. Haslett SOC Design of an IF Subsampling Terminal for a Gigabit Wireless LAN with Asymmetric Equalization. [Citation Graph (0, 0)][DBLP ] Conf ] Richard F. Hobson , Allan R. Dyck , Keith Cheung SoC Features for a Multi-Processor WCDMA Base-station Modem. [Citation Graph (0, 0)][DBLP ] Conf ] 