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Conferences in DBLP

International Workshop System-on-Chip for Real-Time Applications (iwsoc)
2004 (conf/iwsoc/2004)


  1. Program Committee. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:- [Conf]

  2. Message from the Chairs. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:- [Conf]
  3. Russell Klein
    SoC Integration Challenges. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:3- [Conf]
  4. James Paris
    Integrating a Single Physical Verification Tool for Systems-on-Chip Designs. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:7- [Conf]
  5. Vishy Lakshmanan
    Automated Fixing of Complex/Process Critical DRC Violations in Place and Route Systems Using Calibre in the Synopsys/Milkyway Environment. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:7- [Conf]
  6. Krzysztof Iniewski, Shahriar Mirabbasi
    High-Speed I/Os and PLLs for Data Communication Applications. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:11-12 [Conf]
  7. Ashraf Salem
    Formal Verification of Digital Circuits. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:15- [Conf]
  8. Brian Marshall
    Beyond P-Cell and Gate-Level: Accuracy Requirements for Simulation of Nanometer SoC Designs. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:23-26 [Conf]
  9. Minghua Shi, Amine Bermak, Sofiane Brahim-Belhouari
    A Real-time Architecture of SOC Selective Gas Sensor Array Using KNN Based on the Dynamic Slope and the Steady State Response. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:29-32 [Conf]
  10. Yat-Fong Yung, Amine Bermak
    A Digital CMOS Imager with Pixel Level Analog-to-digital Converter and Reconfigurable SRAM/Counter. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:33-36 [Conf]
  11. Alexandre Chureau, Yvon Savaria, El Mostapha Aboulhamid
    Interface-based Design of Systems-on-Chip using UML-RT. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:39-44 [Conf]
  12. Luc Charest, El Mostapha Aboulhamid, Guy Bois
    Using Design Patterns for Type Unification and Introspection in SystemC. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:45-50 [Conf]
  13. L.-P. Lafrance, Yvon Savaria
    A Framework for Implementing Reusable Digital Signal Processing Modules. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:51-54 [Conf]
  14. Samy Meftali, Jean-Luc Dekeyser
    An Optimal Charge Balancing Model for Fast Distributed SystemC Simulation in IP/SoC Design. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:55-58 [Conf]
  15. Wenjing Zhang, Graham A. Jullien, Vassil S. Dimitrov
    A Programmable Base MDLNS MAC with Self-Generated Look-Up Table. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:61-64 [Conf]
  16. Kuo-Hsing Cheng, Shun-Wen Cheng, Chan-Wei Huang
    64-bit Hybrid Dual-Threshold Voltage Power-Aware Conditional Carry Adder Design. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:65-68 [Conf]
  17. Attif A. Ibrahem, Hamed Elsimary, Aly E. Salama
    FPGA Implementation of Fast Radix 4 Division Algorithm. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:69-72 [Conf]
  18. Wei Wang, M. N. S. Swamy, M. Omair Ahmad
    RNS Application for Digital Image Processing. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:77-80 [Conf]
  19. Bijan Alizadeh, Zainalabedin Navabi
    Using Integer Equations to Check PSL Properties in RT Level Design. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:83-86 [Conf]
  20. S. Regimbal, Yvon Savaria, Guy Bois
    Verification Strategy Determination Using Dependence Analysis of Transaction-Level Models. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:87-92 [Conf]
  21. D. Morin, F. Normandin, M.-E. Grandmaison, H. Dang, Yvon Savaria, Mohamad Sawan
    An Intellectual Property Module for Auto-Calibration of Time-Interleaved Pipelined Analog-to-Digital Converters. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:111-114 [Conf]
  22. Hung Tien Bui, Yvon Savaria
    10 GHz PLL Using Active Shunt-Peaked MCML Gates and Improved Frequency Acquisition XOR Phase Detector in 0.18 µm CMOS. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:115-118 [Conf]
  23. R. Chebli, Mohamad Sawan
    A CMOS High-Voltage DC-DC Up Converter Dedicated for Ultrasonic Applications. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:119-122 [Conf]
  24. Masud H. Chowdhury, Yehea I. Ismail
    Possible Noise Failure Modes in Static and Dynamic Circuits. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:123-126 [Conf]
  25. Donghoon Han, Abhijit Chatterjee
    Simulation-in-the-Loop Analog Circuit Sizing Method using Adaptive Model-based Simulated Annealing. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:127-130 [Conf]
  26. Y. Ibrahim, Graham A. Jullien, William C. Miller
    Ultra Low Noise Signed Digit Arithmetic using Cellular Neural Networks. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:136-142 [Conf]
  27. Deng Lei, Wen Gao, Ming-Zeng Hu, Zhenzhou Ji
    An Efficient VLSI Implementation of MC Interpolation for MPEG-4. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:149-152 [Conf]
  28. Ling-zhi Liu, Lin Qiu, Meng-tian Rong, Jiang Li
    A 2-D Forward/Inverse Integer Transform Processor of H.264 Based on Highly-parallel Architecture. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:158-161 [Conf]
  29. Victor H. S. Ha, Sung Kyu Choi, Jong-Gu Jeon, Geon Hyoung Lee, Won-Kap Jang, Woo-Sung Shim
    Real-time Audio/Video Decoders for Digital Multimedia Broadcasting. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:162-167 [Conf]
  30. Hongkyu Kim, D. Scott Wills, Linda M. Wills
    Empirical Analysis of Operand Usage and Transport in Multimedia Applications. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:168-171 [Conf]
  31. Yung-Chi Chang, Chih-Wei Hsu, Liang-Gee Chen
    MPEG-4 FGS Encoder Design for an Interactive Content-aware MPEG-4 Video Streaming SOC. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:172-175 [Conf]
  32. Sherif G. Aly, Ashraf M. Salem
    Observability-Based RTL Simulation using JAVA. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:179-182 [Conf]
  33. Jean-Pierre David, Etienne Bergeron
    A Step towards Intelligent Translation from High-Level Design to RTL. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:183-188 [Conf]
  34. M. Watheq El-Kharashi, M. H. El-Malaki, S. Hammad, Ashraf Salem, A. Wahdan
    Towards Automating Hardware/Software Co-Design. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:189-192 [Conf]
  35. Ashwin K. Kumaraswamy, Ahmet T. Erdogan, Indrajit Atluri
    Development of Timing Driven IP Design Flow based on Physical Knowledge Synthesis. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:193-197 [Conf]
  36. Milan Pastrnak, Peter Poplavko, Peter H. N. de With, Dirk Farin
    Data-flow Timing Models of Dynamic Multimedia Applications for Multiprocessor Systems. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:206-209 [Conf]
  37. Krzysztof Iniewski, Valery Axelrad, Andrei Shibkov, Artur Balasinski, Marek Syrzycki
    Design Strategies for ESD Protection in SOC. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:210-214 [Conf]
  38. Mikael Olausson, Anders Edman, Dake Liu
    Bit Memory Instructions for a General CPU. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:215-218 [Conf]
  39. Keh-Jeng Chang
    Accurate On-Chip Variation Modeling to Achieve Design for Manufacturability. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:219-222 [Conf]
  40. K. Ola Andersson, Mark Vesterbacka
    A Parameterized Cell-Based Design Approach for Digital-to-Analog Converters. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:225-228 [Conf]
  41. Erik Sall, Mark Vesterbacka
    Design of a Comparator in CMOS SOI. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:229-232 [Conf]
  42. Iman Y. Taha, Majid Ahmadi, William C. Miller
    A Sigma-Delta Modulator for Digital Hearing Instruments Using 0.18µm CMOS Technology. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:233-236 [Conf]
  43. Sherif Hammouda, Mohamed Dessouky, Mohamed Tawfik, Wael M. Badawy
    A Fully Automated Approach for Analog Circuit Reuse. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:237-240 [Conf]
  44. Mountassar Maamoun, Boualem Laichi, Abdelhalim Benbelkacem, Daoud Berkani
    Interfacing in Microprocessor-based Systems with an Advanced Physical Addressing. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:243-246 [Conf]
  45. Krzysztof Iniewski, R. Badalone, M. Lapointe, Marek Syrzycki
    SERDES Technology for Gigabit I/O Communications in Storage Area Networking. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:247-252 [Conf]
  46. Tina Lindkvist, Jacob Löfvenberg, Henrik Ohlsson, Kenny Johansson, Lars Wanhammar
    A Power-Efficient, Low-Complexity, Memoryless Coding Scheme for Buses with Dominating Inter-Wire Capacitances. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:257-262 [Conf]
  47. Daniel Wiklund, Sumant Sathe, Dake Liu
    Network on Chip Simulations for Benchmarking. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:269-274 [Conf]
  48. Jacob Löfvenberg
    Non-Redundant Coding for Deep Sub-Micron Address Buses. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:275-279 [Conf]
  49. Azeddien M. Sllame
    A Model for a Reusable System-on-a-Chip Hardware Component Integrated with Design Exploration Methodology. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:287-290 [Conf]
  50. Xizhi Li, Tiecai Li
    ECOMIPS: An Economic MIPS CPU Design on FPGA. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:291-294 [Conf]
  51. S. A. Rahim, Laurence E. Turner
    A Field Programmable Bit-Serial Digital Signal Processor. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:295-298 [Conf]
  52. Pascal Nsame, Yvon Savaria
    A Customizable Embedded SoC Platform Architecture. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:299-304 [Conf]
  53. Holly Pekau, Joshua K. Nakaska, Jim Kulyk, Grant McGibney, James W. Haslett
    SOC Design of an IF Subsampling Terminal for a Gigabit Wireless LAN with Asymmetric Equalization. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:307-313 [Conf]
  54. Richard F. Hobson, Allan R. Dyck, Keith Cheung
    SoC Features for a Multi-Processor WCDMA Base-station Modem. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:318-321 [Conf]
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NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
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