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Conferences in DBLP

International Workshop System-on-Chip for Real-Time Applications (iwsoc)
2003 (conf/iwsoc/2003)


  1. Program Committee. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:- [Conf]

  2. Message from the General Chairs. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:- [Conf]
  3. Yuanqing Guo, Gerard J. M. Smit, Hajo Broersma, Paul M. Heysters
    Template Generation and Selection Algorithms. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:2-6 [Conf]
  4. Sérgio G. Araújo, Antônio C. Mesquita, Aloysio Pedroza
    Optimized Datapath Design by Evolutionary Computation. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:6-9 [Conf]
  5. Matthias Grünewald, Jörg-Christian Niemann, Ulrich Rückert
    A performance evaluation method for optimizing embedded applications. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:10-15 [Conf]
  6. Kuo-Hsing Cheng, Wei-Chun Chang, Chia Ming Tu
    A Robust Handshake for Asynchronous System. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:16-19 [Conf]
  7. Bill Halpin, Naresh Sehgal, C. Y. Roger Chen
    Detailed Placement with Net Length Constraints. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:22-27 [Conf]
  8. Laleh Behjat, Anthony Vannelli
    Steiner Tree Construction Based on Congestion for the Global Routing Problem. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:28-31 [Conf]
  9. Dorothy Kucar, Anthony Vannelli
    InterconnectionModelling Using Distributed RLC Models. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:32-35 [Conf]
  10. Patricia Guitton-Ouhamou, Cécile Belleudy, Michel Auguin
    Energy Optimization in a HW/SW Tool: Design of Low. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:38-43 [Conf]
  11. Kugan Vivekanandarajah, Thambipillai Srikanthan, Saurav Bhattacharyya, Prasanna Venkatesh Kannan
    Incorporating Pattern Prediction Technique for Energy Efficient Filter Cache Design. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:44-47 [Conf]
  12. Li-Chuan Weng, Xiaojun Wang, Bin Liu
    A Survey of Dynamic Power Optimization Techniques. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:48-52 [Conf]
  13. T. W. Fox, A. Carreira, L. E. Turner
    The Design of Low-Power Fixed-Point FIR Differentiator IP Blocks. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:53-58 [Conf]
  14. Amr T. Abdel-Hamid, Sofiène Tahar, El Mostapha Aboulhamid
    IP Watermarking Techniques: Survey and Comparison. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:60-65 [Conf]
  15. Minyi Fu, Graham A. Jullien, Vassil S. Dimitrov, Majid Ahmadi, William C. Miller
    The Application of 2D Algebraic Integer Encoding to a DCT IP Core. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:66-69 [Conf]
  16. Boris D. Andreev, Edward L. Titlebaum, Eby G. Friedman
    Transformations of Signed-Binary Number Representations for Efficient VLSI Arithmetic. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:70-75 [Conf]
  17. Nitish Patel, George Coghill, Sing Kiong Nguang
    Digital Realization of Analogue Computing Elements Using Bit Streams. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:76-80 [Conf]
  18. S. M. Rezaul Hasan
    A High Performance Wide-band CMOS Transimpedance Amplifier for Optical Transceivers. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:82-85 [Conf]
  19. Jhy-Neng Yang, Yi-Chang Cheng, Chen-Yi Lee
    A Design of CMOS Broadband Amplifier With High-Q Active Inductor. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:86-89 [Conf]
  20. Kuo-Hsing Cheng, Yu-lung Lo, Wen Fang Yu, Shu-Yin Hung
    A Mixed-Mode Delay-Locked Loop for Wide-Range Operation and Multiphase Clock Generation. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:90-93 [Conf]
  21. Sau-Mou Wu, Ron-Yi Liu, Wei-Liang Chen
    A 5.8-GHz High Efficient, Low Power, Low Phase Noise CMOS VCO for IEEE 802.11a. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:94-97 [Conf]
  22. Stephen Machan
    A Low-Power Fully Differential 2.4-GHz Prescaler in 0.18µm CMOS Technology. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:98-100 [Conf]
  23. Peter Waldeck, Neil W. Bergmann
    Dynamic Hardware-Software Partitioning on Reconfigurable System-on-Chip. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:102-105 [Conf]
  24. Philippe Brunet, Camel Tanougast, Yves Berviller, Serge Weber
    Hardware Partitioning Software for Dynamically Reconfigurable SoC Design. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:106-111 [Conf]
  25. Neil W. Bergmann, Peter Waldeck, John A. Williams
    A Catalog of Hardware Acceleration Techniques for Real-Time Reconfigurable System on Chip. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:112-115 [Conf]
  26. Magesh Sadasivam, Sangjin Hong
    Application Specific Coarse-Grained FPGA for Processing Element in Real-Time Parallel Particle Filters. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:116-119 [Conf]
  27. Costantino Giaconia, Antonio Di Stefano, Giuseppe Capponi
    Reconfigurable Digital Instrumentation Based on FPGA. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:120-122 [Conf]
  28. H. Emam, M. A. Ashour, H. Fekry, A. M. Wahdan
    Introducing an FPGA based - genetic algorithms in the applications of blind signals separation. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:123-127 [Conf]
  29. Shih-Chang Hsia
    A High Speed Multi -Input Comparator with Clocking-Charge Based for Low-Power Systems. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:130-133 [Conf]
  30. Dae-Ik Kim, Myung-Whan An, Ho-Yong Chung, Suk-Young Kim
    Area Efficient Implementation of Noise Generation System. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:134-137 [Conf]
  31. Panduka Wijetunga
    High-performance crossbar design for system-on-chip. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:138-143 [Conf]
  32. Mountassar Maamoun, Abdelhalim Benbelkacem, Daoud Berkani, Abderrezak Guessoum
    Interfacing in Microprocessor-based Systems with a Fast Physical Addressing. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:144-149 [Conf]
  33. Hiroto Saito, Shogo Nakamura, Masahide Yoneyama
    A Speech Speed Control Using Fourier Composite Approach. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:152-156 [Conf]
  34. Andrew Y. Lin, Karl S. Gugel, José Carlos Príncipe
    Feasibility of Fixed-Point Transversal Adaptive Filters in FPGA Devices with Embedded DSP Blocks. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:157-160 [Conf]
  35. Sergio Saponara, Luca Fanucci, L. Serafini
    Low-Power FFT/IFFT VLSI Macro Cell for Scalable Broadband VDSL Modem. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:161-166 [Conf]
  36. Shih-Chang Hsia
    VLSI Implementation of Very Low-Power Motion Estimator for Scaleable Coding Systems. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:167-170 [Conf]
  37. Mohamed Karray, Patricia Desgreys, Jean-Jacques Charlot
    A CMOS inverter TIA modeling with VHDL-AMS. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:172-174 [Conf]
  38. Armando Armaroli, Marcello Coppola, Mario Diaz-Nava, Luca Fanucci
    High Level Modeling and Simulation of a VDSL Modem in SystemC 2.0 - IPsim. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:175-180 [Conf]
  39. Sherif G. Aly, Ashraf M. Salem
    Java Based Co-Verification of Expedited Mobile Device. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:181-184 [Conf]
  40. Kasim A. Rashid
    Multi-Models Adaptive Controller for Multivariable Systems. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:185-189 [Conf]
  41. Jari Heikkinen, Tommi Rantanen, Andrea G. M. Cilio, Jarmo Takala, Henk Corporaal
    Evaluating Template-Based Instruction Compression on Transport Triggered Architectures. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:192-195 [Conf]
  42. J. L. Silva, R. M. Costa, G. H. R. Jorge
    RtrASSoc - An Adaptable Superscalar Reconfigurable System-On-Chip. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:196-200 [Conf]
  43. James Northern III, Michael A. Shanblatt
    An Evolutionary Approach to Configuring an Embedded System Based on Power Consumption. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:201-204 [Conf]
  44. Oswaldo Cadenas, Graham M. Megson
    Pullpipelining: A technique for systolic pipelined circuits. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:205-210 [Conf]
  45. Ali Habibi, Sofiène Tahar
    A Survey oA Survey on System-On-a-Chip Designn System-On-a-Chip Design. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:212-215 [Conf]
  46. Azeddien M. Sllame
    Design Space Exploration Methodology for High-Performance System-on-a-Chip Hardware Cores. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:216-221 [Conf]
  47. Christian Panis, Raimund Leitner, Jari Nurmi
    Scaleable Shadow Stack for a Configurable DSP Concept. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:222-227 [Conf]
  48. S. Regimbal, Jean-Francois Lemire, Yvon Savaria, Guy Bois, El Mostapha Aboulhamid, A. Baron
    Automating Functional Coverage Analysis Based on an Executable Specification. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:228-234 [Conf]
  49. Aldo Romani, Fabio Campi, S. Ronconi, Marco Tartagni, Gianni Medoro, Nicolò Manaresi
    A System-on-a-Programmable-Chip for Real-Time Control of Massively Parallel Arrays of Biosensors and Actuators. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:236-241 [Conf]
  50. Vojko Matko
    Porosity Sensor by Using Quartz Crystals and Two Excitation Signals. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:242-246 [Conf]
  51. Abdallah Kassem, J. Wang, Abdelhakim Khouas, Mohamad Sawan, Mounir Boukadoum
    Pipelined Sampled-Delay Focusing CMOS Implementation for Ultrasonic Digital Beamforming. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:247-250 [Conf]
  52. José Vicente Calvano, Marcelo Lubaszewski
    Designing for Test Analog Signal Processors for MEMS-Based Inertial Sensors. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:251-256 [Conf]
  53. Bogdan Georgescu, Joshua K. Nakaska, Robert G. Randall, James W. Haslett
    A 0.28µm CMOS Bluetooth Frequency Synthesizer for Integration with a Bluetooth SOC Reference Platform. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:258-263 [Conf]
  54. Lin Jia, Alper Cabuk, Jianguo Ma, Kiat Seng Yeo
    A 52 GHz VCO with Low Phase Noise Implemented in SiGe BiCMOS Technology. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:264-269 [Conf]
  55. Rodrigo L. Oliveira Pinto, Franco Maloberti
    Novel Design Methodology for Short-Channel MOSFET Analog Circuits. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:270-276 [Conf]
  56. F. Schlogl, H. Zimmermann
    120nm CMOS Operational Amplifier with Pseudo-Cascodes and Positive Feedback. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:277-280 [Conf]
  57. Suchitav Khadanga
    Synchronous programmable divider design for PLL Using 0.18 um cmos technology. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:281-286 [Conf]
  58. Tao Lin, Zhou Zhengou
    The Implementation of 100MHz Data Acquisition Based on FPGA. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:287-291 [Conf]
  59. Chung-Seok (Andy) Seo, Abhijit Chatterjee
    Free-Space Optical Interconnect for High-Performance MCM Systems. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:294-298 [Conf]
  60. Neal K. Bambha, Shuvra S. Bhattacharyya, Gary Euliss
    Design Considerations for Optically Connected Systems on Chip. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:299-303 [Conf]
  61. Partha Pratim Pande, Cristian Grecu, André Ivanov
    High-Throughput Switch-Based Interconnect for Future SoCs. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:304-310 [Conf]
  62. Chang Hee Pyoun, Chi-Ho Lin, Hi-Seok Kim, Jong Wha Chong
    The Efficient Bus Arbitration Scheme in SoC Environment. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:311-315 [Conf]
  63. John Ferguson
    The Glue in a Confident SoC Flow. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:316-319 [Conf]
  64. Masud H. Chowdhury, Yehea I. Ismail
    Analysis of Coupling Noise in Dynamic Circuit. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:320-325 [Conf]
  65. Mohammed Sayed, Wael M. Badawy
    A New Class of Computational RAM Architectures for Real-Time MPEG-4 Applications. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:328-332 [Conf]
  66. Mehboob Alam, Choudhury A. Rahman, Wael M. Badawy, Graham A. Jullien
    Efficient Distributed Arithmetic Based DWT Architecture for Multimedia Applications. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:333-336 [Conf]
  67. Chia-Tien Dan Lo
    The Design of a Self-Maintained Memory Module for Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:337-342 [Conf]
  68. Jae Hong Park, Jung-Min Choi, Min Ho Kim, Jong Wha Chong
    An Efficient Equalizer Architecture Using Tap Allocation Memory for HDTV Channel. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:343-349 [Conf]
  69. Aman A. Al-Imari, Kasim A. Rashid, Mohammed Al-Dagstany
    Telemetry Based System for Measurement and Monitoring of Biomedical Signals. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:352-356 [Conf]
  70. Aman A. Al-Imari, Kasim A. Rashid, Najat Hader Al-Egaidy
    Design and Implementation of a Surface Electromycogram System for Sport Field Application. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:357-361 [Conf]
  71. J. R. Keilman, Graham A. Jullien, Karan V. I. S. Kaler
    A SoC Bio-analysis Platform for Real-time Biological Cell Analysis-on-a-Chip. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:362-368 [Conf]
  72. Jiann-Chyi Rau, Yi-Yuan Chang, Chia-Hung Lin
    An Efficient Mechanism for Debugging RTL Description. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:370-373 [Conf]
  73. Jiann-Chyi Rau, Kuo-Chun Kuo
    An Enhanced Tree-Structured Scan Chain for Pseudo-Exhaustive Testing of VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:374-377 [Conf]
  74. Emil Dumitrescu, Dominique Borrione
    Symbolic Simulation as a Simplifying Strategy for SoC Verification. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:378-383 [Conf]
  75. Nikzad Babaii Rizvandi, Abdolreza Nabavi
    Design, Simulation and Implementation of a Low-Power Digital Decimation Filter for G.232 Standard. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:390-393 [Conf]
  76. Fernando De Bernardinis, Luca Fanucci, T. Ramacciotti, Pierangelo Terreni
    A QoS Internet Protocol Scheduler on the IXP1200 Network Platform. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:394-399 [Conf]
  77. Robert Gulde, Michael Weeks
    A Position Control System Design. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:400-405 [Conf]
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