Conferences in DBLP
Introduction. [Citation Graph (0, 0)][DBLP ] Conf ] Juan Antonio Carballo Open HW, Open Design SW, and the VC Ecosystem Dilemma. [Citation Graph (0, 0)][DBLP ] Conf ] Paul Kempf Enabling Technology for Analog Integration, invited. [Citation Graph (0, 0)][DBLP ] Conf ] S. P. Voinigescu , M. Gordon , C. Lee , T. Yao , A. Mangan , K. Yau System-on-Chip Design beyond 50 GHz, invited. [Citation Graph (0, 0)][DBLP ] Conf ] Scott E. Thompson Strained Si and the Future Direction of CMOS, invited. [Citation Graph (0, 0)][DBLP ] Conf ] Johan van der Tang , Harm van Rumpt , Dieter Kasperkovitz HW/SW Co-Design for SoC on Mobile Platforms, invited. [Citation Graph (0, 0)][DBLP ] Conf ] Alena Tsikhanovich , El Mostapha Aboulhamid , Guy Bois A Methodology for Hw/Sw Specification and Simulation at Multiple Levels of Abstraction. [Citation Graph (0, 0)][DBLP ] Conf ] Paul R. Schumacher , Marco Mattavelli , Adrian Chirila-Rus , Robert D. Turney A Software/Hardware Platform for Rapid Prototyping of Video and Multimedia Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Baodong Yu , Xuecheng Zou The Software/Hardware Co-Debug Environment with Emulator. [Citation Graph (0, 0)][DBLP ] Conf ] Artur Balasinski DfM for SoC, invited. [Citation Graph (0, 0)][DBLP ] Conf ] Yoon Huh , Peter Bendix , Kyungjin Min , Jau-Wen Chen , Ravindra Narayan , Larry D. Johnson , Steven H. Voldman ESD-Induced Internal Core Device Failure: New Failure Modes in System-on-Chip (SoC) Designs, invited. [Citation Graph (0, 0)][DBLP ] Conf ] Azzouz Nezar , Michael Creighton System on Chip: Challenges and Design for Manufacturing, invited. [Citation Graph (0, 0)][DBLP ] Conf ] Mohab Anis , Mohamed H. Abu-Rahma Leakage Current Variability in Nanometer Technologies, invited. [Citation Graph (0, 0)][DBLP ] Conf ] Nur Kurt-Karsilayan Generic Modeling of Non-planar Dielectrics for 2 1/2D Parasitic Extraction. [Citation Graph (0, 0)][DBLP ] Conf ] Luca Larcher , Paolo Pavan , A. Maurelli Flash Memories for SoC: An Overview on System Constraints and Technology Issues, invited. [Citation Graph (0, 0)][DBLP ] Conf ] Dong-Shong Liang , Kwang-Jow Gan , Long-Xian Su , Chi-Pin Chen , Chung-Chih Hsiao , Cher-Shiung Tsai , Yaw-Hwang Chen , Shih-Yu Wang , Shun-Huo Kuo , Feng-Chang Chiang Four-Valued Memory Circuit Designed by Multiple-Peak MOS-NDR Devices and Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Farhad Zarkeshvari , Peter Noel , Tad A. Kwasniewski PLL-Based Fractional-N Frequency Synthesizers. [Citation Graph (0, 0)][DBLP ] Conf ] M. M. Tabriz , Nasser Masoumi A New Topology for Power Control of High Efficiency Class-E Switched Mode Power Amplifier. [Citation Graph (0, 0)][DBLP ] Conf ] Joshua K. Nakaska , James W. Haslett A CMOS Quality Factor Enhanced Parallel Resonant LC-Tank with Independent Q and Frequency Tuning for RF Integrated Filters. [Citation Graph (0, 0)][DBLP ] Conf ] Hyoungsoo Kim , Youngsik Hur , Moonkyun Maeng , Franklin Bien , Soumya Chandramouli , Edward Gebara , Joy Laskar A Novel Clock Recovery Scheme with Improved Jitter Tolerance for PAM4 Signaling. [Citation Graph (0, 0)][DBLP ] Conf ] Shih-Chang Hsia , Wen-Ching Lee A Very Low-Power Flash A/D Converter Based on Cmos Inverter Circuit. [Citation Graph (0, 0)][DBLP ] Conf ] Chia-Jung Chang , Ke-Horng Chen Bidirectional Current-Mode Capacitor Multiplier in DC-DC Converter Compensation. [Citation Graph (0, 0)][DBLP ] Conf ] Chun-Yueh Huang , Tsung-Tien Hou , Chi-Chieh Chuang , Hung-Yu Wang Design of 12-bit 100-MHz Current-Steering DAC for SoC Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Syed Masood Ali , Rabin Raut , Mohamad Sawan A Power Efficient Decoder for 2GHz, 6-bit CMOS Flash-ADC Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] B. Khadem Hosseinieh , N. Masoumi A Comprehensive Model for On-Chip Spiral Inductors. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth A. Townsend , James W. Haslett , Krzysztof Iniewski Design and Optimization of Low-Voltage Low-Power Quasi-Floating Gate Digital Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Lech Józwiak Life-Inspired Systems: Assuring Quality in the Era of Complexity, invited. [Citation Graph (0, 0)][DBLP ] Conf ] James B. Kuo Evolution of Bootstrap Techniques in Low-Voltage CMOS Digital VLSI Circuits for SoC Applications, invited. [Citation Graph (0, 0)][DBLP ] Conf ] Charles E. Berndt , Tad A. Kwasniewski A Review of Common Receive-End Adaptive Equalization Schemes and Algorithms for a High-Speed Serial Backplane. [Citation Graph (0, 0)][DBLP ] Conf ] Robert B. Staszewski , Sameh Rezeq , Chih-Ming Hung , Patrick Cruise , John L. Wallberg Sigma-Delta Noise Shaping for Digital-to-Frequency and Digital-to-RF-Amplitude Conversion. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaolong Yuan , Andreas Gothenberg , Xiaobo Wu Improved Wideband Low Distortion Cascaded Delta-Sigma Modulator. [Citation Graph (0, 0)][DBLP ] Conf ] Mohammad Hadi Izadi , Karim S. Karim Noise Analysis of a CMOS Active Pixel Sensor for Tomographic Mammography. [Citation Graph (0, 0)][DBLP ] Conf ] Amine Bermak Conversion Time Analysis of Time Domain Digital Pixel Sensor in Uniform and Non-Uniform Quantizers, invited. [Citation Graph (0, 0)][DBLP ] Conf ] Yanjie Wang , Yanbin Wang , Garry Tarr , Kris Iniewski A Temperature, Supply Voltage Compensated Floating-Gate MOS Dosimeter Using V_TH Extractor. [Citation Graph (0, 0)][DBLP ] Conf ] Haigang Yang , Hongguang Sun , Jinghong Han , Jinbao Wei , Zengjin Lin , Shanhong Xia , Hua Zhong A pH-ISFET Based Micro Sensor System on Chip Using Standard CMOS Technology. [Citation Graph (0, 0)][DBLP ] Conf ] Mohammad M. Ahmadi , Graham A. Jullien A Very Low Power CMOS Potentiostat for Bioimplantable Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Mostafa Borhani , Vafa Sedghi An Acoustic Echo Canceller Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Shih-Chang Hsia , Shih Wen Chou A High-Performance Error Concealment Processor for Video Decoder. [Citation Graph (0, 0)][DBLP ] Conf ] Farid Boussaïd , Chen Shoushun , Amine Bermak A Scalable Low Power Imager Architecture for Compound-Eye Vision Sensors. [Citation Graph (0, 0)][DBLP ] Conf ] Choudhury A. Rahman , Wael M. Badawy UMHexagonS Algorithm Based Motion Estimation Architecture for H.264/AVC. [Citation Graph (0, 0)][DBLP ] Conf ] Ihab Amer , Choudhury A. Rahman , Tamer Mohamed , Mohammed Sayed , Wael M. Badawy A Hardware-Accelerated Framework with IP-Blocks for Application in MPEG-4. [Citation Graph (0, 0)][DBLP ] Conf ] Robert B. Staszewski , Khurram Muhammad , Dirk Leipold Digital RF Processing Techniques for SoC Radios, invited. [Citation Graph (0, 0)][DBLP ] Conf ] Christian Cojocaru Low Power Bluetooth for Headset Applications, invited. [Citation Graph (0, 0)][DBLP ] Conf ] N. Patrick Kelly , Ben W. Jones , Nestor A. Fesas , John M. Morton Design of 802.11 Access Point Chipsets for Enterprise Applications, invited. [Citation Graph (0, 0)][DBLP ] Conf ] Robert B. Staszewski , Roman Staszewski , Poras T. Balsara VHDL Simulation and Modeling of an All-Digital RF Transmitter. [Citation Graph (0, 0)][DBLP ] Conf ] Il-Gu Lee , Heejung Yu , Sok-Kyu Lee , Jin Lee , Sin-Chong Park Efficient Pattern-Based Emulation for IEEE 802.11a Baseband. [Citation Graph (0, 0)][DBLP ] Conf ] Yanjie Wang , Kris Iniewski A 2.3GHz CMOS Transimpedance Preamplifier for Optical Communication. [Citation Graph (0, 0)][DBLP ] Conf ] Yanjie Wang , M. Zamin Khan , Kris Iniewski A 0.65V, 1.9mW CMOS Low-Noise Amplifier at 5GHz. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Wiklund , Dake Liu Design Mapping, and Simulations of a 3G WCDMA/FDD Basestation Using Network on Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Jung Ko , Vincent C. Gaudet , Robert Hang A Tier 3 Software Defined AM Radio. [Citation Graph (0, 0)][DBLP ] Conf ] S. A. Moghaddam , N. Masoumi , C. Lucas A Stochastic Power-Supply Noise Reduction Technique Using Max-Flow Algorithm and Decoupling Capacitance. [Citation Graph (0, 0)][DBLP ] Conf ] Jianhua Li , Laleh Behjat , Blair Schiffner A Structure Based Clustering Algorithm with Applications to VLSI Physical Design. [Citation Graph (0, 0)][DBLP ] Conf ] P. L. Takouda , Miguel F. Anjos , Anthony Vannelli Global Lower Bounds for the VLSI Macrocell Floorplanning Problem Using Semidefinite Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Nasser Masoumi , Mahmoud Ahmadian , Farshid Raissi , Massoud Masoumi , J. Ghasemi Enhancing Performance and Saving Energy in CMOS DCVSL Gates by Using a New Transistor Sizing Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Robert Grou-Szabo , Hany Ghattas , Yvon Savaria , Gabriela Nicolescu Component-Based Methodology for Hardware Design of a Dataflow Processing Network. [Citation Graph (0, 0)][DBLP ] Conf ] Li-Chun Tien , Jing-Jou Tang , Mi-Chang Chang An Automatic Layout Generator for I/O Cells. [Citation Graph (0, 0)][DBLP ] Conf ] Tina Lindkvist Additional Knowledge of Bus Invert Coding Schemes. [Citation Graph (0, 0)][DBLP ] Conf ] Marco Mattavelli , Massimo Ravasi High Level Extraction of SoC Architectural Information from Generic C Algorithmic Descriptions. [Citation Graph (0, 0)][DBLP ] Conf ] Abhijit Ray , Thambipillai Srikanthan , Wu Jigang Practical Techniques for Performance Estimation of Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Blair Schiffner , Jianhua Li , Laleh Behjat A Multivalue Eigenvalue Based Circuit Partitioning Technique. [Citation Graph (0, 0)][DBLP ] Conf ] Haidar Harmanani , Bassem Karablieh A Hybrid Distributed Test Generation Method Using Deterministic and Genetic Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Russell Klein , Tomasz Piekarz Accelerating Functional Simulation for Processor Based Designs, invited. [Citation Graph (0, 0)][DBLP ] Conf ] Ho-seok Choi , Seungbeom Lee , Sin-Chong Park Instruction Based Testbench Architecture, invited. [Citation Graph (0, 0)][DBLP ] Conf ] J. Derakhshandeh , Nasser Masoumi , B. Kasiri , Y. Farazmand , Akbarzadeh , S. Aghnoot A Precise Model for Leakage Power Estimation in VLSI Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Moeed Israr , Tad A. Kwasniewski Turbo Codes - Digital IC Design. [Citation Graph (0, 0)][DBLP ] Conf ] Eric Tell , Anders Nilsson , Dake Liu A Low Area and Low Power Programmable Baseband Processor Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Hung-Ch Lee , Kuo-Tai Chang , Ke-Horng Chen , Wen Tsao Chen Power Saving of a Dynamic Width Controller for a Monolithic Current-Mode CMOS DC-DC Converter. [Citation Graph (0, 0)][DBLP ] Conf ] Ki-Bog Kim , Chi-Ho Lin An Optimal ILP Model for Delay Time to Minimize Peak Power and Area. [Citation Graph (0, 0)][DBLP ] Conf ] Meeta Srivastav , S. S. S. P. Rao , Himanshu Bhatnagar Power Reduction Technique Using Multi-vt Libraries. [Citation Graph (0, 0)][DBLP ] Conf ] Payam Ghafari , Ehsan Mirhadi , Mohab Anis , Shawki Areibi , Mohamed I. Elmasry A Low-Power Partitioning Methodology by Maximizing Sleep Time and Minimizing Cut Nets. [Citation Graph (0, 0)][DBLP ] Conf ] Dong-Shong Liang , Kwang-Jow Gan , Chung-Chih Hsiao , Cher-Shiung Tsai , Yaw-Hwang Chen , Shih-Yu Wang , Shun-Huo Kuo , Feng-Chang Chiang , Long-Xian Su Novel Voltage-Controlled Oscillator Design by MOS-NDR Devices and Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Richard Hobson , Scott Wakelin An Area-Efficient High-Speed AES S-Box Method. [Citation Graph (0, 0)][DBLP ] Conf ] Sang-Ho Seo , Sin-Chong Park Low Latency and Power Efficient VD Using Register Exchanged State-Mapping Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Amir Khatibzadeh , Kaamran Raahemifar A Novel Design of a 6-GHz 8 X 8-b Pipelined Multiplier. [Citation Graph (0, 0)][DBLP ] Conf ] Kwang-Jow Gan , Dong-Shong Liang , Chung-Chih Hsiao , Shih-Yu Wang , Feng-Chang Chiang , Cher-Shiung Tsai , Yaw-Hwang Chen , Shun-Huo Kuo , Chi-Pin Chen Logic Circuit Design Based on MOS-NDR Devices and Circuits Fabricated by CMOS Process. [Citation Graph (0, 0)][DBLP ] Conf ] Shaoqiang Bi , Warren J. Gross , Wei Wang , Asim J. Al-Khalili , M. N. S. Swamy An Area-Reduced Scheme for Modulo 2n-1 Addition/Subtraction. [Citation Graph (0, 0)][DBLP ] Conf ] Kyle Kelley , David Harris Very High Radix Scalable Montgomery Multipliers. [Citation Graph (0, 0)][DBLP ] Conf ] Chul-hyung Ryu , Sung-Woong Ra A Fast Full Search Equivalent Encoding Algorithm for Image Vector Quantization Based on the WHT and a LUT. [Citation Graph (0, 0)][DBLP ] Conf ] Paul E. Hasler Low-Power Programmable Signal Processing, invited. [Citation Graph (0, 0)][DBLP ] Conf ] Mona Safar , M. Watheq El-Kharashi , Ashraf Salem An FPGA Based Accelerator for SAT Based Combinational Equivalence Checking. [Citation Graph (0, 0)][DBLP ] Conf ] David N. Abramson , Jordan D. Gray , Shyam Subramanian , Paul E. Hasler A Field-Programmable Analog Array Using Translinear Elements. [Citation Graph (0, 0)][DBLP ] Conf ] P. Samson , P. Sinha Hardware Acceleration of Deadlock Avoidance and Detection in Real-Time Operating Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Joachim Becker , Fabian Henrici , Yiannos Manoli System-Level Analog Simulation of a Mixed-Signal Continuous-Time Field Programmable Analog Array. [Citation Graph (0, 0)][DBLP ] Conf ] Miro Milanovic , Mitja Truntic , Primoz Slibar FPGA Implementation of Digital Controller for DC-DC Buck Converter. [Citation Graph (0, 0)][DBLP ] Conf ] A. N. M. Ehtesham Rafiq , M. Watheq El-Kharashi , Fayez Gebali Systolic Array-Based String Matching Unit for Spam Blocking. [Citation Graph (0, 0)][DBLP ] Conf ] Esam Khan , M. Watheq El-Kharashi , Fayez Gebali , Mostafa Abd-El-Barr An FPGA Design of a Unified Hash Engine for IPSec Authentication. [Citation Graph (0, 0)][DBLP ] Conf ] Bill Pontikakis , François R. Boyer , Yvon Savaria Performance Improvement of Configurable Processor Architectures Using a Variable Clock Period. [Citation Graph (0, 0)][DBLP ] Conf ] Paul Hasler , AiChen Low Programmable Low Dropout Voltage Regulator. [Citation Graph (0, 0)][DBLP ] Conf ] Earl E. Swartzlander Jr. Three Dimensional System on Chip Technology, invited. [Citation Graph (0, 0)][DBLP ] Conf ] Sung-Rok Yoon , Sin-Chong Park Simulation and Analysis of Network on Chip Architecture for Wireless Communication System. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth A. Townsend , James W. Haslett , Tommy Kwong-Kin Tsang , Mourad N. El-Gamal , Krzysztof Iniewski Recent Advances and Future Trends in Low Power Wireless Systems for Medical Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Paul E. Hasler Floating-Gate Devices, Circuits, and Systems, invited. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen Bates , Kris Iniewski 10 GBPS over Copper Lines - State of the Art in VLSI, invited. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas Palkert A Review of Current Standards Activities for High Speed Physical Layers, invited. [Citation Graph (0, 0)][DBLP ] Conf ] Miao Li , Peter Noel , Tad A. Kwasniewski , Shoujun Wang Decision Feedback Equalization with Quarter-Rate Clock Timing for High-Speed Backplane Data Communications. [Citation Graph (0, 0)][DBLP ] Conf ] S. M. Rezaul Hasan A High Efficiency 3GHz 24-dBm CMOS Linear Power Amplifier for RF Application. [Citation Graph (0, 0)][DBLP ] Conf ] Ching-Te Chiu , Chun-Chieh Chang , Shih-Min Chen , Hou-Cheng Tzeng , Ming-Chang Du , Yu-Ho Hsu , Jen-Ming Wu , Kai-Ming Feng A 20 Gbps Scalable Load-Balanced TDM Switch with CODEC for High Speed Networking Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Vladimir Stojanovic High-Speed Serial Links: Design Trends and Challenges, invited. [Citation Graph (0, 0)][DBLP ] Conf ] Roger Su , Raman Mittal , Vivek Garg Synchronous Pipelined Relay Stations with Back-Pressure Tolerance. [Citation Graph (0, 0)][DBLP ] Conf ] Xiqun Zhu , Yuan Ma Modular Architecture for System-on-Chip Design of Scalable MEMS Optical Switch Actuator Controller. [Citation Graph (0, 0)][DBLP ] Conf ] Gyongsu Lee , Sin-Chong Park Architecture for Multi-processor SoC Platform Using Dedicated Channels. [Citation Graph (0, 0)][DBLP ] Conf ] Sangik Choi , Shinwook Kang Implementation of an On-Chip Bus Bridge between Heterogeneous Buses with Different Clock Frequencies. [Citation Graph (0, 0)][DBLP ] Conf ] Zhonghai Lu , Axel Jantsch Traffic Configuration for Evaluating Networks on Chips. [Citation Graph (0, 0)][DBLP ] Conf ] Jin Lee , Sin-Chong Park Orthogonalized Communication Architecture for MP-SoC with Global Bus. [Citation Graph (0, 0)][DBLP ] Conf ] Luiza Gheorghe , Gabriela Nicolescu MP SoCs Including Optical Interconnect. Technological Progresses and Challenges for CAD Tools Design. [Citation Graph (0, 0)][DBLP ] Conf ] Seungbeom Lee , Sin-Chong Park Transaction Analysis of Multiprocessor Based Platform with Bus Matrix. [Citation Graph (0, 0)][DBLP ] Conf ] Hung Tien Bui , Yvon Savaria A Generic Method for Embedded Measurement and Compensation of Process and Temperature Variations in SoCs. [Citation Graph (0, 0)][DBLP ] Conf ] 