Conferences in DBLP
Margaret Martonosi Embedded systems in the wild: ZebraNet software, hardware, and deployment experiences. [Citation Graph (0, 0)][DBLP ] Conf ] Carl von Platen , Johan Eker Feedback linking: optimizing object code layout for updates. [Citation Graph (0, 0)][DBLP ] Conf ] Kun Zhang , Santosh Pande Minimizing downtime in seamless migrations of mobile applications. [Citation Graph (0, 0)][DBLP ] Conf ] Michal Spivak , Sivan Toledo Storing a persistent transactional object heap on flash memory. [Citation Graph (0, 0)][DBLP ] Conf ] John Regehr , Usit Duongsaa Deriving abstract transfer functions for analyzing embedded software. [Citation Graph (0, 0)][DBLP ] Conf ] Nathan Cooprider , John Regehr Pluggable abstract domains for analyzing embedded software. [Citation Graph (0, 0)][DBLP ] Conf ] Antoine Miné Field-sensitive value analysis of embedded C programs with union types and pointer arithmetics. [Citation Graph (0, 0)][DBLP ] Conf ] William C. Kreahling , Stephen Hines , David B. Whalley , Gary S. Tyson Reducing the cost of conditional transfers of control by using comparison specifications. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaotong Zhuang , Santosh Pande Effective thread management on network processors with compiler analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Prasad Kulkarni , David B. Whalley , Gary S. Tyson , Jack W. Davidson In search of near-optimal optimization phase orderings. [Citation Graph (0, 0)][DBLP ] Conf ] Klaus Danne , Marco Platzner An EDF schedulability test for periodic tasks on reconfigurable hardware devices. [Citation Graph (0, 0)][DBLP ] Conf ] Christer Sandberg , Andreas Ermedahl , Jan Gustafsson , Björn Lisper Faster WCET flow analysis by program slicing. [Citation Graph (0, 0)][DBLP ] Conf ] Steffen Prochnow , Claus Traulsen , Reinhard von Hanxleden Synthesizing safe state machines from Esterel. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen A. Edwards , Olivier Tardieu Efficient code generation from SHIM models. [Citation Graph (0, 0)][DBLP ] Conf ] Tom Rothamel , Yanhong A. Liu , Constance L. Heitmeyer , Elizabeth I. Leonard Generating optimized code from SCR specifications. [Citation Graph (0, 0)][DBLP ] Conf ] Stefan Farfeleder , Andreas Krall , Edwin Steiner , Florian Brandner Effective compiler generation by architecture description. [Citation Graph (0, 0)][DBLP ] Conf ] Jian-Jia Chen , Tei-Wei Kuo Procrastination for leakage-aware rate-monotonic scheduling on a dynamic voltage scaling processor. [Citation Graph (0, 0)][DBLP ] Conf ] Madhu Mutyam , Feihui Li , Narayanan Vijaykrishnan , Mahmut T. Kandemir , Mary Jane Irwin Compiler-directed thermal management for VLIW functional units. [Citation Graph (0, 0)][DBLP ] Conf ] Sanghyun Park , Aviral Shrivastava , Nikil D. Dutt , Alexandru Nicolau , Yunheung Paek , Eugene Earlie Bypass aware instruction scheduling for register file power reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Leipo Yan , Thambipillai Srikanthan , Niu Gang Area and delay estimation for FPGA implementation of coarse-grained reconfigurable architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Raju Pandey , Jeffrey Wu BOTS: a constraint-based component system for synthesizing scalable software systems. [Citation Graph (0, 0)][DBLP ] Conf ] Weihua Zhang , Xinglong Qian , Ye Wang , Binyu Zang , Chuanqi Zhu Optimizing compiler for shared-memory multiple SIMD architecture. [Citation Graph (0, 0)][DBLP ] Conf ] 