Conferences in DBLP
Philippe Magarshack Systems-on-chip needs for embedded software development: an industrial perspective. [Citation Graph (0, 0)][DBLP ] Conf ] Hendra Saputra , Mahmut T. Kandemir , Narayanan Vijaykrishnan , Mary Jane Irwin , Jie S. Hu , Chung-Hsing Hsu , Ulrich Kremer Energy-conscious compilation based on voltage scaling. [Citation Graph (0, 0)][DBLP ] Conf ] Hyunok Oh , Soonhoi Ha Fractional rate dataflow model and efficient code synthesis for multimedia applications. [Citation Graph (0, 0)][DBLP ] Conf ] Sumit Mohanty , Viktor K. Prasanna , Sandeep Neema , James R. Davis Rapid design space exploration of heterogeneous embedded systems using symbolic search and multi-granular simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Krishna V. Palem , Rodric M. Rabbah , Vincent John Mooney , Pinar Korkmaz , Kiran Puttaswamy Design space optimization of embedded memory systems via data remapping. [Citation Graph (0, 0)][DBLP ] Conf ] Frank Hunleth , Ron Cytron Footprint and feature management using aspect-oriented programming techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Kästner , Stephan Wilhelm Generic control flow reconstruction from assembly code. [Citation Graph (0, 0)][DBLP ] Conf ] Arvind Krishnaswamy , Rajiv Gupta Profile guided selection of ARM and thumb instructions. [Citation Graph (0, 0)][DBLP ] Conf ] Takayuki Wakabayashi , Hiroaki Takada Standardization approach of ITRON debugging interface specification and evaluation of its adaptability. [Citation Graph (0, 0)][DBLP ] Conf ] Arshad Jhumka , Martin Hiller , Vilgot Claesson , Neeraj Suri On systematic design of globally consistent executable assertions in embedded software. [Citation Graph (0, 0)][DBLP ] Conf ] Xiushan Feng , Alan J. Hu Automatic formal verification for scheduled VLIW code. [Citation Graph (0, 0)][DBLP ] Conf ] Gerhard Fettweis DSPs: why don't they just go away!. [Citation Graph (0, 0)][DBLP ] Conf ] Markus Lorenz , Lars Wehmeyer , Thorsten Dräger Energy aware compilation for DSPs with SIMD instructions. [Citation Graph (0, 0)][DBLP ] Conf ] Christoph W. Keßler , Andrzej Bednarski Optimal integrated code generation for clustered VLIW architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Yi Qian , Steve Carr , Philip H. Sweany Loop fusion for clustered VLIW architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Mayur Naik , Jens Palsberg Compiling with code-size constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Jeonghun Cho , Yunheung Paek , David B. Whalley Efficient register and memory assignment for non-orthogonal architectures via graph coloring and MST algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Bernhard Scholz , Erik Eckstein Register allocation for irregular architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Volker Barthelmann Inter-task register-allocation for static operating systems. [Citation Graph (0, 0)][DBLP ] Conf ] Wankang Zhao , Baosheng Cai , David B. Whalley , Mark W. Bailey , Robert van Engelen , Xin Yuan , Jason Hiser , Jack W. Davidson , Kyle Gallivan , Douglas L. Jones VISTA: a system for interactive code improvement. [Citation Graph (0, 0)][DBLP ] Conf ] Jie S. Hu , Mahmut T. Kandemir , Narayanan Vijaykrishnan , Mary Jane Irwin , Hendra Saputra , Wei Zhang 0002 Compiler-directed cache polymorphism. [Citation Graph (0, 0)][DBLP ] Conf ] Christopher W. Milner , Jack W. Davidson Quick piping: a fast, high-level model for describing processor pipelines.Citation Graph (0, 0)][DBLP ] Conf ] Oliver Wahlen , Tilman Glökler , Achim Nohl , Andreas Hoffmann , Rainer Leupers , Heinrich Meyr Application specific compiler/architecture codesign: a case study. [Citation Graph (0, 0)][DBLP ] Conf ] Jeffrey Palm , Han Bok Lee , Amer Diwan , J. Eliot B. Moss When to use a compilation service? [Citation Graph (0, 0)][DBLP ] Conf ] Matt Newsome , Des Watson Proxy compilation of dynamically loaded Java classes with MoJo. [Citation Graph (0, 0)][DBLP ] Conf ] Ajay Dudani , Frank Mueller , Yifan Zhu Energy-conserving feedback EDF scheduling for embedded systems with real-time constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Saehwa Kim , Seongsoo Hong , Tae-hyung Kim Perfecting preemption threshold scheduling for object-oriented real-time system design: from the perspective of real-time synchronization. [Citation Graph (0, 0)][DBLP ] Conf ] 