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Conferences in DBLP
- Randal E. Bryant
System modeling and verification with UCLID. [Citation Graph (0, 0)][DBLP]
MEMOCODE, 2004, pp:3-4 [Conf]
- Himanshu Jain, Daniel Kroening, Edmund M. Clarke
Verification of SpecC using predicate abstraction. [Citation Graph (0, 0)][DBLP]
MEMOCODE, 2004, pp:7-16 [Conf]
- Tobias Schüle, Klaus Schneider
Bounded model checking of infinite state systems: exploiting the automata hierarchy. [Citation Graph (0, 0)][DBLP]
MEMOCODE, 2004, pp:17-26 [Conf]
- Ahmed Sobeih, Mahesh Viswanathan, Jennifer C. Hou
Check and simulate: a case for incorporating model checking in network simulation. [Citation Graph (0, 0)][DBLP]
MEMOCODE, 2004, pp:27-36 [Conf]
- Olivier Tardieu, Robert de Simone
Curing schizophrenia by program rewriting in Esterel. [Citation Graph (0, 0)][DBLP]
MEMOCODE, 2004, pp:39-48 [Conf]
- Grace Nordin, James C. Hoe
Synchronous extensions to operation centric hardware description languages. [Citation Graph (0, 0)][DBLP]
MEMOCODE, 2004, pp:49-56 [Conf]
- Christel Baier, Frank Ciesinski, Marcus Größer
PROBMELA: a modeling language for communicating probabilistic processes. [Citation Graph (0, 0)][DBLP]
MEMOCODE, 2004, pp:57-66 [Conf]
- Rishiyur S. Nikhil
Bluespec System Verilog: efficient, correct RTL from high level specifications. [Citation Graph (0, 0)][DBLP]
MEMOCODE, 2004, pp:69-70 [Conf]
- Ralph D. Jeffords, Elizabeth I. Leonard
Using invariants to optimize formal specifications before code synthesis. [Citation Graph (0, 0)][DBLP]
MEMOCODE, 2004, pp:73-82 [Conf]
- Dag Björklund
Efficient code synthesis from synchronous dataflow graphs. [Citation Graph (0, 0)][DBLP]
MEMOCODE, 2004, pp:83-92 [Conf]
- Nirav Dave
Designing a reorder buffer in Bluespec. [Citation Graph (0, 0)][DBLP]
MEMOCODE, 2004, pp:93-102 [Conf]
- David L. Dill
The battle of accountable voting systems. [Citation Graph (0, 0)][DBLP]
MEMOCODE, 2004, pp:105- [Conf]
- Cagkan Erbas, Selin C. Erbas, Andy D. Pimentel
Static priority scheduling of event triggered real time embedded systems. [Citation Graph (0, 0)][DBLP]
MEMOCODE, 2004, pp:109-118 [Conf]
- Bhaskar Pal, Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti
The BUSpec platform for automated generation of verification aids for standard bus protocols. [Citation Graph (0, 0)][DBLP]
MEMOCODE, 2004, pp:119-128 [Conf]
- K. Kalyanasundaram, R. K. Shyamasundar
Formal verification of pipelined processors with precise exceptions. [Citation Graph (0, 0)][DBLP]
MEMOCODE, 2004, pp:129-139 [Conf]
- Brian Bailey
Is formal being squeezed out of functional verification? [Citation Graph (0, 0)][DBLP]
MEMOCODE, 2004, pp:143- [Conf]
- Gerard J. Holzmann
Formal methods and software reliability. [Citation Graph (0, 0)][DBLP]
MEMOCODE, 2004, pp:145-146 [Conf]
- Robert P. Kurshan
Formal verification as a technology transfer problem. [Citation Graph (0, 0)][DBLP]
MEMOCODE, 2004, pp:147-150 [Conf]
- Vladimir Levin
Static driver verifier, a formal verification tool for Windows device drivers. [Citation Graph (0, 0)][DBLP]
MEMOCODE, 2004, pp:151- [Conf]
- John O'Leary
Formal verification in Intel CPU design. [Citation Graph (0, 0)][DBLP]
MEMOCODE, 2004, pp:152- [Conf]
- Carl Pixley, D. Meyers, S. McMaster, A. Chittor
Designers want proofs - but show me the money. [Citation Graph (0, 0)][DBLP]
MEMOCODE, 2004, pp:153-154 [Conf]
- Sandeep K. Shukla, Tevfik Bultan, Constance L. Heitmeyer
Panel: given that hardware verification has been an uphill battle, what is the future of software verification? [Citation Graph (0, 0)][DBLP]
MEMOCODE, 2004, pp:157-158 [Conf]
- Edward A. Lee, Stephen Neuendorffer
Classes and subclasses in actor-oriented design. [Citation Graph (0, 0)][DBLP]
MEMOCODE, 2004, pp:161-168 [Conf]
- Daniel Große, Rolf Drechsler
Checkers for SystemC designs. [Citation Graph (0, 0)][DBLP]
MEMOCODE, 2004, pp:171-178 [Conf]
- Stephen Neuendorffer, Edward A. Lee
Hierarchical reconfiguration of dataflow models. [Citation Graph (0, 0)][DBLP]
MEMOCODE, 2004, pp:179-188 [Conf]
- Daniel L. Rosenband
The ephemeral history register: flexible scheduling for rule-based designs. [Citation Graph (0, 0)][DBLP]
MEMOCODE, 2004, pp:189-198 [Conf]
- Sagar Chaki, Edmund M. Clarke, Joël Ouaknine, Natasha Sharygina
Automated, compositional and iterative deadlock detection. [Citation Graph (0, 0)][DBLP]
MEMOCODE, 2004, pp:201-210 [Conf]
- Christoph Sprenger, Dilian Gurov, Marieke Huisman
Compositional verification for secure loading of smart card applets. [Citation Graph (0, 0)][DBLP]
MEMOCODE, 2004, pp:211-222 [Conf]
- Yamine Aït Ameur, Remi Delmas, Virginie Wiels
A framework for heterogeneous formal modeling and compositional verification of avionics systems. [Citation Graph (0, 0)][DBLP]
MEMOCODE, 2004, pp:223-232 [Conf]
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