Conferences in DBLP
Nicolas Halbwachs A synchronous language at work: the story of Lustre. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Pellauer , Mieszko Lis , Don Baltus , Rishiyur S. Nikhil Synthesis of synchronous assertions with guarded atomic actions. [Citation Graph (0, 0)][DBLP ] Conf ] Nirav Dave , Man Cheuk Ng , Arvind Automatic synthesis of cache-coherence protocol processors using Bluespec. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen A. Edwards , Olivier Tardieu Deterministic receptive processes are Kahn processes. [Citation Graph (0, 0)][DBLP ] Conf ] Shuqing Zhao , Daniel D. Gajski Structural operational semantics for supporting multi-cycle operations in RTL HDLs. [Citation Graph (0, 0)][DBLP ] Conf ] Greg Hoover , Forrest Brewer PyPBS design and methodologies. [Citation Graph (0, 0)][DBLP ] Conf ] Myla Archer Making PVS do what you want. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Gajski System design extreme makeover. [Citation Graph (0, 0)][DBLP ] Conf ] Tuba Yavuz-Kahveci , Tevfik Bultan Verification of parameterized hierarchical state machines using action language verifier. [Citation Graph (0, 0)][DBLP ] Conf ] Jan Jürjens Verification of low-level crypto-protocol implementations using automated theorem proving. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Kroening , Natasha Sharygina Formal verification of SystemC by automatic hardware/software partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Fei Xie , Xiaoyu Song , Haera Chung , Ranajoy Nandi Translation-based co-verification. [Citation Graph (0, 0)][DBLP ] Conf ] Thanyapat Sakunkonchak , Satoshi Komatsu , Masahiro Fujita Synchronization verification in system-level design with ILP solvers. [Citation Graph (0, 0)][DBLP ] Conf ] Nicolae Savoiu , Sandeep K. Shukla , Rajesh K. Gupta Improving SystemC simulation through Petri net reductions. [Citation Graph (0, 0)][DBLP ] Conf ] Manfred Broy Automotive software and systems engineering (Panel). [Citation Graph (0, 0)][DBLP ] Conf ] Ingolf Krüger Service-oriented software and systems engineering - a vision for the automotive domain. [Citation Graph (0, 0)][DBLP ] Conf ] Wolfgang Pree From bold idea to product - a case study. [Citation Graph (0, 0)][DBLP ] Conf ] Felice Balarin , Claudio Passerone , Alessandro Pinto , Alberto L. Sangiovanni-Vincentelli A formal approach to system level design: metamodels and unified design environments. [Citation Graph (0, 0)][DBLP ] Conf ] Françoise Bellegarde , Samir Chouali , Jacques Julliand Refinemant verification of fair transition systems can contribute to PLTL model checking. [Citation Graph (0, 0)][DBLP ] Conf ] Tobias Schüle , Klaus Schneider Three-valued logic in bounded model checking. [Citation Graph (0, 0)][DBLP ] Conf ] Panagiotis Manolios , Sudarshan K. Srinivasan A computationally ef~cient method based on commitment re~nement maps for verifying pipelined machines. [Citation Graph (0, 0)][DBLP ] Conf ] Ali Sezgin , Ganesh Gopalakrishnan On the decidability of shared memory consistency verification. [Citation Graph (0, 0)][DBLP ] Conf ] Christos Kloukinas Thunderstriking constraints with JUPITER. [Citation Graph (0, 0)][DBLP ] Conf ] Stefano Brait , Franco Fummi , Graziano Pravadelli On the use of a high-level fault model to analyze logical consequence of properties. [Citation Graph (0, 0)][DBLP ] Conf ] Tevfik Bultan , Constance L. Heitmeyer , John O'Leary Panel on design for verification. [Citation Graph (0, 0)][DBLP ] Conf ] Nicola Bombieri , Andrea Fedeli , Franco Fummi Extended abstract: on the property-based verification in SoC design flow founded on transaction level modeling. [Citation Graph (0, 0)][DBLP ] Conf ] Masahiro Fujita Extended abstract: a formal design approach from software oriented UML descriptions to hardware oriented RTL. [Citation Graph (0, 0)][DBLP ] Conf ] Ralph D. Jeffords , Ramesh Bharadwaj Extended abstract: formal verification of architectural patterns in support of dependable distributed systems. [Citation Graph (0, 0)][DBLP ] Conf ] Elizabeth I. Leonard , Myla Archer Extended abstract: organizing automaton specifications to achieve faithful representation. [Citation Graph (0, 0)][DBLP ] Conf ] Gustaf Naeser , Johan Furunäs Extended abstract: evaluation of delay queues for a Ravenscar HW kernel. [Citation Graph (0, 0)][DBLP ] Conf ] Lars Pareto Extended abstract: requirements modeling within iterative, incremental processes. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Poplavko , Twan Basten , Milan Pastrnak , Jef L. van Meerbergen , Marco Bekooij , Peter H. N. de With Extended abstract: estimation times of on-chip multiprocessor stream-oriented applications. [Citation Graph (0, 0)][DBLP ] Conf ] Klaus Rothbart , Ulrich Neffe , Christian Steger , Reinhold Weiss , Edgar Rieger , Andreas Mühlberger Extended abstract: an environment for design verification of smart card systems using attack simulation in SystemC. [Citation Graph (0, 0)][DBLP ] Conf ] Patrick Schaumont , Sandeep K. Shukla , Ingrid Verbauwhede Extended abstract: a race-free hardware modeling language. [Citation Graph (0, 0)][DBLP ] Conf ] Iñigo Ugarte , Pablo Sanchez Extended abstract: polynomial model-based evaluation of the branch coverage metric for functional verification of hardware systems. [Citation Graph (0, 0)][DBLP ] Conf ] Xingwen Xu , Shinji Kimura , Kazunari Horikawa , Takehiko Tsuchiya Extended abstract: transition traversal coverage estimation for symbolic model checking. [Citation Graph (0, 0)][DBLP ] Conf ] 