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Conferences in DBLP

International Symposium on Microarchitecture (MICRO) (micro)
2004 (conf/micro/2004)

  1. Shekhar Y. Borkar
    Microarchitecture and Design Challenges for Gigascale Integration. [Citation Graph (0, 0)][DBLP]
    MICRO, 2004, pp:3- [Conf]
  2. Peter G. Sassone, D. Scott Wills
    Dynamic Strands: Collapsing Speculative Dependence Chains for Reducing Pipeline Communication. [Citation Graph (0, 0)][DBLP]
    MICRO, 2004, pp:7-17 [Conf]
  3. Anne Bracy, Prashant Prahlad, Amir Roth
    Dataflow Mini-Graphs: Amplifying Superscalar Capacity and Bandwidth. [Citation Graph (0, 0)][DBLP]
    MICRO, 2004, pp:18-29 [Conf]
  4. Nathan Clark, Manjunath Kudlur, Hyunchul Park, Scott A. Mahlke, Krisztián Flautner
    Application-Specific Processing on a General-Purpose Core via Transparent Instruction Set Customization. [Citation Graph (0, 0)][DBLP]
    MICRO, 2004, pp:30-40 [Conf]
  5. Daniel Gracia Pérez, Gilles Mouchard, Olivier Temam
    MicroLib: A Case for the Quantitative Comparison of Micro-Architecture Mechanisms. [Citation Graph (0, 0)][DBLP]
    MICRO, 2004, pp:43-54 [Conf]
  6. Martin Burtscher, Ilya Ganusov
    Automatic Synthesis of High-Speed Processor Simulators. [Citation Graph (0, 0)][DBLP]
    MICRO, 2004, pp:55-66 [Conf]
  7. Li Shang, Li-Shiuan Peh, Amit Kumar 0002, Niraj K. Jha
    Thermal Modeling, Characterization and Management of On-Chip Networks. [Citation Graph (0, 0)][DBLP]
    MICRO, 2004, pp:67-78 [Conf]
  8. Harish Patil, Robert S. Cohn, Mark Charney, Rajiv Kapoor, Andrew Sun, Anand Karunanidhi
    Pinpointing Representative Portions of Large Intel® Itanium® Programs with Dynamic Instrumentation. [Citation Graph (0, 0)][DBLP]
    MICRO, 2004, pp:81-92 [Conf]
  9. Murali Annavaram, Ryan Rakvic, Marzia Polito, Jean-Yves Bouguet, Richard A. Hankins, Bob Davies
    The Fuzzy Correlation between Code and Performance Predictability. [Citation Graph (0, 0)][DBLP]
    MICRO, 2004, pp:93-104 [Conf]
  10. Xiangyu Zhang, Rajiv Gupta
    Whole Execution Traces. [Citation Graph (0, 0)][DBLP]
    MICRO, 2004, pp:105-116 [Conf]
  11. David N. Armstrong, Hyesoon Kim, Onur Mutlu, Yale N. Patt
    Wrong Path Events: Exploiting Unusual and Illegal Program Behavior for Early Misprediction Detection and Recovery. [Citation Graph (0, 0)][DBLP]
    MICRO, 2004, pp:119-128 [Conf]
  12. Jamison D. Collins, Dean M. Tullsen, Hong Wang
    Control Flow Optimization Via Dynamic Reconvergence Prediction. [Citation Graph (0, 0)][DBLP]
    MICRO, 2004, pp:129-140 [Conf]
  13. Gurindar S. Sohi
    Single-Chip Multiprocessors: The Next Wave of Computer Architecture Innovation. [Citation Graph (0, 0)][DBLP]
    MICRO, 2004, pp:143- [Conf]
  14. Arindam Mallik, Gokhan Memik
    A Case for Clumsy Packet Processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 2004, pp:147-156 [Conf]
  15. Steven G. Dropsho, Greg Semeraro, David H. Albonesi, Grigorios Magklis, Michael L. Scott
    Dynamically Trading Frequency for Complexity in a GALS Microprocessor. [Citation Graph (0, 0)][DBLP]
    MICRO, 2004, pp:157-168 [Conf]
  16. Francisco J. Cazorla, Alex Ramírez, Mateo Valero, Enrique Fernández
    Dynamically Controlled Resource Allocation in SMT Processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 2004, pp:171-182 [Conf]
  17. Eric Tune, Rakesh Kumar, Dean M. Tullsen, Brad Calder
    Balanced Multithreading: Increasing Throughput via a Low Cost Multithreading Hierarchy. [Citation Graph (0, 0)][DBLP]
    MICRO, 2004, pp:183-194 [Conf]
  18. Rakesh Kumar, Norman P. Jouppi, Dean M. Tullsen
    Conjoined-Core Chip Multiprocessing. [Citation Graph (0, 0)][DBLP]
    MICRO, 2004, pp:195-206 [Conf]
  19. Nathan Tuck, Brad Calder, George Varghese
    Hardware and Binary Modification Support for Code Pointer Protection From Buffer Overflow. [Citation Graph (0, 0)][DBLP]
    MICRO, 2004, pp:209-220 [Conf]
  20. Jedidiah R. Crandall, Frederic T. Chong
    Minos: Control Data Attack Prevention Orthogonal to Memory Model. [Citation Graph (0, 0)][DBLP]
    MICRO, 2004, pp:221-232 [Conf]
  21. Milenko Drinic, Darko Kirovski
    A Hardware-Software Platform for Intrusion Prevention. [Citation Graph (0, 0)][DBLP]
    MICRO, 2004, pp:233-242 [Conf]
  22. Neil Vachharajani, Matthew J. Bridges, Jonathan Chang, Ram Rangan, Guilherme Ottoni, Jason A. Blome, George A. Reis, Manish Vachharajani, David I. August
    RIFLE: An Architectural Framework for User-Centric Information-Flow Security. [Citation Graph (0, 0)][DBLP]
    MICRO, 2004, pp:243-254 [Conf]
  23. Jared C. Smolens, Jangwoo Kim, James C. Hoe, Babak Falsafi
    Efficient Resource Sharing in Concurrent Error Detecting Superscalar Microarchitectures. [Citation Graph (0, 0)][DBLP]
    MICRO, 2004, pp:257-268 [Conf]
  24. Pin Zhou, Wei Liu, Long Fei, Shan Lu, Feng Qin, Yuanyuan Zhou, Samuel P. Midkiff, Josep Torrellas
    AccMon: Automatically Detecting Memory-Related Bugs via Program Counter-Based Invariants. [Citation Graph (0, 0)][DBLP]
    MICRO, 2004, pp:269-280 [Conf]
  25. Ghassan Shobaki, Kent D. Wilken
    Optimal Superblock Scheduling Using Enumeration. [Citation Graph (0, 0)][DBLP]
    MICRO, 2004, pp:283-293 [Conf]
  26. Gerolf Hoflehner, Knud Kirkegaard, Rod Skinner, Daniel M. Lavery, Yong-Fong Lee, Wei Li
    Compiler Optimizations for Transaction Processing Workloads on Itanium® Linux Systems. [Citation Graph (0, 0)][DBLP]
    MICRO, 2004, pp:294-303 [Conf]
  27. Oguz Ergin, Deniz Balkan, Kanad Ghose, Dmitry V. Ponomarev
    Register Packing: Exploiting Narrow-Width Operands for Reducing Register File Pressure. [Citation Graph (0, 0)][DBLP]
    MICRO, 2004, pp:304-315 [Conf]
  28. Bradford M. Beckmann, David A. Wood
    Managing Wire Delay in Large Chip-Multiprocessor Caches. [Citation Graph (0, 0)][DBLP]
    MICRO, 2004, pp:319-330 [Conf]
  29. Christopher Batten, Ronny Krashinsky, Steve Gerding, Krste Asanovic
    Cache Refill/Access Decoupling for Vector Machines. [Citation Graph (0, 0)][DBLP]
    MICRO, 2004, pp:331-342 [Conf]
  30. Ibrahim Hur, Calvin Lin
    Adaptive History-Based Memory Schedulers. [Citation Graph (0, 0)][DBLP]
    MICRO, 2004, pp:343-354 [Conf]
  31. Scott Rixner
    Memory Controller Optimizations for Web Servers. [Citation Graph (0, 0)][DBLP]
    MICRO, 2004, pp:355-366 [Conf]
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