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Conferences in DBLP
- Kerry Bernstein
Microarchitecture on the MOSFET Diet. [Citation Graph (0, 0)][DBLP]
MICRO, 2003, pp:3-6 [Conf]
- Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pant, Rajeev R. Rao, Toan Pham, Conrad H. Ziesler, David Blaauw, Todd M. Austin, Krisztián Flautner, Trevor N. Mudge
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation. [Citation Graph (0, 0)][DBLP]
MICRO, 2003, pp:7-18 [Conf]
- Hai Li, Chen-Yong Cher, T. N. Vijaykumar, Kaushik Roy
VSV: L2-Miss-Driven Variable Supply-Voltage Scaling for Low Power. [Citation Graph (0, 0)][DBLP]
MICRO, 2003, pp:19-28 [Conf]
- Shubhendu S. Mukherjee, Christopher Weaver, Joel S. Emer, Steven K. Reinhardt, Todd M. Austin
A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor. [Citation Graph (0, 0)][DBLP]
MICRO, 2003, pp:29-42 [Conf]
- Bradford M. Beckmann, David A. Wood
TLC: Transmission Line Caches. [Citation Graph (0, 0)][DBLP]
MICRO, 2003, pp:43-54 [Conf]
- Zeshan Chishti, Michael D. Powell, T. N. Vijaykumar
Distance Associativity for High-Performance Energy-Efficient Non-Uniform Cache Architectures. [Citation Graph (0, 0)][DBLP]
MICRO, 2003, pp:55-66 [Conf]
- Se-Hyun Yang, Babak Falsafi
Near-Optimal Precharging in High-Performance Nanoscale CMOS Caches. [Citation Graph (0, 0)][DBLP]
MICRO, 2003, pp:67-80 [Conf]
- Rakesh Kumar, Keith I. Farkas, Norman P. Jouppi, Parthasarathy Ranganathan, Dean M. Tullsen
Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction. [Citation Graph (0, 0)][DBLP]
MICRO, 2003, pp:81-92 [Conf]
- Canturk Isci, Margaret Martonosi
Runtime Power Monitoring in High-End Processors: Methodology and Empirical Data. [Citation Graph (0, 0)][DBLP]
MICRO, 2003, pp:93-104 [Conf]
- Hangsheng Wang, Li-Shiuan Peh, Sharad Malik
Power-driven Design of Router Microarchitectures in On-chip Networks. [Citation Graph (0, 0)][DBLP]
MICRO, 2003, pp:105-116 [Conf]
- Allan Hartstein, Thomas R. Puzak
Optimum Power/Performance Pipeline Depth. [Citation Graph (0, 0)][DBLP]
MICRO, 2003, pp:117-128 [Conf]
- Nathan Clark, Hongtao Zhong, Scott A. Mahlke
Processor Acceleration Through Automated Instruction Set Customization. [Citation Graph (0, 0)][DBLP]
MICRO, 2003, pp:129-140 [Conf]
- Silviu Ciricescu, Ray Essick, Brian Lucas, Phil May, Kent Moat, Jim Norris, Michael A. Schuette, Ali Saidi
The Reconfigurable Streaming Vector Processor (RSVPTM). [Citation Graph (0, 0)][DBLP]
MICRO, 2003, pp:141-150 [Conf]
- Richard A. Hankins, Trung A. Diep, Murali Annavaram, Brian Hirano, Harald Eri, Hubert Nueckel, John Paul Shen
Scaling and Charact rizing Database Workloads: Bridging the Gap between Research and Practice. [Citation Graph (0, 0)][DBLP]
MICRO, 2003, pp:151-164 [Conf]
- Michael S. Schlansker
In Memory of Bob Rau. [Citation Graph (0, 0)][DBLP]
MICRO, 2003, pp:165-168 [Conf]
- Kim M. Hazelwood, Michael D. Smith
Generational Cache Management of Code Traces in Dynamic Optimization Systems. [Citation Graph (0, 0)][DBLP]
MICRO, 2003, pp:169-179 [Conf]
- Jiwei Lu, Howard Chen, Rao Fu, Wei-Chung Hsu, Bobbie Othmer, Pen-Chung Yew, Dong-yuan Chen
The Performance of Runtime Data Cache Prefetching in a Dynamic Optimization System. [Citation Graph (0, 0)][DBLP]
MICRO, 2003, pp:180-190 [Conf]
- Leonid Baraz, Tevi Devor, Orna Etzion, Shalom Goldenberg, Alex Skaletsky, Yun Wang, Yigel Zemach
IA-32 Execution Layer: a two-phase dynamic translator designed to support IA-32 applications on Itanium-based systems. [Citation Graph (0, 0)][DBLP]
MICRO, 2003, pp:191-204 [Conf]
- Vikram S. Adve, Chris Lattner, Michael Brukman, Anand Shukla, Brian Gaeke
LLVA: A Low-level Virtual Instruction Set Architecture. [Citation Graph (0, 0)][DBLP]
MICRO, 2003, pp:205-216 [Conf]
- Ashutosh S. Dhodapkar, James E. Smith
Comparing Program Phase Detection Techniques. [Citation Graph (0, 0)][DBLP]
MICRO, 2003, pp:217-227 [Conf]
- Brian A. Fields, Rastislav Bodík, Mark D. Hill, Chris J. Newburn
Using Interaction Costs for Microarchitectural Bottleneck Analysis. [Citation Graph (0, 0)][DBLP]
MICRO, 2003, pp:228-242 [Conf]
- Daniel A. Jiménez
Fast Path-Based Neural Branch Prediction. [Citation Graph (0, 0)][DBLP]
MICRO, 2003, pp:243-252 [Conf]
- Ho-Seop Kim, James E. Smith
Hardware Support for Control Transfers in Code Caches. [Citation Graph (0, 0)][DBLP]
MICRO, 2003, pp:253-264 [Conf]
- Saisanthosh Balakrishnan, Gurindar S. Sohi
Exploiting Value Locality in Physical Register Files. [Citation Graph (0, 0)][DBLP]
MICRO, 2003, pp:265-276 [Conf]
- Ilhyun Kim, Mikko H. Lipasti
Macro-op Scheduling: Relaxing Scheduling Loop Constraints. [Citation Graph (0, 0)][DBLP]
MICRO, 2003, pp:277-290 [Conf]
- Steven Swanson, Ken Michelson, Andrew Schwerin, Mark Oskin
WaveScalar. [Citation Graph (0, 0)][DBLP]
MICRO, 2003, pp:291-302 [Conf]
- Karthikeyan Sankaralingam, Stephen W. Keckler, William R. Mark, Doug Burger
Universal Mechanisms for Data-Parallel Architectures. [Citation Graph (0, 0)][DBLP]
MICRO, 2003, pp:303-314 [Conf]
- Enric Gibert, F. Jesús Sánchez, Antonio González
Flexible Compiler-Managed L0 Buffers for Clustered VLIW Processors. [Citation Graph (0, 0)][DBLP]
MICRO, 2003, pp:315-325 [Conf]
- Alex Aletà, Josep M. Codina, Antonio González, David R. Kaeli
Instruction Replication for Clustered Microarchitectures. [Citation Graph (0, 0)][DBLP]
MICRO, 2003, pp:326-338 [Conf]
- G. Edward Suh, Dwaine E. Clarke, Blaise Gassend, Marten van Dijk, Srinivas Devadas
Efficient Memory Integrity Verification and Encryption for Secure Processors. [Citation Graph (0, 0)][DBLP]
MICRO, 2003, pp:339-350 [Conf]
- Jun Yang, Youtao Zhang, Lan Gao
Fast Secure Processor for Inhibiting Software Piracy and Tampering. [Citation Graph (0, 0)][DBLP]
MICRO, 2003, pp:351-360 [Conf]
- Stefanos Kaxiras, Georgios Keramidas
IPStash: a Power-Efficient Memory Architecture for IP-lookup. [Citation Graph (0, 0)][DBLP]
MICRO, 2003, pp:361-372 [Conf]
- Jorge García, Jesús Corbal, Llorenç Cerdà, Mateo Valero
Design and Implementation of High-Performance Memory Systems for Future Packet Buffers. [Citation Graph (0, 0)][DBLP]
MICRO, 2003, pp:373-386 [Conf]
- Ronald D. Barnes, Erik M. Nystrom, John W. Sias, Sanjay J. Patel, Nacho Navarro, Wen-mei W. Hwu
Beating in-order stalls with "flea-flicker" two-pass pipelining. [Citation Graph (0, 0)][DBLP]
MICRO, 2003, pp:387-398 [Conf]
- Simha Sethumadhavan, Rajagopalan Desikan, Doug Burger, Charles R. Moore, Stephen W. Keckler
Scalable Hardware Memory Disambiguation for High ILP Processors. [Citation Graph (0, 0)][DBLP]
MICRO, 2003, pp:399-410 [Conf]
- Il Park, Chong-liang Ooi, T. N. Vijaykumar
Reducing Design Complexity of the Load/Store Queue. [Citation Graph (0, 0)][DBLP]
MICRO, 2003, pp:411-422 [Conf]
- Haitham Akkary, Ravi Rajwar, Srikanth T. Srinivasan
Checkpoint Processing and Recovery: Towards Scalable Large Instruction Window Processors. [Citation Graph (0, 0)][DBLP]
MICRO, 2003, pp:423-0 [Conf]
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