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Conferences in DBLP

International Symposium on Microarchitecture (MICRO) (micro)
1996 (conf/micro/96)

  1. Thomas M. Conte, Sumedh W. Sathaye, Sanjeev Banerjia
    A Persistent Rescheduled-page Cache for Low Overhead Object Code Compatibility in VLIW Architectures. [Citation Graph (0, 0)][DBLP]
    MICRO, 1996, pp:4-13 [Conf]
  2. James O. Bondi, Ashwini K. Nanda, Simonjit Dutta
    Integrating a Misprediction Recovery Cache (MRC) into a Superscalar Pipeline. [Citation Graph (0, 0)][DBLP]
    MICRO, 1996, pp:14-23 [Conf]
  3. Eric Rotenberg, Steve Bennett, James E. Smith
    Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching. [Citation Graph (0, 0)][DBLP]
    MICRO, 1996, pp:24-35 [Conf]
  4. Thomas M. Conte, Kishore N. Menezes, Mary Ann Hirsch
    Accurate and Practical Profile-driven Compilation Using the Profile Buffer. [Citation Graph (0, 0)][DBLP]
    MICRO, 1996, pp:36-45 [Conf]
  5. Thomas Ball, James R. Larus
    Efficient Path Profiling. [Citation Graph (0, 0)][DBLP]
    MICRO, 1996, pp:46-57 [Conf]
  6. Chandra Chekuri, Richard Johnson, Rajeev Motwani, B. Natarajan, B. Ramakrishna Rau, Michael S. Schlansker
    Profile-driven Instruction Level Parallel Scheduling with Application to Super Blocks. [Citation Graph (0, 0)][DBLP]
    MICRO, 1996, pp:58-67 [Conf]
  7. Brian L. Deitrich, Wen-mei W. Hwu
    Speculative Hedge: Regulating Compile-time Speculation Against Profile Variations. [Citation Graph (0, 0)][DBLP]
    MICRO, 1996, pp:70-79 [Conf]
  8. Robert S. Cohn, P. Geoffrey Lowney
    Hot Cold Optimization of Large Windows/NT Applications. [Citation Graph (0, 0)][DBLP]
    MICRO, 1996, pp:80-89 [Conf]
  9. Cheng-Hsueh A. Hsieh, John C. Gyllenhaal, Wen-mei W. Hwu
    Java Bytecode to Native Code Translation: The Caffeine Prototype and Preliminary Results. [Citation Graph (0, 0)][DBLP]
    MICRO, 1996, pp:90-99 [Conf]
  10. Richard Johnson, Michael S. Schlansker
    Analysis Techniques for Predicated Code. [Citation Graph (0, 0)][DBLP]
    MICRO, 1996, pp:100-113 [Conf]
  11. David M. Gillies, Roy Dz-Ching Ju, Richard Johnson, Michael S. Schlansker
    Global Predicate Analysis and Its Application to Register Allocation. [Citation Graph (0, 0)][DBLP]
    MICRO, 1996, pp:114-125 [Conf]
  12. Daniel M. Lavery, Wen-mei W. Hwu
    Modulo Scheduling of Loops in Control-intensive Non-numeric Programs. [Citation Graph (0, 0)][DBLP]
    MICRO, 1996, pp:126-137 [Conf]
  13. Erik Jacobsen, Eric Rotenberg, James E. Smith
    Assigning Confidence to Conditional Branch Predictions. [Citation Graph (0, 0)][DBLP]
    MICRO, 1996, pp:142-152 [Conf]
  14. Scott A. Mahlke, Balas K. Natarajan
    Compiler Synthesized Dynamic Branch Prediction. [Citation Graph (0, 0)][DBLP]
    MICRO, 1996, pp:153-164 [Conf]
  15. Jim Pierce, Trevor N. Mudge
    Wrong-path Instruction Prefetching. [Citation Graph (0, 0)][DBLP]
    MICRO, 1996, pp:165-175 [Conf]
  16. Robert Yung
    Design Decisions Influencing the UltraSPARC's Instruction Fetch Architecture. [Citation Graph (0, 0)][DBLP]
    MICRO, 1996, pp:178-190 [Conf]
  17. Eric Hao, Po-Yung Chang, Marius Evers, Yale N. Patt
    Increasing the Instruction Fetch Rate via Block-structured Instruction Set Architectures. [Citation Graph (0, 0)][DBLP]
    MICRO, 1996, pp:191-200 [Conf]
  18. Thomas M. Conte, Sanjeev Banerjia, Sergei Y. Larin, Kishore N. Menezes, Sumedh W. Sathaye
    Instruction Fetch Mechanisms for VLIW Architectures with Compressed Encodings. [Citation Graph (0, 0)][DBLP]
    MICRO, 1996, pp:201-211 [Conf]
  19. Shlomit S. Pinter, Adi Yoaz
    Tango: A Hardware-Based Data Prefetching Technique for Superscalar Processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 1996, pp:214-225 [Conf]
  20. Mikko H. Lipasti, John Paul Shen
    Exceeding the Dataflow Limit via Value Prediction. [Citation Graph (0, 0)][DBLP]
    MICRO, 1996, pp:226-237 [Conf]
  21. Yiannakis Sazeides, Stamatis Vassiliadis, James E. Smith
    The Performance Potential of Data Dependence Speculation & Collapsing. [Citation Graph (0, 0)][DBLP]
    MICRO, 1996, pp:238-247 [Conf]
  22. Josep Llosa, Mateo Valero, Eduard Ayguadé
    Heuristics for Register-Constrained Software Pipelining. [Citation Graph (0, 0)][DBLP]
    MICRO, 1996, pp:250-261 [Conf]
  23. Mark G. Stoodley, Corinna G. Lee
    Software Pipelining Loops with Conditional Branches. [Citation Graph (0, 0)][DBLP]
    MICRO, 1996, pp:262-273 [Conf]
  24. Michael E. Wolf, Dror E. Maydan, Ding-Kai Chen
    Combining Loop Transformations Considering Caches and Scheduling. [Citation Graph (0, 0)][DBLP]
    MICRO, 1996, pp:274-286 [Conf]
  25. Eric Schnarr, James R. Larus
    Instruction Scheduling and Executable Editing. [Citation Graph (0, 0)][DBLP]
    MICRO, 1996, pp:288-297 [Conf]
  26. David A. Dunn, Wei-Chung Hsu
    Instruction Scheduling for the HP PA-8000. [Citation Graph (0, 0)][DBLP]
    MICRO, 1996, pp:298-307 [Conf]
  27. Santosh G. Abraham, Vinod Kathail, Brian L. Deitrich
    Meld Scheduling: Relaxing Scheduling Constraints Across Region Boundaries. [Citation Graph (0, 0)][DBLP]
    MICRO, 1996, pp:308-321 [Conf]
  28. Joseph A. Fisher, Paolo Faraboschi, Giuseppe Desoli
    Custom-fit Processors: Letting Applications Define Architectures. [Citation Graph (0, 0)][DBLP]
    MICRO, 1996, pp:324-335 [Conf]
  29. Anne M. Holler
    Optimization for a Superscalar Out-of-Order Machine. [Citation Graph (0, 0)][DBLP]
    MICRO, 1996, pp:336-348 [Conf]
  30. John C. Gyllenhaal, Wen-mei W. Hwu, B. Ramakrishna Rau
    Optimization of Machine Descriptions for Efficient Use. [Citation Graph (0, 0)][DBLP]
    MICRO, 1996, pp:349-358 [Conf]
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