Conferences in DBLP
K. Lall , J. William Atwood A microprogrammed interpreter for concurrent Euclid. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen J. Allan Functional languages in microcode compilers. [Citation Graph (0, 0)][DBLP ] Conf ] Fadi N. Sibai , L. Watson , M. Lu Design and performance measurements of a parallel machine for the unification algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] M. Brady A direct execution architecture for Prolog? [Citation Graph (0, 0)][DBLP ] Conf ] Hans Mulder , R. J. Portier Cost-effective design of application specific VLIW processors using the SCARCE framework. [Citation Graph (0, 0)][DBLP ] Conf ] Toshio Nakatani , Kemal Ebcioglu "Combining" as a compilation technique for VLIW architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Patrick M. Lenders , Heiko Schröder , Peter E. Strazdins Microprogramming instruction systolic arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Rubin A. Parekhji , N. K. Nanda Design methodology and microdiagnostics development for a self-checking microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] L. A. Kovacs , S. F. Gilli Extended microcode error checking on a pipelined machine. [Citation Graph (0, 0)][DBLP ] Conf ] Yashwant K. Malaiya On inherent untestability of unaugmented microprogrammed control. [Citation Graph (0, 0)][DBLP ] Conf ] Giacomo R. Sechi Abstract computing machines. [Citation Graph (0, 0)][DBLP ] Conf ] Vicki H. Allan Peephole optimization as a targeting and coupling tool. [Citation Graph (0, 0)][DBLP ] Conf ] R. Katti , L. Manwaring Information structures in language directed architectures. [Citation Graph (0, 0)][DBLP ] Conf ] A. J. van de Goor , Henk Corporaal DOAS: an object oriented architecture supporting secure languages. [Citation Graph (0, 0)][DBLP ] Conf ] D. Liu , Wolfgang K. Giloi A loop optimization technique based on scheduling table. [Citation Graph (0, 0)][DBLP ] Conf ] Franco Gasperoni , Uwe Schwiegelshohn , Kemal Ebcioglu On optimal loop parallelization. [Citation Graph (0, 0)][DBLP ] Conf ] E. Sanchez A microprogramming teaching environment using the Macintosh computer. [Citation Graph (0, 0)][DBLP ] Conf ] A. Parker , James O. Hamblen A VLSI based microprogramming evaluation system to support an instructional laboratory. [Citation Graph (0, 0)][DBLP ] Conf ] Sergio D'Angelo , Giacomo R. Sechi Definition of elementary arithmetic operations by using ACM. [Citation Graph (0, 0)][DBLP ] Conf ] Pantung Wijaya , Vicki H. Allan Incremental foresighted local compaction. [Citation Graph (0, 0)][DBLP ] Conf ] J. L. Linn , C. D. Ardoin All example of using pseudofields to eliminate version shuffling in horizontal code compaction. [Citation Graph (0, 0)][DBLP ] Conf ] M. C. Ertem Multiple operation memory structures. [Citation Graph (0, 0)][DBLP ] Conf ] P.-H. Chang , Wen-mei W. Hwu Forward semantic: a compiler-assisted instruction fetch method for heavily pipelined processors. [Citation Graph (0, 0)][DBLP ] Conf ] Jong-Jiann Shieh , Christos A. Papachristou On reordering instruction streams for pipelined computers. [Citation Graph (0, 0)][DBLP ] Conf ] Colin C. Charlton , D. Jackson , Paul H. Leng A functional model of clocked microarchitectures. [Citation Graph (0, 0)][DBLP ] Conf ] Yale N. Patt Microarchitecture choices (implementation of the VAX). [Citation Graph (0, 0)][DBLP ] Conf ] John A. Nestor , Bassel Soudan , Zubair Mayet MIES: a microarchitecture design tool. [Citation Graph (0, 0)][DBLP ] Conf ] Hans Mulder , P. Stravers A flexible VLSI core for an adaptable architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Edil S. Tavares Fernandes A model for microarchitecture structure evaluation. [Citation Graph (0, 0)][DBLP ] Conf ] Michael J. Flynn , R. I. Winner ASIC microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Monica Alderighi , Giacomo R. Sechi , Roberto Vaccaro , Lorenzo Verdoscia A computing unit for FFP function evaluation in support of correctness proofs. [Citation Graph (0, 0)][DBLP ] Conf ] 