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Conferences in DBLP
- Michael J. Flynn
Instruction sets and their implementations. [Citation Graph (0, 0)][DBLP]
MICRO, 1990, pp:1-6 [Conf]
- Marco Danelutto, Marco Vanneschi
VLIW-in-the-large: a model for fine grain parallelism exploitation on distributed memory multiprocessors. [Citation Graph (0, 0)][DBLP]
MICRO, 1990, pp:7-16 [Conf]
- Bogong Su, Jian Wang, Zhizhong Tang, Wei Zhao, Yimin Wu
A software pipelining based VLIW architecture and optimizing compiler. [Citation Graph (0, 0)][DBLP]
MICRO, 1990, pp:17-27 [Conf]
- Rajiv Gupta
A fine-grained MIMD architecture based upon register channels. [Citation Graph (0, 0)][DBLP]
MICRO, 1990, pp:28-37 [Conf]
- Soo-Mook Moon, Scott D. Carson, Ashok K. Agrawala
Hardware implementation of a general multi-way jump mechanism. [Citation Graph (0, 0)][DBLP]
MICRO, 1990, pp:38-45 [Conf]
- Reese B. Jones, Vicki H. Allan
Software pipelining: a comparison and improvement. [Citation Graph (0, 0)][DBLP]
MICRO, 1990, pp:46-56 [Conf]
- Toshio Nakatani, Kemal Ebcioglu
Using a lookahead window in a compaction-based parallelizing compiler. [Citation Graph (0, 0)][DBLP]
MICRO, 1990, pp:57-68 [Conf]
- Alexandru Nicolau, Roni Potasman
Realistic scheduling: compaction for pipelined architectures. [Citation Graph (0, 0)][DBLP]
MICRO, 1990, pp:69-79 [Conf]
- Alessandro De Gloria, Paolo Faraboschi
An evaluation system for application specific architectures. [Citation Graph (0, 0)][DBLP]
MICRO, 1990, pp:80-89 [Conf]
- J. M. Mulder, R. J. Portier, A. Srivastava
A framework for high-speed controller design. [Citation Graph (0, 0)][DBLP]
MICRO, 1990, pp:90-96 [Conf]
- Paul Kenyon, Prathima Agrawal, Sharad C. Seth
High-level microprogramming: an optimizing C compiler for a processing element of a CAD accelerator. [Citation Graph (0, 0)][DBLP]
MICRO, 1990, pp:97-106 [Conf]
- Philip H. Sweany, Steven J. Beaty
Post-compaction register assignment in a retargetable compiler. [Citation Graph (0, 0)][DBLP]
MICRO, 1990, pp:107-116 [Conf]
- Steven J. Beaty, Darrell Whitley, Gearold Johnson
Motivation and framework for using genetic algorithms for microcode compaction. [Citation Graph (0, 0)][DBLP]
MICRO, 1990, pp:117-124 [Conf]
- S. ShouHan Wang, Augustus K. Uht
Ideograph/Ideogram: framework/hardware for eager evaluation. [Citation Graph (0, 0)][DBLP]
MICRO, 1990, pp:125-134 [Conf]
- Jong-Jiann Shieh, Christos A. Papachristou
An instruction reoderer for pipelined computers. [Citation Graph (0, 0)][DBLP]
MICRO, 1990, pp:135-142 [Conf]
- Feipei Lai, Hung-Chang Lee, Chun-Luh Lee
Optimization on instruction reorganization. [Citation Graph (0, 0)][DBLP]
MICRO, 1990, pp:143-148 [Conf]
- David Binger, David Knapp
Automatic synthesis of a dual-PLA controller with a counter. [Citation Graph (0, 0)][DBLP]
MICRO, 1990, pp:149-157 [Conf]
- Forrest Brewer, Barry M. Pangrle, Andrew Seawright
Interconnection synthesis with geometric constraints. [Citation Graph (0, 0)][DBLP]
MICRO, 1990, pp:158-165 [Conf]
- Farhad Mavaddat, M. Mahmood, Mantis H. M. Cheng
An application of L systems to local microcode synthesis. [Citation Graph (0, 0)][DBLP]
MICRO, 1990, pp:166-175 [Conf]
- Tsang-Ling Sheu, Yuan-Bao Shieh, Woei Lin
The selection of optimal cache lines for microprocessor-based controllers. [Citation Graph (0, 0)][DBLP]
MICRO, 1990, pp:183-192 [Conf]
- Arvin Park, Matthew K. Farrens
Address compression through base register caching. [Citation Graph (0, 0)][DBLP]
MICRO, 1990, pp:193-199 [Conf]
- Feipei Lai, Chyuan-Yow Wu, Tai-Ming Parng
A memory management unit and cache controller for the MARS system. [Citation Graph (0, 0)][DBLP]
MICRO, 1990, pp:200-208 [Conf]
- Matthew K. Farrens, Andrew R. Pleszkun
An evaluation of functional unit lengths for single-chip processors. [Citation Graph (0, 0)][DBLP]
MICRO, 1990, pp:209-215 [Conf]
- Lawrence Rauchwerger, P. Michael Farmwald
A multiple floating point coprocessor architecture. [Citation Graph (0, 0)][DBLP]
MICRO, 1990, pp:216-222 [Conf]
- Reuven Bakalash, Zhong Xu
A barrel shift microsystem for parallel processing. [Citation Graph (0, 0)][DBLP]
MICRO, 1990, pp:223-229 [Conf]
- Beverly Gocal
PRISM architecture: parallel and pipeline features. [Citation Graph (0, 0)][DBLP]
MICRO, 1990, pp:230-236 [Conf]
- L. Campanale, M. De Blasi, A. Gentile, F. Greco
Topologies for the parallel backtracking Prolog engine. [Citation Graph (0, 0)][DBLP]
MICRO, 1990, pp:237-242 [Conf]
- Christian Iseli, Eduardo Sanchez
A high-level microprogrammed processor. [Citation Graph (0, 0)][DBLP]
MICRO, 1990, pp:244-251 [Conf]
- Djahida Smati, Jerry Hwang, Christos A. Papachristou
SMDSS - a structured microcode development and simulation system. [Citation Graph (0, 0)][DBLP]
MICRO, 1990, pp:252-259 [Conf]
- S. Hwang, Rochit Rajsuman, Yashwant K. Malaiya
On the testing of microprogrammed processor. [Citation Graph (0, 0)][DBLP]
MICRO, 1990, pp:260-266 [Conf]
- C. Hwa Chang, Hammad K. Azzam
A weighted technique for programmable logic devices minimization. [Citation Graph (0, 0)][DBLP]
MICRO, 1990, pp:267-274 [Conf]
- Liwen Shih
Microprogramming heritage of RISC design. [Citation Graph (0, 0)][DBLP]
MICRO, 1990, pp:275-280 [Conf]
- Sunil R. Das, Amiya Nayak
A survey on bit dimension optimization strategies of microprograms. [Citation Graph (0, 0)][DBLP]
MICRO, 1990, pp:281-291 [Conf]
- Monica Alderighi, Giacomo R. Sechi
A model of a microprogrammed functional-oriented computing unit. [Citation Graph (0, 0)][DBLP]
MICRO, 1990, pp:292-298 [Conf]
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